BaseCPU.py revision 8839
15222Sksewell@umich.edu# Copyright (c) 2012 ARM Limited 25222Sksewell@umich.edu# All rights reserved. 35222Sksewell@umich.edu# 45222Sksewell@umich.edu# The license below extends only to copyright in the software and shall 55222Sksewell@umich.edu# not be construed as granting a license to any other intellectual 65222Sksewell@umich.edu# property including but not limited to intellectual property relating 75222Sksewell@umich.edu# to a hardware implementation of the functionality of the software 85222Sksewell@umich.edu# licensed hereunder. You may use the software subject to the license 95222Sksewell@umich.edu# terms below provided that you ensure that this notice is replicated 105222Sksewell@umich.edu# unmodified and in its entirety in all distributions of the software, 115222Sksewell@umich.edu# modified or unmodified, in source code or in binary form. 125222Sksewell@umich.edu# 135222Sksewell@umich.edu# Copyright (c) 2005-2008 The Regents of The University of Michigan 145222Sksewell@umich.edu# Copyright (c) 2011 Regents of the University of California 155222Sksewell@umich.edu# All rights reserved. 165222Sksewell@umich.edu# 175222Sksewell@umich.edu# Redistribution and use in source and binary forms, with or without 185222Sksewell@umich.edu# modification, are permitted provided that the following conditions are 195222Sksewell@umich.edu# met: redistributions of source code must retain the above copyright 205222Sksewell@umich.edu# notice, this list of conditions and the following disclaimer; 215222Sksewell@umich.edu# redistributions in binary form must reproduce the above copyright 225222Sksewell@umich.edu# notice, this list of conditions and the following disclaimer in the 235222Sksewell@umich.edu# documentation and/or other materials provided with the distribution; 245222Sksewell@umich.edu# neither the name of the copyright holders nor the names of its 255222Sksewell@umich.edu# contributors may be used to endorse or promote products derived from 265222Sksewell@umich.edu# this software without specific prior written permission. 275222Sksewell@umich.edu# 285222Sksewell@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 295222Sksewell@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 305222Sksewell@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 315222Sksewell@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 325222Sksewell@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 335222Sksewell@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 345222Sksewell@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 355222Sksewell@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 365222Sksewell@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 375222Sksewell@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 385222Sksewell@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 395222Sksewell@umich.edu# 405222Sksewell@umich.edu# Authors: Nathan Binkert 415222Sksewell@umich.edu# Rick Strong 425222Sksewell@umich.edu# Andreas Hansson 435222Sksewell@umich.edu 445222Sksewell@umich.eduimport sys 455222Sksewell@umich.edu 465222Sksewell@umich.edufrom m5.defines import buildEnv 475222Sksewell@umich.edufrom m5.params import * 485222Sksewell@umich.edufrom m5.proxy import * 495222Sksewell@umich.edu 505222Sksewell@umich.edufrom Bus import Bus 515222Sksewell@umich.edufrom InstTracer import InstTracer 525222Sksewell@umich.edufrom ExeTracer import ExeTracer 535222Sksewell@umich.edufrom MemObject import MemObject 545222Sksewell@umich.edu 555222Sksewell@umich.edudefault_tracer = ExeTracer() 565222Sksewell@umich.edu 575222Sksewell@umich.eduif buildEnv['TARGET_ISA'] == 'alpha': 585222Sksewell@umich.edu from AlphaTLB import AlphaDTB, AlphaITB 595222Sksewell@umich.edu from AlphaInterrupts import AlphaInterrupts 605222Sksewell@umich.eduelif buildEnv['TARGET_ISA'] == 'sparc': 615222Sksewell@umich.edu from SparcTLB import SparcTLB 625222Sksewell@umich.edu from SparcInterrupts import SparcInterrupts 635222Sksewell@umich.eduelif buildEnv['TARGET_ISA'] == 'x86': 645222Sksewell@umich.edu from X86TLB import X86TLB 655222Sksewell@umich.edu from X86LocalApic import X86LocalApic 665222Sksewell@umich.eduelif buildEnv['TARGET_ISA'] == 'mips': 675222Sksewell@umich.edu from MipsTLB import MipsTLB 685222Sksewell@umich.edu from MipsInterrupts import MipsInterrupts 695222Sksewell@umich.eduelif buildEnv['TARGET_ISA'] == 'arm': 705222Sksewell@umich.edu from ArmTLB import ArmTLB 715222Sksewell@umich.edu from ArmInterrupts import ArmInterrupts 725222Sksewell@umich.eduelif buildEnv['TARGET_ISA'] == 'power': 735222Sksewell@umich.edu from PowerTLB import PowerTLB 745222Sksewell@umich.edu from PowerInterrupts import PowerInterrupts 755222Sksewell@umich.edu 765222Sksewell@umich.educlass BaseCPU(MemObject): 775222Sksewell@umich.edu type = 'BaseCPU' 785222Sksewell@umich.edu abstract = True 795222Sksewell@umich.edu 805222Sksewell@umich.edu system = Param.System(Parent.any, "system object") 815222Sksewell@umich.edu cpu_id = Param.Int(-1, "CPU identifier") 825222Sksewell@umich.edu numThreads = Param.Unsigned(1, "number of HW thread contexts") 835222Sksewell@umich.edu 845222Sksewell@umich.edu function_trace = Param.Bool(False, "Enable function trace") 855222Sksewell@umich.edu function_trace_start = Param.Tick(0, "Cycle to start function trace") 865222Sksewell@umich.edu 875222Sksewell@umich.edu checker = Param.BaseCPU(NULL, "checker CPU") 885222Sksewell@umich.edu 895222Sksewell@umich.edu do_checkpoint_insts = Param.Bool(True, 905222Sksewell@umich.edu "enable checkpoint pseudo instructions") 915222Sksewell@umich.edu do_statistics_insts = Param.Bool(True, 925222Sksewell@umich.edu "enable statistics pseudo instructions") 935222Sksewell@umich.edu 945222Sksewell@umich.edu profile = Param.Latency('0ns', "trace the kernel stack") 955222Sksewell@umich.edu do_quiesce = Param.Bool(True, "enable quiesce instructions") 965222Sksewell@umich.edu 975222Sksewell@umich.edu workload = VectorParam.Process([], "processes to run") 985222Sksewell@umich.edu 995222Sksewell@umich.edu if buildEnv['TARGET_ISA'] == 'sparc': 1005222Sksewell@umich.edu dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 1015222Sksewell@umich.edu itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 1025222Sksewell@umich.edu interrupts = Param.SparcInterrupts( 1035222Sksewell@umich.edu SparcInterrupts(), "Interrupt Controller") 1045222Sksewell@umich.edu elif buildEnv['TARGET_ISA'] == 'alpha': 1055222Sksewell@umich.edu dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 1065222Sksewell@umich.edu itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 1075222Sksewell@umich.edu interrupts = Param.AlphaInterrupts( 1085222Sksewell@umich.edu AlphaInterrupts(), "Interrupt Controller") 1095222Sksewell@umich.edu elif buildEnv['TARGET_ISA'] == 'x86': 1105222Sksewell@umich.edu dtb = Param.X86TLB(X86TLB(), "Data TLB") 1115222Sksewell@umich.edu itb = Param.X86TLB(X86TLB(), "Instruction TLB") 1125222Sksewell@umich.edu _localApic = X86LocalApic(pio_addr=0x2000000000000000) 1135222Sksewell@umich.edu interrupts = Param.X86LocalApic(_localApic, "Interrupt Controller") 1145222Sksewell@umich.edu elif buildEnv['TARGET_ISA'] == 'mips': 1155222Sksewell@umich.edu dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 1165222Sksewell@umich.edu itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 1175222Sksewell@umich.edu interrupts = Param.MipsInterrupts( 1185222Sksewell@umich.edu MipsInterrupts(), "Interrupt Controller") 1195222Sksewell@umich.edu elif buildEnv['TARGET_ISA'] == 'arm': 1205222Sksewell@umich.edu dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 1215222Sksewell@umich.edu itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 1225222Sksewell@umich.edu interrupts = Param.ArmInterrupts( 1235222Sksewell@umich.edu ArmInterrupts(), "Interrupt Controller") 1245222Sksewell@umich.edu elif buildEnv['TARGET_ISA'] == 'power': 1255222Sksewell@umich.edu UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 1265222Sksewell@umich.edu dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 1275222Sksewell@umich.edu itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 1285222Sksewell@umich.edu interrupts = Param.PowerInterrupts( 1295222Sksewell@umich.edu PowerInterrupts(), "Interrupt Controller") 1305222Sksewell@umich.edu else: 1315222Sksewell@umich.edu print "Don't know what TLB to use for ISA %s" % \ 1325222Sksewell@umich.edu buildEnv['TARGET_ISA'] 1335222Sksewell@umich.edu sys.exit(1) 1345222Sksewell@umich.edu 1355222Sksewell@umich.edu max_insts_all_threads = Param.Counter(0, 1365222Sksewell@umich.edu "terminate when all threads have reached this inst count") 1375222Sksewell@umich.edu max_insts_any_thread = Param.Counter(0, 1385222Sksewell@umich.edu "terminate when any thread reaches this inst count") 1395222Sksewell@umich.edu max_loads_all_threads = Param.Counter(0, 1405222Sksewell@umich.edu "terminate when all threads have reached this load count") 1415222Sksewell@umich.edu max_loads_any_thread = Param.Counter(0, 1425222Sksewell@umich.edu "terminate when any thread reaches this load count") 1435222Sksewell@umich.edu progress_interval = Param.Tick(0, 1445222Sksewell@umich.edu "interval to print out the progress message") 1455222Sksewell@umich.edu 1465222Sksewell@umich.edu defer_registration = Param.Bool(False, 1475222Sksewell@umich.edu "defer registration with system (for sampling)") 1485222Sksewell@umich.edu 1495222Sksewell@umich.edu clock = Param.Clock('1t', "clock speed") 1505222Sksewell@umich.edu phase = Param.Latency('0ns', "clock phase") 1515222Sksewell@umich.edu 1525222Sksewell@umich.edu tracer = Param.InstTracer(default_tracer, "Instruction tracer") 1535222Sksewell@umich.edu 1545222Sksewell@umich.edu icache_port = MasterPort("Instruction Port") 1555222Sksewell@umich.edu dcache_port = MasterPort("Data Port") 1565222Sksewell@umich.edu _cached_ports = ['icache_port', 'dcache_port'] 1575222Sksewell@umich.edu 1585222Sksewell@umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 1595222Sksewell@umich.edu _cached_ports += ["itb.walker.port", "dtb.walker.port"] 1605222Sksewell@umich.edu 1615222Sksewell@umich.edu _uncached_slave_ports = [] 1625222Sksewell@umich.edu _uncached_master_ports = [] 1635222Sksewell@umich.edu if buildEnv['TARGET_ISA'] == 'x86': 1645222Sksewell@umich.edu _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"] 1655222Sksewell@umich.edu _uncached_master_ports += ["interrupts.int_master"] 1665222Sksewell@umich.edu 1675222Sksewell@umich.edu def connectCachedPorts(self, bus): 1685222Sksewell@umich.edu for p in self._cached_ports: 1695222Sksewell@umich.edu exec('self.%s = bus.slave' % p) 1705222Sksewell@umich.edu 1715222Sksewell@umich.edu def connectUncachedPorts(self, bus): 1725222Sksewell@umich.edu for p in self._uncached_slave_ports: 1735222Sksewell@umich.edu exec('self.%s = bus.master' % p) 1745222Sksewell@umich.edu for p in self._uncached_master_ports: 1755222Sksewell@umich.edu exec('self.%s = bus.slave' % p) 1765222Sksewell@umich.edu 1775222Sksewell@umich.edu def connectAllPorts(self, cached_bus, uncached_bus = None): 1785222Sksewell@umich.edu self.connectCachedPorts(cached_bus) 1795222Sksewell@umich.edu if not uncached_bus: 1805222Sksewell@umich.edu uncached_bus = cached_bus 1815222Sksewell@umich.edu self.connectUncachedPorts(uncached_bus) 1825222Sksewell@umich.edu 1835222Sksewell@umich.edu def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 1845222Sksewell@umich.edu self.icache = ic 1855222Sksewell@umich.edu self.dcache = dc 1865222Sksewell@umich.edu self.icache_port = ic.cpu_side 1875222Sksewell@umich.edu self.dcache_port = dc.cpu_side 1885222Sksewell@umich.edu self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 1895222Sksewell@umich.edu if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 1905222Sksewell@umich.edu if iwc and dwc: 1915222Sksewell@umich.edu self.itb_walker_cache = iwc 1925222Sksewell@umich.edu self.dtb_walker_cache = dwc 1935222Sksewell@umich.edu self.itb.walker.port = iwc.cpu_side 1945222Sksewell@umich.edu self.dtb.walker.port = dwc.cpu_side 1955222Sksewell@umich.edu self._cached_ports += ["itb_walker_cache.mem_side", \ 1965222Sksewell@umich.edu "dtb_walker_cache.mem_side"] 1975222Sksewell@umich.edu else: 1985222Sksewell@umich.edu self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 1995222Sksewell@umich.edu # Checker doesn't need its own tlb caches because it does 2005222Sksewell@umich.edu # functional accesses only 2015222Sksewell@umich.edu if buildEnv['USE_CHECKER']: 2025222Sksewell@umich.edu self._cached_ports += ["checker.itb.walker.port", \ 2035222Sksewell@umich.edu "checker.dtb.walker.port"] 2045222Sksewell@umich.edu 2055222Sksewell@umich.edu def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 2065222Sksewell@umich.edu self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 2075222Sksewell@umich.edu self.toL2Bus = Bus() 2085222Sksewell@umich.edu self.connectCachedPorts(self.toL2Bus) 2095222Sksewell@umich.edu self.l2cache = l2c 2105222Sksewell@umich.edu self.toL2Bus.master = self.l2cache.cpu_side 2115222Sksewell@umich.edu self._cached_ports = ['l2cache.mem_side'] 2125222Sksewell@umich.edu