BaseCPU.py revision 8839
1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2005-2008 The Regents of The University of Michigan 14# Copyright (c) 2011 Regents of the University of California 15# All rights reserved. 16# 17# Redistribution and use in source and binary forms, with or without 18# modification, are permitted provided that the following conditions are 19# met: redistributions of source code must retain the above copyright 20# notice, this list of conditions and the following disclaimer; 21# redistributions in binary form must reproduce the above copyright 22# notice, this list of conditions and the following disclaimer in the 23# documentation and/or other materials provided with the distribution; 24# neither the name of the copyright holders nor the names of its 25# contributors may be used to endorse or promote products derived from 26# this software without specific prior written permission. 27# 28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39# 40# Authors: Nathan Binkert 41# Rick Strong 42# Andreas Hansson 43 44import sys 45 46from m5.defines import buildEnv 47from m5.params import * 48from m5.proxy import * 49 50from Bus import Bus 51from InstTracer import InstTracer 52from ExeTracer import ExeTracer 53from MemObject import MemObject 54 55default_tracer = ExeTracer() 56 57if buildEnv['TARGET_ISA'] == 'alpha': 58 from AlphaTLB import AlphaDTB, AlphaITB 59 from AlphaInterrupts import AlphaInterrupts 60elif buildEnv['TARGET_ISA'] == 'sparc': 61 from SparcTLB import SparcTLB 62 from SparcInterrupts import SparcInterrupts 63elif buildEnv['TARGET_ISA'] == 'x86': 64 from X86TLB import X86TLB 65 from X86LocalApic import X86LocalApic 66elif buildEnv['TARGET_ISA'] == 'mips': 67 from MipsTLB import MipsTLB 68 from MipsInterrupts import MipsInterrupts 69elif buildEnv['TARGET_ISA'] == 'arm': 70 from ArmTLB import ArmTLB 71 from ArmInterrupts import ArmInterrupts 72elif buildEnv['TARGET_ISA'] == 'power': 73 from PowerTLB import PowerTLB 74 from PowerInterrupts import PowerInterrupts 75 76class BaseCPU(MemObject): 77 type = 'BaseCPU' 78 abstract = True 79 80 system = Param.System(Parent.any, "system object") 81 cpu_id = Param.Int(-1, "CPU identifier") 82 numThreads = Param.Unsigned(1, "number of HW thread contexts") 83 84 function_trace = Param.Bool(False, "Enable function trace") 85 function_trace_start = Param.Tick(0, "Cycle to start function trace") 86 87 checker = Param.BaseCPU(NULL, "checker CPU") 88 89 do_checkpoint_insts = Param.Bool(True, 90 "enable checkpoint pseudo instructions") 91 do_statistics_insts = Param.Bool(True, 92 "enable statistics pseudo instructions") 93 94 profile = Param.Latency('0ns', "trace the kernel stack") 95 do_quiesce = Param.Bool(True, "enable quiesce instructions") 96 97 workload = VectorParam.Process([], "processes to run") 98 99 if buildEnv['TARGET_ISA'] == 'sparc': 100 dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 101 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") 102 interrupts = Param.SparcInterrupts( 103 SparcInterrupts(), "Interrupt Controller") 104 elif buildEnv['TARGET_ISA'] == 'alpha': 105 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 106 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") 107 interrupts = Param.AlphaInterrupts( 108 AlphaInterrupts(), "Interrupt Controller") 109 elif buildEnv['TARGET_ISA'] == 'x86': 110 dtb = Param.X86TLB(X86TLB(), "Data TLB") 111 itb = Param.X86TLB(X86TLB(), "Instruction TLB") 112 _localApic = X86LocalApic(pio_addr=0x2000000000000000) 113 interrupts = Param.X86LocalApic(_localApic, "Interrupt Controller") 114 elif buildEnv['TARGET_ISA'] == 'mips': 115 dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 116 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") 117 interrupts = Param.MipsInterrupts( 118 MipsInterrupts(), "Interrupt Controller") 119 elif buildEnv['TARGET_ISA'] == 'arm': 120 dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 121 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") 122 interrupts = Param.ArmInterrupts( 123 ArmInterrupts(), "Interrupt Controller") 124 elif buildEnv['TARGET_ISA'] == 'power': 125 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 126 dtb = Param.PowerTLB(PowerTLB(), "Data TLB") 127 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB") 128 interrupts = Param.PowerInterrupts( 129 PowerInterrupts(), "Interrupt Controller") 130 else: 131 print "Don't know what TLB to use for ISA %s" % \ 132 buildEnv['TARGET_ISA'] 133 sys.exit(1) 134 135 max_insts_all_threads = Param.Counter(0, 136 "terminate when all threads have reached this inst count") 137 max_insts_any_thread = Param.Counter(0, 138 "terminate when any thread reaches this inst count") 139 max_loads_all_threads = Param.Counter(0, 140 "terminate when all threads have reached this load count") 141 max_loads_any_thread = Param.Counter(0, 142 "terminate when any thread reaches this load count") 143 progress_interval = Param.Tick(0, 144 "interval to print out the progress message") 145 146 defer_registration = Param.Bool(False, 147 "defer registration with system (for sampling)") 148 149 clock = Param.Clock('1t', "clock speed") 150 phase = Param.Latency('0ns', "clock phase") 151 152 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 153 154 icache_port = MasterPort("Instruction Port") 155 dcache_port = MasterPort("Data Port") 156 _cached_ports = ['icache_port', 'dcache_port'] 157 158 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 159 _cached_ports += ["itb.walker.port", "dtb.walker.port"] 160 161 _uncached_slave_ports = [] 162 _uncached_master_ports = [] 163 if buildEnv['TARGET_ISA'] == 'x86': 164 _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"] 165 _uncached_master_ports += ["interrupts.int_master"] 166 167 def connectCachedPorts(self, bus): 168 for p in self._cached_ports: 169 exec('self.%s = bus.slave' % p) 170 171 def connectUncachedPorts(self, bus): 172 for p in self._uncached_slave_ports: 173 exec('self.%s = bus.master' % p) 174 for p in self._uncached_master_ports: 175 exec('self.%s = bus.slave' % p) 176 177 def connectAllPorts(self, cached_bus, uncached_bus = None): 178 self.connectCachedPorts(cached_bus) 179 if not uncached_bus: 180 uncached_bus = cached_bus 181 self.connectUncachedPorts(uncached_bus) 182 183 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 184 self.icache = ic 185 self.dcache = dc 186 self.icache_port = ic.cpu_side 187 self.dcache_port = dc.cpu_side 188 self._cached_ports = ['icache.mem_side', 'dcache.mem_side'] 189 if buildEnv['TARGET_ISA'] in ['x86', 'arm']: 190 if iwc and dwc: 191 self.itb_walker_cache = iwc 192 self.dtb_walker_cache = dwc 193 self.itb.walker.port = iwc.cpu_side 194 self.dtb.walker.port = dwc.cpu_side 195 self._cached_ports += ["itb_walker_cache.mem_side", \ 196 "dtb_walker_cache.mem_side"] 197 else: 198 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 199 # Checker doesn't need its own tlb caches because it does 200 # functional accesses only 201 if buildEnv['USE_CHECKER']: 202 self._cached_ports += ["checker.itb.walker.port", \ 203 "checker.dtb.walker.port"] 204 205 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): 206 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) 207 self.toL2Bus = Bus() 208 self.connectCachedPorts(self.toL2Bus) 209 self.l2cache = l2c 210 self.toL2Bus.master = self.l2cache.cpu_side 211 self._cached_ports = ['l2cache.mem_side'] 212