BaseCPU.py revision 4486
16145Snate@binkert.org# Copyright (c) 2005-2007 The Regents of The University of Michigan 26145Snate@binkert.org# All rights reserved. 36145Snate@binkert.org# 46145Snate@binkert.org# Redistribution and use in source and binary forms, with or without 56145Snate@binkert.org# modification, are permitted provided that the following conditions are 66145Snate@binkert.org# met: redistributions of source code must retain the above copyright 76145Snate@binkert.org# notice, this list of conditions and the following disclaimer; 86145Snate@binkert.org# redistributions in binary form must reproduce the above copyright 96145Snate@binkert.org# notice, this list of conditions and the following disclaimer in the 106145Snate@binkert.org# documentation and/or other materials provided with the distribution; 116145Snate@binkert.org# neither the name of the copyright holders nor the names of its 126145Snate@binkert.org# contributors may be used to endorse or promote products derived from 136145Snate@binkert.org# this software without specific prior written permission. 146145Snate@binkert.org# 156145Snate@binkert.org# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166145Snate@binkert.org# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176145Snate@binkert.org# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186145Snate@binkert.org# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196145Snate@binkert.org# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206145Snate@binkert.org# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216145Snate@binkert.org# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226145Snate@binkert.org# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236145Snate@binkert.org# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246145Snate@binkert.org# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256145Snate@binkert.org# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266145Snate@binkert.org# 276145Snate@binkert.org# Authors: Nathan Binkert 286145Snate@binkert.org 297039Snate@binkert.orgfrom m5.SimObject import SimObject 307039Snate@binkert.orgfrom m5.params import * 316145Snate@binkert.orgfrom m5.proxy import * 327039Snate@binkert.orgfrom m5 import build_env 337039Snate@binkert.orgfrom Bus import Bus 346154Snate@binkert.orgimport sys 357039Snate@binkert.org 367039Snate@binkert.orgif build_env['FULL_SYSTEM']: 377039Snate@binkert.org if build_env['TARGET_ISA'] == 'alpha': 386145Snate@binkert.org from AlphaTLB import AlphaDTB, AlphaITB 396145Snate@binkert.org 406145Snate@binkert.org if build_env['TARGET_ISA'] == 'sparc': 417039Snate@binkert.org from SparcTLB import SparcDTB, SparcITB 427039Snate@binkert.org 436145Snate@binkert.orgclass BaseCPU(SimObject): 447039Snate@binkert.org type = 'BaseCPU' 456145Snate@binkert.org abstract = True 466145Snate@binkert.org 476145Snate@binkert.org system = Param.System(Parent.any, "system object") 486145Snate@binkert.org cpu_id = Param.Int("CPU identifier") 497039Snate@binkert.org 507039Snate@binkert.org if build_env['FULL_SYSTEM']: 516145Snate@binkert.org do_quiesce = Param.Bool(True, "enable quiesce instructions") 527039Snate@binkert.org do_checkpoint_insts = Param.Bool(True, 537039Snate@binkert.org "enable checkpoint pseudo instructions") 547039Snate@binkert.org do_statistics_insts = Param.Bool(True, 556145Snate@binkert.org "enable statistics pseudo instructions") 566145Snate@binkert.org 577039Snate@binkert.org if build_env['TARGET_ISA'] == 'sparc': 587039Snate@binkert.org dtb = Param.SparcDTB(SparcDTB(), "Data TLB") 596843Sdrh5@cs.wisc.edu itb = Param.SparcITB(SparcITB(), "Instruction TLB") 607039Snate@binkert.org elif build_env['TARGET_ISA'] == 'alpha': 6110005Snilay@cs.wisc.edu dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") 627039Snate@binkert.org itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") 637039Snate@binkert.org else: 647039Snate@binkert.org print "Unknown architecture, can't pick TLBs" 657039Snate@binkert.org sys.exit(1) 666843Sdrh5@cs.wisc.edu else: 676843Sdrh5@cs.wisc.edu workload = VectorParam.Process("processes to run") 687039Snate@binkert.org 697039Snate@binkert.org max_insts_all_threads = Param.Counter(0, 7010005Snilay@cs.wisc.edu "terminate when all threads have reached this inst count") 716467Sdrh5@cs.wisc.edu max_insts_any_thread = Param.Counter(0, 727039Snate@binkert.org "terminate when any thread reaches this inst count") 737039Snate@binkert.org max_loads_all_threads = Param.Counter(0, 7410005Snilay@cs.wisc.edu "terminate when all threads have reached this load count") 7510005Snilay@cs.wisc.edu max_loads_any_thread = Param.Counter(0, 7610005Snilay@cs.wisc.edu "terminate when any thread reaches this load count") 7710005Snilay@cs.wisc.edu progress_interval = Param.Tick(0, 786468Sdrh5@cs.wisc.edu "interval to print out the progress message") 796467Sdrh5@cs.wisc.edu 806467Sdrh5@cs.wisc.edu defer_registration = Param.Bool(False, 817039Snate@binkert.org "defer registration with system (for sampling)") 827039Snate@binkert.org 836145Snate@binkert.org clock = Param.Clock('1t', "clock speed") 847039Snate@binkert.org phase = Param.Latency('0ns', "clock phase") 856145Snate@binkert.org 866145Snate@binkert.org _mem_ports = [] 877039Snate@binkert.org 887039Snate@binkert.org def connectMemPorts(self, bus): 896145Snate@binkert.org for p in self._mem_ports: 907039Snate@binkert.org exec('self.%s = bus.port' % p) 916145Snate@binkert.org 926145Snate@binkert.org def addPrivateSplitL1Caches(self, ic, dc): 937039Snate@binkert.org assert(len(self._mem_ports) == 2) 947039Snate@binkert.org self.icache = ic 957039Snate@binkert.org self.dcache = dc 966926SBrad.Beckmann@amd.com self.icache_port = ic.cpu_side 976926SBrad.Beckmann@amd.com self.dcache_port = dc.cpu_side 986145Snate@binkert.org self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] 997039Snate@binkert.org 100 def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 101 self.addPrivateSplitL1Caches(ic, dc) 102 self.toL2Bus = Bus() 103 self.connectMemPorts(self.toL2Bus) 104 self.l2cache = l2c 105 self.l2cache.cpu_side = self.toL2Bus.port 106 self._mem_ports = ['l2cache.mem_side'] 107