BaseCPU.py revision 4486
1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Nathan Binkert 28 29from m5.SimObject import SimObject 30from m5.params import * 31from m5.proxy import * 32from m5 import build_env 33from Bus import Bus 34import sys 35 36if build_env['FULL_SYSTEM']: 37 if build_env['TARGET_ISA'] == 'alpha': 38 from AlphaTLB import AlphaDTB, AlphaITB 39 40 if build_env['TARGET_ISA'] == 'sparc': 41 from SparcTLB import SparcDTB, SparcITB 42 43class BaseCPU(SimObject): 44 type = 'BaseCPU' 45 abstract = True 46 47 system = Param.System(Parent.any, "system object") 48 cpu_id = Param.Int("CPU identifier") 49 50 if build_env['FULL_SYSTEM']: 51 do_quiesce = Param.Bool(True, "enable quiesce instructions") 52 do_checkpoint_insts = Param.Bool(True, 53 "enable checkpoint pseudo instructions") 54 do_statistics_insts = Param.Bool(True, 55 "enable statistics pseudo instructions") 56 57 if build_env['TARGET_ISA'] == 'sparc': 58 dtb = Param.SparcDTB(SparcDTB(), "Data TLB") 59 itb = Param.SparcITB(SparcITB(), "Instruction TLB") 60 elif build_env['TARGET_ISA'] == 'alpha': 61 dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") 62 itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") 63 else: 64 print "Unknown architecture, can't pick TLBs" 65 sys.exit(1) 66 else: 67 workload = VectorParam.Process("processes to run") 68 69 max_insts_all_threads = Param.Counter(0, 70 "terminate when all threads have reached this inst count") 71 max_insts_any_thread = Param.Counter(0, 72 "terminate when any thread reaches this inst count") 73 max_loads_all_threads = Param.Counter(0, 74 "terminate when all threads have reached this load count") 75 max_loads_any_thread = Param.Counter(0, 76 "terminate when any thread reaches this load count") 77 progress_interval = Param.Tick(0, 78 "interval to print out the progress message") 79 80 defer_registration = Param.Bool(False, 81 "defer registration with system (for sampling)") 82 83 clock = Param.Clock('1t', "clock speed") 84 phase = Param.Latency('0ns', "clock phase") 85 86 _mem_ports = [] 87 88 def connectMemPorts(self, bus): 89 for p in self._mem_ports: 90 exec('self.%s = bus.port' % p) 91 92 def addPrivateSplitL1Caches(self, ic, dc): 93 assert(len(self._mem_ports) == 2) 94 self.icache = ic 95 self.dcache = dc 96 self.icache_port = ic.cpu_side 97 self.dcache_port = dc.cpu_side 98 self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] 99 100 def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 101 self.addPrivateSplitL1Caches(ic, dc) 102 self.toL2Bus = Bus() 103 self.connectMemPorts(self.toL2Bus) 104 self.l2cache = l2c 105 self.l2cache.cpu_side = self.toL2Bus.port 106 self._mem_ports = ['l2cache.mem_side'] 107