utility.cc revision 9887
15086Sgblack@eecs.umich.edu/* 25086Sgblack@eecs.umich.edu * Copyright (c) 2007 The Hewlett-Packard Development Company 38466Snilay@cs.wisc.edu * Copyright (c) 2011 Advanced Micro Devices, Inc. 45086Sgblack@eecs.umich.edu * All rights reserved. 55086Sgblack@eecs.umich.edu * 67087Snate@binkert.org * The license below extends only to copyright in the software and shall 77087Snate@binkert.org * not be construed as granting a license to any other intellectual 87087Snate@binkert.org * property including but not limited to intellectual property relating 97087Snate@binkert.org * to a hardware implementation of the functionality of the software 107087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 117087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 127087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 137087Snate@binkert.org * modified or unmodified, in source code or in binary form. 145086Sgblack@eecs.umich.edu * 157087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 167087Snate@binkert.org * modification, are permitted provided that the following conditions are 177087Snate@binkert.org * met: redistributions of source code must retain the above copyright 187087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 197087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 207087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 217087Snate@binkert.org * documentation and/or other materials provided with the distribution; 227087Snate@binkert.org * neither the name of the copyright holders nor the names of its 235086Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 247087Snate@binkert.org * this software without specific prior written permission. 255086Sgblack@eecs.umich.edu * 265086Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 275086Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 285086Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 295086Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 305086Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 315086Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 325086Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 335086Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 345086Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 355086Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 365086Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 375086Sgblack@eecs.umich.edu * 385086Sgblack@eecs.umich.edu * Authors: Gabe Black 395086Sgblack@eecs.umich.edu */ 405086Sgblack@eecs.umich.edu 415647Sgblack@eecs.umich.edu#include "arch/x86/interrupts.hh" 428466Snilay@cs.wisc.edu#include "arch/x86/registers.hh" 438466Snilay@cs.wisc.edu#include "arch/x86/tlb.hh" 445086Sgblack@eecs.umich.edu#include "arch/x86/utility.hh" 455135Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh" 465647Sgblack@eecs.umich.edu#include "cpu/base.hh" 475234Sgblack@eecs.umich.edu#include "sim/system.hh" 485086Sgblack@eecs.umich.edu 495086Sgblack@eecs.umich.edunamespace X86ISA { 505086Sgblack@eecs.umich.edu 517707Sgblack@eecs.umich.eduuint64_t 527707Sgblack@eecs.umich.edugetArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) 537707Sgblack@eecs.umich.edu{ 549887Sandreas@sandberg.pp.se if (!FullSystem) { 559887Sandreas@sandberg.pp.se panic("getArgument() only implemented for full system mode.\n"); 569887Sandreas@sandberg.pp.se } else if (fp) { 579887Sandreas@sandberg.pp.se panic("getArgument(): Floating point arguments not implemented\n"); 589887Sandreas@sandberg.pp.se } else if (size != 8) { 599887Sandreas@sandberg.pp.se panic("getArgument(): Can only handle 64-bit arguments.\n"); 609887Sandreas@sandberg.pp.se } 619887Sandreas@sandberg.pp.se 629887Sandreas@sandberg.pp.se // The first 6 integer arguments are passed in registers, the rest 639887Sandreas@sandberg.pp.se // are passed on the stack. 649887Sandreas@sandberg.pp.se const int int_reg_map[] = { 659887Sandreas@sandberg.pp.se INTREG_RDI, INTREG_RSI, INTREG_RDX, 669887Sandreas@sandberg.pp.se INTREG_RCX, INTREG_R8, INTREG_R9 679887Sandreas@sandberg.pp.se }; 689887Sandreas@sandberg.pp.se if (number < sizeof(int_reg_map) / sizeof(*int_reg_map)) { 699887Sandreas@sandberg.pp.se return tc->readIntReg(int_reg_map[number]); 709887Sandreas@sandberg.pp.se } else { 719887Sandreas@sandberg.pp.se panic("getArgument(): Don't know how to handle stack arguments.\n"); 729887Sandreas@sandberg.pp.se } 735086Sgblack@eecs.umich.edu} 745135Sgblack@eecs.umich.edu 755135Sgblack@eecs.umich.eduvoid initCPU(ThreadContext *tc, int cpuId) 765135Sgblack@eecs.umich.edu{ 776048Sgblack@eecs.umich.edu // This function is essentially performing a reset. The actual INIT 786048Sgblack@eecs.umich.edu // interrupt does a subset of this, so we'll piggyback on some of its 796048Sgblack@eecs.umich.edu // functionality. 806048Sgblack@eecs.umich.edu InitInterrupt init(0); 816048Sgblack@eecs.umich.edu init.invoke(tc); 826048Sgblack@eecs.umich.edu 837720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 847720Sgblack@eecs.umich.edu pc.upc(0); 857720Sgblack@eecs.umich.edu pc.nupc(1); 867720Sgblack@eecs.umich.edu tc->pcState(pc); 875135Sgblack@eecs.umich.edu 885135Sgblack@eecs.umich.edu // These next two loops zero internal microcode and implicit registers. 895135Sgblack@eecs.umich.edu // They aren't specified by the ISA but are used internally by M5's 905135Sgblack@eecs.umich.edu // implementation. 915135Sgblack@eecs.umich.edu for (int index = 0; index < NumMicroIntRegs; index++) { 925135Sgblack@eecs.umich.edu tc->setIntReg(INTREG_MICRO(index), 0); 935135Sgblack@eecs.umich.edu } 945135Sgblack@eecs.umich.edu 955135Sgblack@eecs.umich.edu for (int index = 0; index < NumImplicitIntRegs; index++) { 965135Sgblack@eecs.umich.edu tc->setIntReg(INTREG_IMPLICIT(index), 0); 975135Sgblack@eecs.umich.edu } 985135Sgblack@eecs.umich.edu 995135Sgblack@eecs.umich.edu // Set integer register EAX to 0 to indicate that the optional BIST 1005135Sgblack@eecs.umich.edu // passed. No BIST actually runs, but software may still check this 1015135Sgblack@eecs.umich.edu // register for errors. 1025135Sgblack@eecs.umich.edu tc->setIntReg(INTREG_RAX, 0); 1035135Sgblack@eecs.umich.edu 1045264Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL); 1055135Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR8, 0); 1065135Sgblack@eecs.umich.edu 1075135Sgblack@eecs.umich.edu // TODO initialize x87, 64 bit, and 128 bit media state 1085135Sgblack@eecs.umich.edu 1095141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRRCAP, 0x0508); 1105141Sgblack@eecs.umich.edu for (int i = 0; i < 8; i++) { 1115141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0); 1125141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0); 1135141Sgblack@eecs.umich.edu } 1145141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0); 1155141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0); 1165141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0); 1175141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0); 1185182Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0); 1195141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0); 1205141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0); 1215141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0); 1225141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0); 1235141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0); 1245141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0); 1255135Sgblack@eecs.umich.edu 1265141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DEF_TYPE, 0); 1275141Sgblack@eecs.umich.edu 1285141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MCG_CAP, 0x104); 1295141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MCG_STATUS, 0); 1305141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MCG_CTL, 0); 1315141Sgblack@eecs.umich.edu 1325141Sgblack@eecs.umich.edu for (int i = 0; i < 5; i++) { 1335141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MC_CTL(i), 0); 1345141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MC_STATUS(i), 0); 1355141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MC_ADDR(i), 0); 1365141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MC_MISC(i), 0); 1375141Sgblack@eecs.umich.edu } 1385135Sgblack@eecs.umich.edu 1395141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TSC, 0); 1405141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TSC_AUX, 0); 1415135Sgblack@eecs.umich.edu 1425141Sgblack@eecs.umich.edu for (int i = 0; i < 4; i++) { 1435141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0); 1445141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0); 1455141Sgblack@eecs.umich.edu } 1465135Sgblack@eecs.umich.edu 1475141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_STAR, 0); 1485141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LSTAR, 0); 1495141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CSTAR, 0); 1505141Sgblack@eecs.umich.edu 1515141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SF_MASK, 0); 1525141Sgblack@eecs.umich.edu 1535141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0); 1545141Sgblack@eecs.umich.edu 1555141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SYSENTER_CS, 0); 1565141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SYSENTER_ESP, 0); 1575141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SYSENTER_EIP, 0); 1585141Sgblack@eecs.umich.edu 1595264Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_PAT, 0x0007040600070406ULL); 1605141Sgblack@eecs.umich.edu 1615141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SYSCFG, 0x20601); 1625141Sgblack@eecs.umich.edu 1635141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IORR_BASE0, 0); 1645141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IORR_BASE1, 0); 1655141Sgblack@eecs.umich.edu 1665141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IORR_MASK0, 0); 1675141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IORR_MASK1, 0); 1685141Sgblack@eecs.umich.edu 1695141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000); 1705141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TOP_MEM2, 0x0); 1715141Sgblack@eecs.umich.edu 1725141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0); 1735141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0); 1745141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0); 1755141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0); 1765141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0); 1775135Sgblack@eecs.umich.edu 1785135Sgblack@eecs.umich.edu // Invalidate the caches (this should already be done for us) 1795135Sgblack@eecs.umich.edu 1805360Sgblack@eecs.umich.edu LocalApicBase lApicBase = 0; 1815360Sgblack@eecs.umich.edu lApicBase.base = 0xFEE00000 >> 12; 1825360Sgblack@eecs.umich.edu lApicBase.enable = 1; 1835360Sgblack@eecs.umich.edu lApicBase.bsp = (cpuId == 0); 1845360Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_APIC_BASE, lApicBase); 1855360Sgblack@eecs.umich.edu 1865647Sgblack@eecs.umich.edu Interrupts * interrupts = dynamic_cast<Interrupts *>( 1875647Sgblack@eecs.umich.edu tc->getCpuPtr()->getInterruptController()); 1885647Sgblack@eecs.umich.edu assert(interrupts); 1895360Sgblack@eecs.umich.edu 1905647Sgblack@eecs.umich.edu interrupts->setRegNoEffect(APIC_ID, cpuId << 24); 1915647Sgblack@eecs.umich.edu 1925647Sgblack@eecs.umich.edu interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14); 1939157Sandreas.hansson@arm.com 1945141Sgblack@eecs.umich.edu // TODO Set the SMRAM base address (SMBASE) to 0x00030000 1955141Sgblack@eecs.umich.edu 1965141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_VM_CR, 0); 1975141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_IGNNE, 0); 1985141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SMM_CTL, 0); 1995141Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0); 2005135Sgblack@eecs.umich.edu} 2015135Sgblack@eecs.umich.edu 2025135Sgblack@eecs.umich.eduvoid startupCPU(ThreadContext *tc, int cpuId) 2035135Sgblack@eecs.umich.edu{ 2048768Sgblack@eecs.umich.edu if (cpuId == 0 || !FullSystem) { 2059180Sandreas.hansson@arm.com tc->activate(Cycles(0)); 2065135Sgblack@eecs.umich.edu } else { 2075135Sgblack@eecs.umich.edu // This is an application processor (AP). It should be initialized to 2085135Sgblack@eecs.umich.edu // look like only the BIOS POST has run on it and put then put it into 2095135Sgblack@eecs.umich.edu // a halted state. 2109180Sandreas.hansson@arm.com tc->suspend(Cycles(0)); 2115135Sgblack@eecs.umich.edu } 2125135Sgblack@eecs.umich.edu} 2135135Sgblack@eecs.umich.edu 2146329Sgblack@eecs.umich.eduvoid 2156329Sgblack@eecs.umich.educopyMiscRegs(ThreadContext *src, ThreadContext *dest) 2166329Sgblack@eecs.umich.edu{ 2178466Snilay@cs.wisc.edu // This function assumes no side effects other than TLB invalidation 2188466Snilay@cs.wisc.edu // need to be considered while copying state. That will likely not be 2198466Snilay@cs.wisc.edu // true in the future. 2206329Sgblack@eecs.umich.edu for (int i = 0; i < NUM_MISCREGS; ++i) { 2216329Sgblack@eecs.umich.edu if ( ( i != MISCREG_CR1 && 2226329Sgblack@eecs.umich.edu !(i > MISCREG_CR4 && i < MISCREG_CR8) && 2236329Sgblack@eecs.umich.edu !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) { 2246329Sgblack@eecs.umich.edu continue; 2256329Sgblack@eecs.umich.edu } 2266329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); 2276329Sgblack@eecs.umich.edu } 2288466Snilay@cs.wisc.edu 2299751Sandreas@sandberg.pp.se // The TSC has to be updated with side-effects if the CPUs in a 2309751Sandreas@sandberg.pp.se // CPU switch have different frequencies. 2319751Sandreas@sandberg.pp.se dest->setMiscReg(MISCREG_TSC, src->readMiscReg(MISCREG_TSC)); 2329751Sandreas@sandberg.pp.se 2339423SAndreas.Sandberg@arm.com dest->getITBPtr()->flushAll(); 2349423SAndreas.Sandberg@arm.com dest->getDTBPtr()->flushAll(); 2356329Sgblack@eecs.umich.edu} 2366329Sgblack@eecs.umich.edu 2376329Sgblack@eecs.umich.eduvoid 2386329Sgblack@eecs.umich.educopyRegs(ThreadContext *src, ThreadContext *dest) 2396329Sgblack@eecs.umich.edu{ 2406329Sgblack@eecs.umich.edu //copy int regs 2418466Snilay@cs.wisc.edu for (int i = 0; i < NumIntRegs; ++i) 2428466Snilay@cs.wisc.edu dest->setIntReg(i, src->readIntReg(i)); 2436329Sgblack@eecs.umich.edu //copy float regs 2448466Snilay@cs.wisc.edu for (int i = 0; i < NumFloatRegs; ++i) 2458466Snilay@cs.wisc.edu dest->setFloatRegBits(i, src->readFloatRegBits(i)); 2466329Sgblack@eecs.umich.edu copyMiscRegs(src, dest); 2477720Sgblack@eecs.umich.edu dest->pcState(src->pcState()); 2486329Sgblack@eecs.umich.edu} 2496329Sgblack@eecs.umich.edu 2507693SAli.Saidi@ARM.comvoid 2517693SAli.Saidi@ARM.comskipFunction(ThreadContext *tc) 2527693SAli.Saidi@ARM.com{ 2537693SAli.Saidi@ARM.com panic("Not implemented for x86\n"); 2547693SAli.Saidi@ARM.com} 2557693SAli.Saidi@ARM.com 2569759Sandreas@sandberg.pp.seuint64_t 2579759Sandreas@sandberg.pp.segetRFlags(ThreadContext *tc) 2589759Sandreas@sandberg.pp.se{ 2599759Sandreas@sandberg.pp.se const uint64_t ncc_flags(tc->readMiscRegNoEffect(MISCREG_RFLAGS)); 2609759Sandreas@sandberg.pp.se const uint64_t cc_flags(tc->readIntReg(X86ISA::INTREG_PSEUDO(0))); 2619759Sandreas@sandberg.pp.se const uint64_t cfof_bits(tc->readIntReg(X86ISA::INTREG_PSEUDO(1))); 2629759Sandreas@sandberg.pp.se const uint64_t df_bit(tc->readIntReg(X86ISA::INTREG_PSEUDO(2))); 2639759Sandreas@sandberg.pp.se // ecf (PSEUDO(3)) & ezf (PSEUDO(4)) are only visible to 2649759Sandreas@sandberg.pp.se // microcode, so we can safely ignore them. 2659759Sandreas@sandberg.pp.se 2669759Sandreas@sandberg.pp.se // Reconstruct the real rflags state, mask out internal flags, and 2679759Sandreas@sandberg.pp.se // make sure reserved bits have the expected values. 2689759Sandreas@sandberg.pp.se return ((ncc_flags | cc_flags | cfof_bits | df_bit) & 0x3F7FD5) 2699759Sandreas@sandberg.pp.se | 0x2; 2709759Sandreas@sandberg.pp.se} 2719759Sandreas@sandberg.pp.se 2729759Sandreas@sandberg.pp.sevoid 2739759Sandreas@sandberg.pp.sesetRFlags(ThreadContext *tc, uint64_t val) 2749759Sandreas@sandberg.pp.se{ 2759759Sandreas@sandberg.pp.se tc->setIntReg(X86ISA::INTREG_PSEUDO(0), val & ccFlagMask); 2769759Sandreas@sandberg.pp.se tc->setIntReg(X86ISA::INTREG_PSEUDO(1), val & cfofMask); 2779759Sandreas@sandberg.pp.se tc->setIntReg(X86ISA::INTREG_PSEUDO(2), val & DFBit); 2789759Sandreas@sandberg.pp.se 2799759Sandreas@sandberg.pp.se // Internal microcode registers (ECF & EZF) 2809759Sandreas@sandberg.pp.se tc->setIntReg(X86ISA::INTREG_PSEUDO(3), 0); 2819759Sandreas@sandberg.pp.se tc->setIntReg(X86ISA::INTREG_PSEUDO(4), 0); 2829759Sandreas@sandberg.pp.se 2839759Sandreas@sandberg.pp.se // Update the RFLAGS misc reg with whatever didn't go into the 2849759Sandreas@sandberg.pp.se // magic registers. 2859759Sandreas@sandberg.pp.se tc->setMiscReg(MISCREG_RFLAGS, val & ~(ccFlagMask | cfofMask | DFBit)); 2869759Sandreas@sandberg.pp.se} 2877693SAli.Saidi@ARM.com 2889880Sandreas@sandberg.pp.seuint8_t 2899880Sandreas@sandberg.pp.seconvX87TagsToXTags(uint16_t ftw) 2909880Sandreas@sandberg.pp.se{ 2919880Sandreas@sandberg.pp.se uint8_t ftwx(0); 2929880Sandreas@sandberg.pp.se for (int i = 0; i < 8; ++i) { 2939880Sandreas@sandberg.pp.se // Extract the tag for the current element on the FP stack 2949880Sandreas@sandberg.pp.se const unsigned tag((ftw >> (2 * i)) & 0x3); 2959880Sandreas@sandberg.pp.se 2969880Sandreas@sandberg.pp.se /* 2979880Sandreas@sandberg.pp.se * Check the type of the current FP element. Valid values are: 2989880Sandreas@sandberg.pp.se * 0 == Valid 2999880Sandreas@sandberg.pp.se * 1 == Zero 3009880Sandreas@sandberg.pp.se * 2 == Special (Nan, unsupported, infinity, denormal) 3019880Sandreas@sandberg.pp.se * 3 == Empty 3029880Sandreas@sandberg.pp.se */ 3039880Sandreas@sandberg.pp.se // The xsave version of the tag word only keeps track of 3049880Sandreas@sandberg.pp.se // whether the element is empty or not. Set the corresponding 3059880Sandreas@sandberg.pp.se // bit in the ftwx if it's not empty, 3069880Sandreas@sandberg.pp.se if (tag != 0x3) 3079880Sandreas@sandberg.pp.se ftwx |= 1 << i; 3089880Sandreas@sandberg.pp.se } 3099880Sandreas@sandberg.pp.se 3109880Sandreas@sandberg.pp.se return ftwx; 3119880Sandreas@sandberg.pp.se} 3129880Sandreas@sandberg.pp.se 3139880Sandreas@sandberg.pp.seuint16_t 3149880Sandreas@sandberg.pp.seconvX87XTagsToTags(uint8_t ftwx) 3159880Sandreas@sandberg.pp.se{ 3169880Sandreas@sandberg.pp.se uint16_t ftw(0); 3179880Sandreas@sandberg.pp.se for (int i = 0; i < 8; ++i) { 3189880Sandreas@sandberg.pp.se const unsigned xtag(((ftwx >> i) & 0x1)); 3199880Sandreas@sandberg.pp.se 3209880Sandreas@sandberg.pp.se // The xtag for an x87 stack position is 0 for empty stack positions. 3219880Sandreas@sandberg.pp.se if (!xtag) { 3229880Sandreas@sandberg.pp.se // Set the tag word to 3 (empty) for the current element. 3239880Sandreas@sandberg.pp.se ftw |= 0x3 << (2 * i); 3249880Sandreas@sandberg.pp.se } else { 3259880Sandreas@sandberg.pp.se // TODO: We currently assume that non-empty elements are 3269880Sandreas@sandberg.pp.se // valid (0x0), but we should ideally reconstruct the full 3279880Sandreas@sandberg.pp.se // state (valid/zero/special). 3289880Sandreas@sandberg.pp.se } 3299880Sandreas@sandberg.pp.se } 3309880Sandreas@sandberg.pp.se 3319880Sandreas@sandberg.pp.se return ftw; 3329880Sandreas@sandberg.pp.se} 3339880Sandreas@sandberg.pp.se 3349765Sandreas@sandberg.pp.seuint16_t 3359765Sandreas@sandberg.pp.segenX87Tags(uint16_t ftw, uint8_t top, int8_t spm) 3369765Sandreas@sandberg.pp.se{ 3379765Sandreas@sandberg.pp.se const uint8_t new_top((top + spm + 8) % 8); 3389765Sandreas@sandberg.pp.se 3399765Sandreas@sandberg.pp.se if (spm > 0) { 3409765Sandreas@sandberg.pp.se // Removing elements from the stack. Flag the elements as empty. 3419765Sandreas@sandberg.pp.se for (int i = top; i != new_top; i = (i + 1 + 8) % 8) 3429765Sandreas@sandberg.pp.se ftw |= 0x3 << (2 * i); 3439765Sandreas@sandberg.pp.se } else if (spm < 0) { 3449765Sandreas@sandberg.pp.se // Adding elements to the stack. Flag the new elements as 3459765Sandreas@sandberg.pp.se // valid. We should ideally decode them and "do the right 3469765Sandreas@sandberg.pp.se // thing". 3479765Sandreas@sandberg.pp.se for (int i = new_top; i != top; i = (i + 1 + 8) % 8) 3489765Sandreas@sandberg.pp.se ftw &= ~(0x3 << (2 * i)); 3499765Sandreas@sandberg.pp.se } 3509765Sandreas@sandberg.pp.se 3519765Sandreas@sandberg.pp.se return ftw; 3529765Sandreas@sandberg.pp.se} 3539765Sandreas@sandberg.pp.se 3547811Ssteve.reinhardt@amd.com} // namespace X86_ISA 355