utility.cc revision 9887
1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * Copyright (c) 2011 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions are 17 * met: redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer; 19 * redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution; 22 * neither the name of the copyright holders nor the names of its 23 * contributors may be used to endorse or promote products derived from 24 * this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 * 38 * Authors: Gabe Black 39 */ 40 41#include "arch/x86/interrupts.hh" 42#include "arch/x86/registers.hh" 43#include "arch/x86/tlb.hh" 44#include "arch/x86/utility.hh" 45#include "arch/x86/x86_traits.hh" 46#include "cpu/base.hh" 47#include "sim/system.hh" 48 49namespace X86ISA { 50 51uint64_t 52getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp) 53{ 54 if (!FullSystem) { 55 panic("getArgument() only implemented for full system mode.\n"); 56 } else if (fp) { 57 panic("getArgument(): Floating point arguments not implemented\n"); 58 } else if (size != 8) { 59 panic("getArgument(): Can only handle 64-bit arguments.\n"); 60 } 61 62 // The first 6 integer arguments are passed in registers, the rest 63 // are passed on the stack. 64 const int int_reg_map[] = { 65 INTREG_RDI, INTREG_RSI, INTREG_RDX, 66 INTREG_RCX, INTREG_R8, INTREG_R9 67 }; 68 if (number < sizeof(int_reg_map) / sizeof(*int_reg_map)) { 69 return tc->readIntReg(int_reg_map[number]); 70 } else { 71 panic("getArgument(): Don't know how to handle stack arguments.\n"); 72 } 73} 74 75void initCPU(ThreadContext *tc, int cpuId) 76{ 77 // This function is essentially performing a reset. The actual INIT 78 // interrupt does a subset of this, so we'll piggyback on some of its 79 // functionality. 80 InitInterrupt init(0); 81 init.invoke(tc); 82 83 PCState pc = tc->pcState(); 84 pc.upc(0); 85 pc.nupc(1); 86 tc->pcState(pc); 87 88 // These next two loops zero internal microcode and implicit registers. 89 // They aren't specified by the ISA but are used internally by M5's 90 // implementation. 91 for (int index = 0; index < NumMicroIntRegs; index++) { 92 tc->setIntReg(INTREG_MICRO(index), 0); 93 } 94 95 for (int index = 0; index < NumImplicitIntRegs; index++) { 96 tc->setIntReg(INTREG_IMPLICIT(index), 0); 97 } 98 99 // Set integer register EAX to 0 to indicate that the optional BIST 100 // passed. No BIST actually runs, but software may still check this 101 // register for errors. 102 tc->setIntReg(INTREG_RAX, 0); 103 104 tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL); 105 tc->setMiscReg(MISCREG_CR8, 0); 106 107 // TODO initialize x87, 64 bit, and 128 bit media state 108 109 tc->setMiscReg(MISCREG_MTRRCAP, 0x0508); 110 for (int i = 0; i < 8; i++) { 111 tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0); 112 tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0); 113 } 114 tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0); 115 tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0); 116 tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0); 117 tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0); 118 tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0); 119 tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0); 120 tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0); 121 tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0); 122 tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0); 123 tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0); 124 tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0); 125 126 tc->setMiscReg(MISCREG_DEF_TYPE, 0); 127 128 tc->setMiscReg(MISCREG_MCG_CAP, 0x104); 129 tc->setMiscReg(MISCREG_MCG_STATUS, 0); 130 tc->setMiscReg(MISCREG_MCG_CTL, 0); 131 132 for (int i = 0; i < 5; i++) { 133 tc->setMiscReg(MISCREG_MC_CTL(i), 0); 134 tc->setMiscReg(MISCREG_MC_STATUS(i), 0); 135 tc->setMiscReg(MISCREG_MC_ADDR(i), 0); 136 tc->setMiscReg(MISCREG_MC_MISC(i), 0); 137 } 138 139 tc->setMiscReg(MISCREG_TSC, 0); 140 tc->setMiscReg(MISCREG_TSC_AUX, 0); 141 142 for (int i = 0; i < 4; i++) { 143 tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0); 144 tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0); 145 } 146 147 tc->setMiscReg(MISCREG_STAR, 0); 148 tc->setMiscReg(MISCREG_LSTAR, 0); 149 tc->setMiscReg(MISCREG_CSTAR, 0); 150 151 tc->setMiscReg(MISCREG_SF_MASK, 0); 152 153 tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0); 154 155 tc->setMiscReg(MISCREG_SYSENTER_CS, 0); 156 tc->setMiscReg(MISCREG_SYSENTER_ESP, 0); 157 tc->setMiscReg(MISCREG_SYSENTER_EIP, 0); 158 159 tc->setMiscReg(MISCREG_PAT, 0x0007040600070406ULL); 160 161 tc->setMiscReg(MISCREG_SYSCFG, 0x20601); 162 163 tc->setMiscReg(MISCREG_IORR_BASE0, 0); 164 tc->setMiscReg(MISCREG_IORR_BASE1, 0); 165 166 tc->setMiscReg(MISCREG_IORR_MASK0, 0); 167 tc->setMiscReg(MISCREG_IORR_MASK1, 0); 168 169 tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000); 170 tc->setMiscReg(MISCREG_TOP_MEM2, 0x0); 171 172 tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0); 173 tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0); 174 tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0); 175 tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0); 176 tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0); 177 178 // Invalidate the caches (this should already be done for us) 179 180 LocalApicBase lApicBase = 0; 181 lApicBase.base = 0xFEE00000 >> 12; 182 lApicBase.enable = 1; 183 lApicBase.bsp = (cpuId == 0); 184 tc->setMiscReg(MISCREG_APIC_BASE, lApicBase); 185 186 Interrupts * interrupts = dynamic_cast<Interrupts *>( 187 tc->getCpuPtr()->getInterruptController()); 188 assert(interrupts); 189 190 interrupts->setRegNoEffect(APIC_ID, cpuId << 24); 191 192 interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14); 193 194 // TODO Set the SMRAM base address (SMBASE) to 0x00030000 195 196 tc->setMiscReg(MISCREG_VM_CR, 0); 197 tc->setMiscReg(MISCREG_IGNNE, 0); 198 tc->setMiscReg(MISCREG_SMM_CTL, 0); 199 tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0); 200} 201 202void startupCPU(ThreadContext *tc, int cpuId) 203{ 204 if (cpuId == 0 || !FullSystem) { 205 tc->activate(Cycles(0)); 206 } else { 207 // This is an application processor (AP). It should be initialized to 208 // look like only the BIOS POST has run on it and put then put it into 209 // a halted state. 210 tc->suspend(Cycles(0)); 211 } 212} 213 214void 215copyMiscRegs(ThreadContext *src, ThreadContext *dest) 216{ 217 // This function assumes no side effects other than TLB invalidation 218 // need to be considered while copying state. That will likely not be 219 // true in the future. 220 for (int i = 0; i < NUM_MISCREGS; ++i) { 221 if ( ( i != MISCREG_CR1 && 222 !(i > MISCREG_CR4 && i < MISCREG_CR8) && 223 !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) { 224 continue; 225 } 226 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i)); 227 } 228 229 // The TSC has to be updated with side-effects if the CPUs in a 230 // CPU switch have different frequencies. 231 dest->setMiscReg(MISCREG_TSC, src->readMiscReg(MISCREG_TSC)); 232 233 dest->getITBPtr()->flushAll(); 234 dest->getDTBPtr()->flushAll(); 235} 236 237void 238copyRegs(ThreadContext *src, ThreadContext *dest) 239{ 240 //copy int regs 241 for (int i = 0; i < NumIntRegs; ++i) 242 dest->setIntReg(i, src->readIntReg(i)); 243 //copy float regs 244 for (int i = 0; i < NumFloatRegs; ++i) 245 dest->setFloatRegBits(i, src->readFloatRegBits(i)); 246 copyMiscRegs(src, dest); 247 dest->pcState(src->pcState()); 248} 249 250void 251skipFunction(ThreadContext *tc) 252{ 253 panic("Not implemented for x86\n"); 254} 255 256uint64_t 257getRFlags(ThreadContext *tc) 258{ 259 const uint64_t ncc_flags(tc->readMiscRegNoEffect(MISCREG_RFLAGS)); 260 const uint64_t cc_flags(tc->readIntReg(X86ISA::INTREG_PSEUDO(0))); 261 const uint64_t cfof_bits(tc->readIntReg(X86ISA::INTREG_PSEUDO(1))); 262 const uint64_t df_bit(tc->readIntReg(X86ISA::INTREG_PSEUDO(2))); 263 // ecf (PSEUDO(3)) & ezf (PSEUDO(4)) are only visible to 264 // microcode, so we can safely ignore them. 265 266 // Reconstruct the real rflags state, mask out internal flags, and 267 // make sure reserved bits have the expected values. 268 return ((ncc_flags | cc_flags | cfof_bits | df_bit) & 0x3F7FD5) 269 | 0x2; 270} 271 272void 273setRFlags(ThreadContext *tc, uint64_t val) 274{ 275 tc->setIntReg(X86ISA::INTREG_PSEUDO(0), val & ccFlagMask); 276 tc->setIntReg(X86ISA::INTREG_PSEUDO(1), val & cfofMask); 277 tc->setIntReg(X86ISA::INTREG_PSEUDO(2), val & DFBit); 278 279 // Internal microcode registers (ECF & EZF) 280 tc->setIntReg(X86ISA::INTREG_PSEUDO(3), 0); 281 tc->setIntReg(X86ISA::INTREG_PSEUDO(4), 0); 282 283 // Update the RFLAGS misc reg with whatever didn't go into the 284 // magic registers. 285 tc->setMiscReg(MISCREG_RFLAGS, val & ~(ccFlagMask | cfofMask | DFBit)); 286} 287 288uint8_t 289convX87TagsToXTags(uint16_t ftw) 290{ 291 uint8_t ftwx(0); 292 for (int i = 0; i < 8; ++i) { 293 // Extract the tag for the current element on the FP stack 294 const unsigned tag((ftw >> (2 * i)) & 0x3); 295 296 /* 297 * Check the type of the current FP element. Valid values are: 298 * 0 == Valid 299 * 1 == Zero 300 * 2 == Special (Nan, unsupported, infinity, denormal) 301 * 3 == Empty 302 */ 303 // The xsave version of the tag word only keeps track of 304 // whether the element is empty or not. Set the corresponding 305 // bit in the ftwx if it's not empty, 306 if (tag != 0x3) 307 ftwx |= 1 << i; 308 } 309 310 return ftwx; 311} 312 313uint16_t 314convX87XTagsToTags(uint8_t ftwx) 315{ 316 uint16_t ftw(0); 317 for (int i = 0; i < 8; ++i) { 318 const unsigned xtag(((ftwx >> i) & 0x1)); 319 320 // The xtag for an x87 stack position is 0 for empty stack positions. 321 if (!xtag) { 322 // Set the tag word to 3 (empty) for the current element. 323 ftw |= 0x3 << (2 * i); 324 } else { 325 // TODO: We currently assume that non-empty elements are 326 // valid (0x0), but we should ideally reconstruct the full 327 // state (valid/zero/special). 328 } 329 } 330 331 return ftw; 332} 333 334uint16_t 335genX87Tags(uint16_t ftw, uint8_t top, int8_t spm) 336{ 337 const uint8_t new_top((top + spm + 8) % 8); 338 339 if (spm > 0) { 340 // Removing elements from the stack. Flag the elements as empty. 341 for (int i = top; i != new_top; i = (i + 1 + 8) % 8) 342 ftw |= 0x3 << (2 * i); 343 } else if (spm < 0) { 344 // Adding elements to the stack. Flag the new elements as 345 // valid. We should ideally decode them and "do the right 346 // thing". 347 for (int i = new_top; i != top; i = (i + 1 + 8) % 8) 348 ftw &= ~(0x3 << (2 * i)); 349 } 350 351 return ftw; 352} 353 354} // namespace X86_ISA 355