utility.cc revision 5234
15086Sgblack@eecs.umich.edu/*
25086Sgblack@eecs.umich.edu * Copyright (c) 2007 The Hewlett-Packard Development Company
35086Sgblack@eecs.umich.edu * All rights reserved.
45086Sgblack@eecs.umich.edu *
55086Sgblack@eecs.umich.edu * Redistribution and use of this software in source and binary forms,
65086Sgblack@eecs.umich.edu * with or without modification, are permitted provided that the
75086Sgblack@eecs.umich.edu * following conditions are met:
85086Sgblack@eecs.umich.edu *
95086Sgblack@eecs.umich.edu * The software must be used only for Non-Commercial Use which means any
105086Sgblack@eecs.umich.edu * use which is NOT directed to receiving any direct monetary
115086Sgblack@eecs.umich.edu * compensation for, or commercial advantage from such use.  Illustrative
125086Sgblack@eecs.umich.edu * examples of non-commercial use are academic research, personal study,
135086Sgblack@eecs.umich.edu * teaching, education and corporate research & development.
145086Sgblack@eecs.umich.edu * Illustrative examples of commercial use are distributing products for
155086Sgblack@eecs.umich.edu * commercial advantage and providing services using the software for
165086Sgblack@eecs.umich.edu * commercial advantage.
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415086Sgblack@eecs.umich.edu * applicable, this list of conditions and the disclaimer below.
425086Sgblack@eecs.umich.edu *
435086Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
445086Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
455086Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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525086Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
535086Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
545086Sgblack@eecs.umich.edu *
555086Sgblack@eecs.umich.edu * Authors: Gabe Black
565086Sgblack@eecs.umich.edu */
575086Sgblack@eecs.umich.edu
585135Sgblack@eecs.umich.edu#include "arch/x86/intregs.hh"
595135Sgblack@eecs.umich.edu#include "arch/x86/miscregs.hh"
605135Sgblack@eecs.umich.edu#include "arch/x86/segmentregs.hh"
615086Sgblack@eecs.umich.edu#include "arch/x86/utility.hh"
625135Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh"
635234Sgblack@eecs.umich.edu#include "sim/system.hh"
645086Sgblack@eecs.umich.edu
655086Sgblack@eecs.umich.edunamespace X86ISA {
665086Sgblack@eecs.umich.edu
675086Sgblack@eecs.umich.eduuint64_t getArgument(ThreadContext *tc, int number, bool fp) {
685086Sgblack@eecs.umich.edu#if FULL_SYSTEM
695086Sgblack@eecs.umich.edu    panic("getArgument() not implemented for x86!\n");
705086Sgblack@eecs.umich.edu#else
715086Sgblack@eecs.umich.edu    panic("getArgument() only implemented for FULL_SYSTEM\n");
725086Sgblack@eecs.umich.edu    M5_DUMMY_RETURN
735086Sgblack@eecs.umich.edu#endif
745086Sgblack@eecs.umich.edu}
755135Sgblack@eecs.umich.edu
765135Sgblack@eecs.umich.edu# if FULL_SYSTEM
775135Sgblack@eecs.umich.eduvoid initCPU(ThreadContext *tc, int cpuId)
785135Sgblack@eecs.umich.edu{
795135Sgblack@eecs.umich.edu    // The otherwise unmodified integer registers should be set to 0.
805135Sgblack@eecs.umich.edu    for (int index = 0; index < NUM_INTREGS; index++) {
815135Sgblack@eecs.umich.edu        tc->setIntReg(index, 0);
825135Sgblack@eecs.umich.edu    }
835135Sgblack@eecs.umich.edu
845135Sgblack@eecs.umich.edu    // These next two loops zero internal microcode and implicit registers.
855135Sgblack@eecs.umich.edu    // They aren't specified by the ISA but are used internally by M5's
865135Sgblack@eecs.umich.edu    // implementation.
875135Sgblack@eecs.umich.edu    for (int index = 0; index < NumMicroIntRegs; index++) {
885135Sgblack@eecs.umich.edu        tc->setIntReg(INTREG_MICRO(index), 0);
895135Sgblack@eecs.umich.edu    }
905135Sgblack@eecs.umich.edu
915135Sgblack@eecs.umich.edu    for (int index = 0; index < NumImplicitIntRegs; index++) {
925135Sgblack@eecs.umich.edu        tc->setIntReg(INTREG_IMPLICIT(index), 0);
935135Sgblack@eecs.umich.edu    }
945135Sgblack@eecs.umich.edu
955135Sgblack@eecs.umich.edu    // Set integer register EAX to 0 to indicate that the optional BIST
965135Sgblack@eecs.umich.edu    // passed. No BIST actually runs, but software may still check this
975135Sgblack@eecs.umich.edu    // register for errors.
985135Sgblack@eecs.umich.edu    tc->setIntReg(INTREG_RAX, 0);
995135Sgblack@eecs.umich.edu
1005135Sgblack@eecs.umich.edu    //The following values are dictated by the architecture for after a RESET#
1015135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_CR0, 0x0000000060000010);
1025135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_CR2, 0);
1035135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_CR3, 0);
1045135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_CR4, 0);
1055135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_CR8, 0);
1065135Sgblack@eecs.umich.edu
1075135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002);
1085135Sgblack@eecs.umich.edu
1095135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_EFER, 0);
1105135Sgblack@eecs.umich.edu
1115141Sgblack@eecs.umich.edu    SegAttr dataAttr = 0;
1125141Sgblack@eecs.umich.edu    dataAttr.writable = 1;
1135141Sgblack@eecs.umich.edu    dataAttr.readable = 1;
1145141Sgblack@eecs.umich.edu    dataAttr.expandDown = 0;
1155141Sgblack@eecs.umich.edu    dataAttr.dpl = 0;
1165141Sgblack@eecs.umich.edu    dataAttr.defaultSize = 0;
1175141Sgblack@eecs.umich.edu
1185135Sgblack@eecs.umich.edu    for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
1195135Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
1205135Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
1215135Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
1225141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr);
1235135Sgblack@eecs.umich.edu    }
1245135Sgblack@eecs.umich.edu
1255141Sgblack@eecs.umich.edu    SegAttr codeAttr = 0;
1265141Sgblack@eecs.umich.edu    codeAttr.writable = 0;
1275141Sgblack@eecs.umich.edu    codeAttr.readable = 1;
1285141Sgblack@eecs.umich.edu    codeAttr.expandDown = 0;
1295141Sgblack@eecs.umich.edu    codeAttr.dpl = 0;
1305141Sgblack@eecs.umich.edu    codeAttr.defaultSize = 0;
1315141Sgblack@eecs.umich.edu
1325135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_CS, 0xf000);
1335135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_CS_BASE, 0x00000000ffff0000);
1345135Sgblack@eecs.umich.edu    // This has the base value pre-added.
1355135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
1365141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
1375135Sgblack@eecs.umich.edu
1385135Sgblack@eecs.umich.edu    tc->setPC(0x000000000000fff0 +
1395135Sgblack@eecs.umich.edu            tc->readMiscReg(MISCREG_CS_BASE));
1405135Sgblack@eecs.umich.edu    tc->setNextPC(tc->readPC() + sizeof(MachInst));
1415135Sgblack@eecs.umich.edu
1425135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_GDTR_BASE, 0);
1435135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xffff);
1445135Sgblack@eecs.umich.edu
1455135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_IDTR_BASE, 0);
1465135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
1475135Sgblack@eecs.umich.edu
1485135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_LDTR, 0);
1495135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_LDTR_BASE, 0);
1505135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_LDTR_LIMIT, 0xffff);
1515135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_LDTR_ATTR, 0);
1525135Sgblack@eecs.umich.edu
1535135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TR, 0);
1545135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TR_BASE, 0);
1555135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
1565135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TR_ATTR, 0);
1575135Sgblack@eecs.umich.edu
1585135Sgblack@eecs.umich.edu    // This value should be the family/model/stepping of the processor.
1595135Sgblack@eecs.umich.edu    // (page 418). It should be consistent with the value from CPUID, but the
1605135Sgblack@eecs.umich.edu    // actual value probably doesn't matter much.
1615135Sgblack@eecs.umich.edu    tc->setIntReg(INTREG_RDX, 0);
1625135Sgblack@eecs.umich.edu
1635135Sgblack@eecs.umich.edu    // TODO initialize x87, 64 bit, and 128 bit media state
1645135Sgblack@eecs.umich.edu
1655141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRRCAP, 0x0508);
1665141Sgblack@eecs.umich.edu    for (int i = 0; i < 8; i++) {
1675141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0);
1685141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0);
1695141Sgblack@eecs.umich.edu    }
1705141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0);
1715141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0);
1725141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0);
1735141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0);
1745182Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0);
1755141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0);
1765141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0);
1775141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0);
1785141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0);
1795141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0);
1805141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0);
1815135Sgblack@eecs.umich.edu
1825141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_DEF_TYPE, 0);
1835141Sgblack@eecs.umich.edu
1845141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MCG_CAP, 0x104);
1855141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MCG_STATUS, 0);
1865141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_MCG_CTL, 0);
1875141Sgblack@eecs.umich.edu
1885141Sgblack@eecs.umich.edu    for (int i = 0; i < 5; i++) {
1895141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_MC_CTL(i), 0);
1905141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_MC_STATUS(i), 0);
1915141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_MC_ADDR(i), 0);
1925141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_MC_MISC(i), 0);
1935141Sgblack@eecs.umich.edu    }
1945135Sgblack@eecs.umich.edu
1955135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_DR0, 0);
1965135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_DR1, 0);
1975135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_DR2, 0);
1985135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_DR3, 0);
1995135Sgblack@eecs.umich.edu
2005135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0);
2015135Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_DR7, 0x0000000000000400);
2025135Sgblack@eecs.umich.edu
2035141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TSC, 0);
2045141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TSC_AUX, 0);
2055135Sgblack@eecs.umich.edu
2065141Sgblack@eecs.umich.edu    for (int i = 0; i < 4; i++) {
2075141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0);
2085141Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0);
2095141Sgblack@eecs.umich.edu    }
2105135Sgblack@eecs.umich.edu
2115141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_STAR, 0);
2125141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_LSTAR, 0);
2135141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_CSTAR, 0);
2145141Sgblack@eecs.umich.edu
2155141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_SF_MASK, 0);
2165141Sgblack@eecs.umich.edu
2175141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0);
2185141Sgblack@eecs.umich.edu
2195141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_SYSENTER_CS, 0);
2205141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_SYSENTER_ESP, 0);
2215141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_SYSENTER_EIP, 0);
2225141Sgblack@eecs.umich.edu
2235141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_PAT, 0x0007040600070406);
2245141Sgblack@eecs.umich.edu
2255141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_SYSCFG, 0x20601);
2265141Sgblack@eecs.umich.edu
2275141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_IORR_BASE0, 0);
2285141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_IORR_BASE1, 0);
2295141Sgblack@eecs.umich.edu
2305141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_IORR_MASK0, 0);
2315141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_IORR_MASK1, 0);
2325141Sgblack@eecs.umich.edu
2335141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000);
2345141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_TOP_MEM2, 0x0);
2355141Sgblack@eecs.umich.edu
2365141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0);
2375141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0);
2385141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0);
2395141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0);
2405141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0);
2415135Sgblack@eecs.umich.edu
2425135Sgblack@eecs.umich.edu    // Invalidate the caches (this should already be done for us)
2435135Sgblack@eecs.umich.edu
2445135Sgblack@eecs.umich.edu    // TODO Turn on the APIC. This should be handled elsewhere but it isn't
2455135Sgblack@eecs.umich.edu    // currently being handled at all.
2465135Sgblack@eecs.umich.edu
2475141Sgblack@eecs.umich.edu    // TODO Set the SMRAM base address (SMBASE) to 0x00030000
2485141Sgblack@eecs.umich.edu
2495141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_VM_CR, 0);
2505141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_IGNNE, 0);
2515141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_SMM_CTL, 0);
2525141Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
2535135Sgblack@eecs.umich.edu}
2545135Sgblack@eecs.umich.edu
2555135Sgblack@eecs.umich.edu#endif
2565135Sgblack@eecs.umich.edu
2575234Sgblack@eecs.umich.edu#if FULL_SYSTEM
2585135Sgblack@eecs.umich.eduvoid startupCPU(ThreadContext *tc, int cpuId)
2595135Sgblack@eecs.umich.edu{
2605135Sgblack@eecs.umich.edu    if (cpuId == 0) {
2615135Sgblack@eecs.umich.edu        // This is the boot strap processor (BSP). Initialize it to look like
2625234Sgblack@eecs.umich.edu        // the boot loader has just turned control over to the 64 bit OS. We
2635234Sgblack@eecs.umich.edu        // won't actually set up real mode or legacy protected mode descriptor
2645234Sgblack@eecs.umich.edu        // tables because we aren't executing any code that would require
2655234Sgblack@eecs.umich.edu        // them. We do, however toggle the control bits in the correct order
2665234Sgblack@eecs.umich.edu        // while allowing consistency checks and the underlying mechansims
2675234Sgblack@eecs.umich.edu        // just to be safe.
2685135Sgblack@eecs.umich.edu
2695234Sgblack@eecs.umich.edu        const int NumPDTs = 4;
2705234Sgblack@eecs.umich.edu
2715234Sgblack@eecs.umich.edu        const Addr PageMapLevel4 = 0x70000;
2725234Sgblack@eecs.umich.edu        const Addr PageDirPtrTable = 0x71000;
2735234Sgblack@eecs.umich.edu        const Addr PageDirTable[NumPDTs] =
2745234Sgblack@eecs.umich.edu            {0x72000, 0x73000, 0x74000, 0x75000};
2755234Sgblack@eecs.umich.edu        const Addr GDTBase = 0x76000;
2765234Sgblack@eecs.umich.edu
2775234Sgblack@eecs.umich.edu        const int PML4Bits = 9;
2785234Sgblack@eecs.umich.edu        const int PDPTBits = 9;
2795234Sgblack@eecs.umich.edu        const int PDTBits = 9;
2805234Sgblack@eecs.umich.edu
2815234Sgblack@eecs.umich.edu        // Get a port to write the page tables and descriptor tables.
2825234Sgblack@eecs.umich.edu        FunctionalPort * physPort = tc->getPhysPort();
2835234Sgblack@eecs.umich.edu
2845234Sgblack@eecs.umich.edu        /*
2855234Sgblack@eecs.umich.edu         * Set up the gdt.
2865234Sgblack@eecs.umich.edu         */
2875234Sgblack@eecs.umich.edu        // Place holder at selector 0
2885234Sgblack@eecs.umich.edu        uint64_t nullDescriptor = 0;
2895234Sgblack@eecs.umich.edu        physPort->writeBlob(GDTBase, (uint8_t *)(&nullDescriptor), 8);
2905234Sgblack@eecs.umich.edu
2915234Sgblack@eecs.umich.edu        //64 bit code segment
2925234Sgblack@eecs.umich.edu        SegDescriptor csDesc = 0;
2935234Sgblack@eecs.umich.edu        csDesc.type.c = 0; // Not conforming
2945234Sgblack@eecs.umich.edu        csDesc.dpl = 0; // Privelege level 0
2955234Sgblack@eecs.umich.edu        csDesc.p = 1; // Present
2965234Sgblack@eecs.umich.edu        csDesc.l = 1; // 64 bit
2975234Sgblack@eecs.umich.edu        csDesc.d = 0; // default operand size
2985234Sgblack@eecs.umich.edu        //Because we're dealing with a pointer and I don't think it's
2995234Sgblack@eecs.umich.edu        //guaranteed that there isn't anything in a nonvirtual class between
3005234Sgblack@eecs.umich.edu        //it's beginning in memory and it's actual data, we'll use an
3015234Sgblack@eecs.umich.edu        //intermediary.
3025234Sgblack@eecs.umich.edu        uint64_t csDescVal = csDesc;
3035234Sgblack@eecs.umich.edu        physPort->writeBlob(GDTBase, (uint8_t *)(&csDescVal), 8);
3045234Sgblack@eecs.umich.edu
3055234Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_GDTR_BASE, GDTBase);
3065234Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xF);
3075234Sgblack@eecs.umich.edu
3085234Sgblack@eecs.umich.edu        /*
3095234Sgblack@eecs.umich.edu         * Identity map the first 4GB of memory. In order to map this region
3105234Sgblack@eecs.umich.edu         * of memory in long mode, there needs to be one actual page map level
3115234Sgblack@eecs.umich.edu         * 4 entry which points to one page directory pointer table which
3125234Sgblack@eecs.umich.edu         * points to 4 different page directory tables which are full of two
3135234Sgblack@eecs.umich.edu         * megabyte pages. All of the other entries in valid tables are set
3145234Sgblack@eecs.umich.edu         * to indicate that they don't pertain to anything valid and will
3155234Sgblack@eecs.umich.edu         * cause a fault if used.
3165234Sgblack@eecs.umich.edu         */
3175234Sgblack@eecs.umich.edu
3185234Sgblack@eecs.umich.edu        // Put valid values in all of the various table entries which indicate
3195234Sgblack@eecs.umich.edu        // that those entries don't point to further tables or pages. Then
3205234Sgblack@eecs.umich.edu        // set the values of those entries which are needed.
3215234Sgblack@eecs.umich.edu
3225234Sgblack@eecs.umich.edu        // Page Map Level 4
3235234Sgblack@eecs.umich.edu
3245234Sgblack@eecs.umich.edu        // read/write, user, not present
3255234Sgblack@eecs.umich.edu        uint64_t pml4e = X86ISA::htog(0x6);
3265234Sgblack@eecs.umich.edu        for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) {
3275234Sgblack@eecs.umich.edu            physPort->writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8);
3285234Sgblack@eecs.umich.edu        }
3295234Sgblack@eecs.umich.edu        // Point to the only PDPT
3305234Sgblack@eecs.umich.edu        pml4e = X86ISA::htog(0x7 | PageDirPtrTable);
3315234Sgblack@eecs.umich.edu        physPort->writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8);
3325234Sgblack@eecs.umich.edu
3335234Sgblack@eecs.umich.edu        // Page Directory Pointer Table
3345234Sgblack@eecs.umich.edu
3355234Sgblack@eecs.umich.edu        // read/write, user, not present
3365234Sgblack@eecs.umich.edu        uint64_t pdpe = X86ISA::htog(0x6);
3375234Sgblack@eecs.umich.edu        for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) {
3385234Sgblack@eecs.umich.edu            physPort->writeBlob(PageDirPtrTable + offset,
3395234Sgblack@eecs.umich.edu                    (uint8_t *)(&pdpe), 8);
3405234Sgblack@eecs.umich.edu        }
3415234Sgblack@eecs.umich.edu        // Point to the PDTs
3425234Sgblack@eecs.umich.edu        for (int table = 0; table < NumPDTs; table++) {
3435234Sgblack@eecs.umich.edu            pdpe = X86ISA::htog(0x7 | PageDirTable[table]);
3445234Sgblack@eecs.umich.edu            physPort->writeBlob(PageDirPtrTable + table * 8,
3455234Sgblack@eecs.umich.edu                    (uint8_t *)(&pdpe), 8);
3465234Sgblack@eecs.umich.edu        }
3475234Sgblack@eecs.umich.edu
3485234Sgblack@eecs.umich.edu        // Page Directory Tables
3495234Sgblack@eecs.umich.edu
3505234Sgblack@eecs.umich.edu        Addr base = 0;
3515234Sgblack@eecs.umich.edu        const Addr pageSize = 2 << 20;
3525234Sgblack@eecs.umich.edu        for (int table = 0; table < NumPDTs; table++) {
3535234Sgblack@eecs.umich.edu            for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) {
3545234Sgblack@eecs.umich.edu                // read/write, user, present, 4MB
3555234Sgblack@eecs.umich.edu                uint64_t pdte = X86ISA::htog(0x87 | base);
3565234Sgblack@eecs.umich.edu                physPort->writeBlob(PageDirTable[table] + offset,
3575234Sgblack@eecs.umich.edu                        (uint8_t *)(&pdte), 8);
3585234Sgblack@eecs.umich.edu                base += pageSize;
3595234Sgblack@eecs.umich.edu            }
3605234Sgblack@eecs.umich.edu        }
3615234Sgblack@eecs.umich.edu
3625234Sgblack@eecs.umich.edu        /*
3635234Sgblack@eecs.umich.edu         * Transition from real mode all the way up to Long mode
3645234Sgblack@eecs.umich.edu         */
3655234Sgblack@eecs.umich.edu        CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
3665234Sgblack@eecs.umich.edu        //Turn off paging.
3675234Sgblack@eecs.umich.edu        cr0.pg = 0;
3685234Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CR0, cr0);
3695234Sgblack@eecs.umich.edu        //Turn on protected mode.
3705234Sgblack@eecs.umich.edu        cr0.pe = 1;
3715234Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CR0, cr0);
3725234Sgblack@eecs.umich.edu
3735234Sgblack@eecs.umich.edu        CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
3745234Sgblack@eecs.umich.edu        //Turn on pae.
3755234Sgblack@eecs.umich.edu        cr4.pae = 1;
3765234Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CR4, cr4);
3775234Sgblack@eecs.umich.edu
3785234Sgblack@eecs.umich.edu        //Point to the page tables.
3795234Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CR3, PageMapLevel4);
3805234Sgblack@eecs.umich.edu
3815234Sgblack@eecs.umich.edu        Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
3825234Sgblack@eecs.umich.edu        //Enable long mode.
3835234Sgblack@eecs.umich.edu        efer.lme = 1;
3845234Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_EFER, efer);
3855234Sgblack@eecs.umich.edu
3865234Sgblack@eecs.umich.edu        //Activate long mode.
3875234Sgblack@eecs.umich.edu        cr0.pg = 1;
3885234Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CR0, cr0);
3895234Sgblack@eecs.umich.edu
3905234Sgblack@eecs.umich.edu        /*
3915234Sgblack@eecs.umich.edu         * Far jump into 64 bit mode.
3925234Sgblack@eecs.umich.edu         */
3935234Sgblack@eecs.umich.edu        // Set the selector
3945234Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CS, 1);
3955234Sgblack@eecs.umich.edu        // Manually set up the segment attributes. In the future when there's
3965234Sgblack@eecs.umich.edu        // other existing functionality to do this, that could be used
3975234Sgblack@eecs.umich.edu        // instead.
3985234Sgblack@eecs.umich.edu        SegAttr csAttr = 0;
3995234Sgblack@eecs.umich.edu        csAttr.writable = 0;
4005234Sgblack@eecs.umich.edu        csAttr.readable = 1;
4015234Sgblack@eecs.umich.edu        csAttr.expandDown = 0;
4025234Sgblack@eecs.umich.edu        csAttr.dpl = 0;
4035234Sgblack@eecs.umich.edu        csAttr.defaultSize = 0;
4045234Sgblack@eecs.umich.edu        csAttr.longMode = 1;
4055234Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CS_ATTR, csAttr);
4065234Sgblack@eecs.umich.edu
4075234Sgblack@eecs.umich.edu        tc->setPC(tc->getSystemPtr()->kernelEntry);
4085234Sgblack@eecs.umich.edu        tc->setNextPC(tc->readPC());
4095234Sgblack@eecs.umich.edu
4105234Sgblack@eecs.umich.edu        // We should now be in long mode. Yay!
4115135Sgblack@eecs.umich.edu
4125135Sgblack@eecs.umich.edu        tc->activate(0);
4135135Sgblack@eecs.umich.edu    } else {
4145135Sgblack@eecs.umich.edu        // This is an application processor (AP). It should be initialized to
4155135Sgblack@eecs.umich.edu        // look like only the BIOS POST has run on it and put then put it into
4165135Sgblack@eecs.umich.edu        // a halted state.
4175234Sgblack@eecs.umich.edu        tc->suspend();
4185135Sgblack@eecs.umich.edu    }
4195135Sgblack@eecs.umich.edu}
4205135Sgblack@eecs.umich.edu
4215234Sgblack@eecs.umich.edu#else
4225234Sgblack@eecs.umich.edu
4235234Sgblack@eecs.umich.eduvoid startupCPU(ThreadContext *tc, int cpuId)
4245234Sgblack@eecs.umich.edu{
4255234Sgblack@eecs.umich.edu    tc->activate(0);
4265234Sgblack@eecs.umich.edu}
4275234Sgblack@eecs.umich.edu
4285234Sgblack@eecs.umich.edu#endif
4295234Sgblack@eecs.umich.edu
4305086Sgblack@eecs.umich.edu} //namespace X86_ISA
431