types.cc revision 4342 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
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10 * use which is NOT directed to receiving any direct monetary
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12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
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17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
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24 *     Palo Alto, California  94304
25 *
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27 * this list of conditions and the following disclaimer.  Redistributions
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33 * this software without specific prior written permission.  No right of
34 * sublicense is granted herewith.  Derivatives of the software and
35 * output created using the software may be prepared, but only for
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37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_TYPES_HH__
59#define __ARCH_X86_TYPES_HH__
60
61#include <inttypes.h>
62#include <iostream>
63
64#include "base/bitfield.hh"
65#include "base/cprintf.hh"
66
67namespace X86ISA
68{
69    //This really determines how many bytes are passed to the predecoder.
70    typedef uint64_t MachInst;
71
72    enum Prefixes {
73        NoOverride,
74        CSOverride,
75        DSOverride,
76        ESOverride,
77        FSOverride,
78        GSOverride,
79        SSOverride,
80        RexPrefix,
81        OperandSizeOverride,
82        AddressSizeOverride,
83        Lock,
84        Rep,
85        Repne
86    };
87
88    BitUnion8(LegacyPrefixVector)
89        Bitfield<7> repne;
90        Bitfield<6> rep;
91        Bitfield<5> lock;
92        Bitfield<4> addr;
93        Bitfield<3> op;
94        //There can be only one segment override, so they share the
95        //first 3 bits in the legacyPrefixes bitfield.
96        Bitfield<2,0> seg;
97    EndBitUnion(LegacyPrefixVector)
98
99    BitUnion8(ModRM)
100        Bitfield<7,6> mod;
101        Bitfield<5,3> reg;
102        Bitfield<2,0> rm;
103    EndBitUnion(ModRM)
104
105    BitUnion8(Sib)
106        Bitfield<7,6> scale;
107        Bitfield<5,3> index;
108        Bitfield<2,0> base;
109    EndBitUnion(Sib)
110
111    BitUnion8(Rex)
112        Bitfield<3> w;
113        Bitfield<2> r;
114        Bitfield<1> x;
115        Bitfield<0> b;
116    EndBitUnion(Rex)
117
118    BitUnion8(Opcode)
119        Bitfield<7,3> top5;
120        Bitfield<2,0> bottom3;
121    EndBitUnion(Opcode)
122
123    //The intermediate structure the x86 predecoder returns.
124    struct ExtMachInst
125    {
126        //Prefixes
127        LegacyPrefixVector legacy;
128        Rex rex;
129        //This holds all of the bytes of the opcode
130        struct
131        {
132            //The number of bytes in this opcode. Right now, we ignore that
133            //this can be 3 in some cases
134            uint8_t num;
135            //The first byte detected in a 2+ byte opcode. Should be 0xF0.
136            uint8_t prefixA;
137            //The second byte detected in a 3+ byte opcode. Could be 0xF0 for
138            //3dnow instructions, or 0x38-0x3F for some SSE instructions.
139            uint8_t prefixB;
140            //The main opcode byte. The highest addressed byte in the opcode.
141            Opcode op;
142        } opcode;
143        //Modifier bytes
144        ModRM modRM;
145        uint8_t sib;
146        //Immediate fields
147        uint64_t immediate;
148        uint64_t displacement;
149
150        //The effective operand size.
151        uint8_t opSize;
152        //The
153    };
154
155    inline static std::ostream &
156        operator << (std::ostream & os, const ExtMachInst & emi)
157    {
158        ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t"
159                     "op = {\n\t\tnum = %d,\n\t\top = %#x,\n\t\t"
160                           "prefixA = %#x,\n\t\tprefixB = %#x\n\t},\n\t"
161                     "modRM = %#x,\n\tsib = %#x,\n\t"
162                     "immediate = %#x,\n\tdisplacement = %#x\n}\n",
163                     emi.legacy, (uint8_t)emi.rex,
164                     emi.opcode.num, emi.opcode.op,
165                     emi.opcode.prefixA, emi.opcode.prefixB,
166                     (uint8_t)emi.modRM, (uint8_t)emi.sib,
167                     emi.immediate, emi.displacement);
168        return os;
169    }
170
171    inline static bool
172        operator == (const ExtMachInst &emi1, const ExtMachInst &emi2)
173    {
174        if(emi1.legacy != emi2.legacy)
175            return false;
176        if(emi1.rex != emi2.rex)
177            return false;
178        if(emi1.opcode.num != emi2.opcode.num)
179            return false;
180        if(emi1.opcode.op != emi2.opcode.op)
181            return false;
182        if(emi1.opcode.prefixA != emi2.opcode.prefixA)
183            return false;
184        if(emi1.opcode.prefixB != emi2.opcode.prefixB)
185            return false;
186        if(emi1.modRM != emi2.modRM)
187            return false;
188        if(emi1.sib != emi2.sib)
189            return false;
190        if(emi1.immediate != emi2.immediate)
191            return false;
192        if(emi1.displacement != emi2.displacement)
193            return false;
194        return true;
195    }
196
197    typedef uint64_t IntReg;
198    //XXX Should this be a 128 bit structure for XMM memory ops?
199    typedef uint64_t LargestRead;
200    typedef uint64_t MiscReg;
201
202    //These floating point types are correct for mmx, but not
203    //technically for x87 (80 bits) or at all for xmm (128 bits)
204    typedef double FloatReg;
205    typedef uint64_t FloatRegBits;
206    typedef union
207    {
208        IntReg intReg;
209        FloatReg fpReg;
210        MiscReg ctrlReg;
211    } AnyReg;
212
213    //XXX This is very hypothetical. X87 instructions would need to
214    //change their "context" constantly. It's also not clear how
215    //this would be handled as far as out of order execution.
216    //Maybe x87 instructions are in order?
217    enum RegContextParam
218    {
219        CONTEXT_X87_TOP
220    };
221
222    typedef int RegContextVal;
223
224    typedef uint8_t RegIndex;
225};
226
227#endif // __ARCH_X86_TYPES_HH__
228