types.cc revision 4342
15245Sgblack@eecs.umich.edu/* 28948Sandreas.hansson@arm.com * Copyright (c) 2007 The Hewlett-Packard Development Company 38948Sandreas.hansson@arm.com * All rights reserved. 48948Sandreas.hansson@arm.com * 58948Sandreas.hansson@arm.com * Redistribution and use of this software in source and binary forms, 68948Sandreas.hansson@arm.com * with or without modification, are permitted provided that the 78948Sandreas.hansson@arm.com * following conditions are met: 88948Sandreas.hansson@arm.com * 98948Sandreas.hansson@arm.com * The software must be used only for Non-Commercial Use which means any 108948Sandreas.hansson@arm.com * use which is NOT directed to receiving any direct monetary 118948Sandreas.hansson@arm.com * compensation for, or commercial advantage from such use. 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Derivatives of the software may be shared with 375245Sgblack@eecs.umich.edu * others provided: (i) the others agree to abide by the list of 385245Sgblack@eecs.umich.edu * conditions herein which includes the Non-Commercial Use restrictions; 395245Sgblack@eecs.umich.edu * and (ii) such Derivatives of the software include the above copyright 405245Sgblack@eecs.umich.edu * notice to acknowledge the contribution from this software where 415245Sgblack@eecs.umich.edu * applicable, this list of conditions and the disclaimer below. 425245Sgblack@eecs.umich.edu * 435245Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 445245Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 455245Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 465245Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 475245Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 485245Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 495245Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 505245Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 515245Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 5211793Sbrandon.potter@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 5311793Sbrandon.potter@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 5410474Sandreas.hansson@arm.com * 5510474Sandreas.hansson@arm.com * Authors: Gabe Black 565245Sgblack@eecs.umich.edu */ 575245Sgblack@eecs.umich.edu 587912Shestness@cs.utexas.edu#ifndef __ARCH_X86_TYPES_HH__ 595245Sgblack@eecs.umich.edu#define __ARCH_X86_TYPES_HH__ 608953Sgblack@eecs.umich.edu 618229Snate@binkert.org#include <inttypes.h> 625245Sgblack@eecs.umich.edu#include <iostream> 638232Snate@binkert.org 645245Sgblack@eecs.umich.edu#include "base/bitfield.hh" 655245Sgblack@eecs.umich.edu#include "base/cprintf.hh" 665245Sgblack@eecs.umich.edu 675245Sgblack@eecs.umich.edunamespace X86ISA 685245Sgblack@eecs.umich.edu{ 695895Sgblack@eecs.umich.edu //This really determines how many bytes are passed to the predecoder. 707912Shestness@cs.utexas.edu typedef uint64_t MachInst; 7112749Sgiacomo.travaglini@arm.com 725245Sgblack@eecs.umich.edu enum Prefixes { 737912Shestness@cs.utexas.edu NoOverride, 747912Shestness@cs.utexas.edu CSOverride, 757912Shestness@cs.utexas.edu DSOverride, 767912Shestness@cs.utexas.edu ESOverride, 779524SAndreas.Sandberg@ARM.com FSOverride, 787912Shestness@cs.utexas.edu GSOverride, 797912Shestness@cs.utexas.edu SSOverride, 807912Shestness@cs.utexas.edu RexPrefix, 817912Shestness@cs.utexas.edu OperandSizeOverride, 827912Shestness@cs.utexas.edu AddressSizeOverride, 837912Shestness@cs.utexas.edu Lock, 847912Shestness@cs.utexas.edu Rep, 857912Shestness@cs.utexas.edu Repne 867912Shestness@cs.utexas.edu }; 877912Shestness@cs.utexas.edu 887912Shestness@cs.utexas.edu BitUnion8(LegacyPrefixVector) 895895Sgblack@eecs.umich.edu Bitfield<7> repne; 907912Shestness@cs.utexas.edu Bitfield<6> rep; 915245Sgblack@eecs.umich.edu Bitfield<5> lock; 925245Sgblack@eecs.umich.edu Bitfield<4> addr; 935245Sgblack@eecs.umich.edu Bitfield<3> op; 945895Sgblack@eecs.umich.edu //There can be only one segment override, so they share the 958953Sgblack@eecs.umich.edu //first 3 bits in the legacyPrefixes bitfield. 967912Shestness@cs.utexas.edu Bitfield<2,0> seg; 975245Sgblack@eecs.umich.edu EndBitUnion(LegacyPrefixVector) 987912Shestness@cs.utexas.edu 998953Sgblack@eecs.umich.edu BitUnion8(ModRM) 1005245Sgblack@eecs.umich.edu Bitfield<7,6> mod; 1015245Sgblack@eecs.umich.edu Bitfield<5,3> reg; 1025245Sgblack@eecs.umich.edu Bitfield<2,0> rm; 1038975Sandreas.hansson@arm.com EndBitUnion(ModRM) 1045245Sgblack@eecs.umich.edu 1058975Sandreas.hansson@arm.com BitUnion8(Sib) 1065245Sgblack@eecs.umich.edu Bitfield<7,6> scale; 1075245Sgblack@eecs.umich.edu Bitfield<5,3> index; 1085245Sgblack@eecs.umich.edu Bitfield<2,0> base; 1098975Sandreas.hansson@arm.com EndBitUnion(Sib) 1105245Sgblack@eecs.umich.edu 1118948Sandreas.hansson@arm.com BitUnion8(Rex) 1129542Sandreas.hansson@arm.com Bitfield<3> w; 1138948Sandreas.hansson@arm.com Bitfield<2> r; 1148948Sandreas.hansson@arm.com Bitfield<1> x; 1158948Sandreas.hansson@arm.com Bitfield<0> b; 1168948Sandreas.hansson@arm.com EndBitUnion(Rex) 1178948Sandreas.hansson@arm.com 1188948Sandreas.hansson@arm.com BitUnion8(Opcode) 1198948Sandreas.hansson@arm.com Bitfield<7,3> top5; 1208948Sandreas.hansson@arm.com Bitfield<2,0> bottom3; 1218948Sandreas.hansson@arm.com EndBitUnion(Opcode) 1228948Sandreas.hansson@arm.com 1235895Sgblack@eecs.umich.edu //The intermediate structure the x86 predecoder returns. 1245245Sgblack@eecs.umich.edu struct ExtMachInst 1258948Sandreas.hansson@arm.com { 1268948Sandreas.hansson@arm.com //Prefixes 1278948Sandreas.hansson@arm.com LegacyPrefixVector legacy; 12810654Sandreas.hansson@arm.com Rex rex; 12910654Sandreas.hansson@arm.com //This holds all of the bytes of the opcode 13010654Sandreas.hansson@arm.com struct 13110654Sandreas.hansson@arm.com { 1325245Sgblack@eecs.umich.edu //The number of bytes in this opcode. Right now, we ignore that 1335245Sgblack@eecs.umich.edu //this can be 3 in some cases 1345245Sgblack@eecs.umich.edu uint8_t num; 1355245Sgblack@eecs.umich.edu //The first byte detected in a 2+ byte opcode. Should be 0xF0. 1365245Sgblack@eecs.umich.edu uint8_t prefixA; 13710713Sandreas.hansson@arm.com //The second byte detected in a 3+ byte opcode. Could be 0xF0 for 1385245Sgblack@eecs.umich.edu //3dnow instructions, or 0x38-0x3F for some SSE instructions. 13910713Sandreas.hansson@arm.com uint8_t prefixB; 1405245Sgblack@eecs.umich.edu //The main opcode byte. The highest addressed byte in the opcode. 1415245Sgblack@eecs.umich.edu Opcode op; 1425245Sgblack@eecs.umich.edu } opcode; 14310713Sandreas.hansson@arm.com //Modifier bytes 1445245Sgblack@eecs.umich.edu ModRM modRM; 1457912Shestness@cs.utexas.edu uint8_t sib; 1467912Shestness@cs.utexas.edu //Immediate fields 1477912Shestness@cs.utexas.edu uint64_t immediate; 1487912Shestness@cs.utexas.edu uint64_t displacement; 1497912Shestness@cs.utexas.edu 1507912Shestness@cs.utexas.edu //The effective operand size. 1517912Shestness@cs.utexas.edu uint8_t opSize; 1527912Shestness@cs.utexas.edu //The 1537912Shestness@cs.utexas.edu }; 1547912Shestness@cs.utexas.edu 1557912Shestness@cs.utexas.edu inline static std::ostream & 15610018Sandreas.hansson@arm.com operator << (std::ostream & os, const ExtMachInst & emi) 15710018Sandreas.hansson@arm.com { 15810018Sandreas.hansson@arm.com ccprintf(os, "\n{\n\tleg = %#x,\n\trex = %#x,\n\t" 15910018Sandreas.hansson@arm.com "op = {\n\t\tnum = %d,\n\t\top = %#x,\n\t\t" 16010018Sandreas.hansson@arm.com "prefixA = %#x,\n\t\tprefixB = %#x\n\t},\n\t" 16110018Sandreas.hansson@arm.com "modRM = %#x,\n\tsib = %#x,\n\t" 16210018Sandreas.hansson@arm.com "immediate = %#x,\n\tdisplacement = %#x\n}\n", 16310018Sandreas.hansson@arm.com emi.legacy, (uint8_t)emi.rex, 16410018Sandreas.hansson@arm.com emi.opcode.num, emi.opcode.op, 16510018Sandreas.hansson@arm.com emi.opcode.prefixA, emi.opcode.prefixB, 16610018Sandreas.hansson@arm.com (uint8_t)emi.modRM, (uint8_t)emi.sib, 16710018Sandreas.hansson@arm.com emi.immediate, emi.displacement); 1687912Shestness@cs.utexas.edu return os; 1697912Shestness@cs.utexas.edu } 17013784Sgabeblack@google.com 17113784Sgabeblack@google.com inline static bool 1727912Shestness@cs.utexas.edu operator == (const ExtMachInst &emi1, const ExtMachInst &emi2) 1737912Shestness@cs.utexas.edu { 1748922Swilliam.wang@arm.com if(emi1.legacy != emi2.legacy) 1757912Shestness@cs.utexas.edu return false; 17613892Sgabeblack@google.com if(emi1.rex != emi2.rex) 1775245Sgblack@eecs.umich.edu return false; 1785245Sgblack@eecs.umich.edu if(emi1.opcode.num != emi2.opcode.num) 1795245Sgblack@eecs.umich.edu return false; 1807912Shestness@cs.utexas.edu if(emi1.opcode.op != emi2.opcode.op) 1817912Shestness@cs.utexas.edu return false; 1827912Shestness@cs.utexas.edu if(emi1.opcode.prefixA != emi2.opcode.prefixA) 1837912Shestness@cs.utexas.edu return false; 1847912Shestness@cs.utexas.edu if(emi1.opcode.prefixB != emi2.opcode.prefixB) 1857912Shestness@cs.utexas.edu return false; 1867912Shestness@cs.utexas.edu if(emi1.modRM != emi2.modRM) 1877912Shestness@cs.utexas.edu return false; 1887912Shestness@cs.utexas.edu if(emi1.sib != emi2.sib) 1897912Shestness@cs.utexas.edu return false; 1909701Sgedare@rtems.org if(emi1.immediate != emi2.immediate) 1919701Sgedare@rtems.org return false; 1929701Sgedare@rtems.org if(emi1.displacement != emi2.displacement) 1939701Sgedare@rtems.org return false; 1949701Sgedare@rtems.org return true; 1959701Sgedare@rtems.org } 1969701Sgedare@rtems.org 1979701Sgedare@rtems.org typedef uint64_t IntReg; 1989701Sgedare@rtems.org //XXX Should this be a 128 bit structure for XMM memory ops? 1999701Sgedare@rtems.org typedef uint64_t LargestRead; 2009701Sgedare@rtems.org typedef uint64_t MiscReg; 2019701Sgedare@rtems.org 2029701Sgedare@rtems.org //These floating point types are correct for mmx, but not 2039701Sgedare@rtems.org //technically for x87 (80 bits) or at all for xmm (128 bits) 20410474Sandreas.hansson@arm.com typedef double FloatReg; 20510474Sandreas.hansson@arm.com typedef uint64_t FloatRegBits; 20610474Sandreas.hansson@arm.com typedef union 2079701Sgedare@rtems.org { 20814096Smatthew.poremba@amd.com IntReg intReg; 20914096Smatthew.poremba@amd.com FloatReg fpReg; 21014096Smatthew.poremba@amd.com MiscReg ctrlReg; 21114096Smatthew.poremba@amd.com } AnyReg; 21214096Smatthew.poremba@amd.com 21314096Smatthew.poremba@amd.com //XXX This is very hypothetical. X87 instructions would need to 21414096Smatthew.poremba@amd.com //change their "context" constantly. It's also not clear how 21514096Smatthew.poremba@amd.com //this would be handled as far as out of order execution. 2169701Sgedare@rtems.org //Maybe x87 instructions are in order? 2179701Sgedare@rtems.org enum RegContextParam 2189701Sgedare@rtems.org { 2199701Sgedare@rtems.org CONTEXT_X87_TOP 2209701Sgedare@rtems.org }; 2219701Sgedare@rtems.org 2229701Sgedare@rtems.org typedef int RegContextVal; 2239701Sgedare@rtems.org 2249701Sgedare@rtems.org typedef uint8_t RegIndex; 2259701Sgedare@rtems.org}; 2269701Sgedare@rtems.org 2277912Shestness@cs.utexas.edu#endif // __ARCH_X86_TYPES_HH__ 2287912Shestness@cs.utexas.edu