misc.hh revision 6346
1/* 2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * 9 * The software must be used only for Non-Commercial Use which means any 10 * use which is NOT directed to receiving any direct monetary 11 * compensation for, or commercial advantage from such use. Illustrative 12 * examples of non-commercial use are academic research, personal study, 13 * teaching, education and corporate research & development. 14 * Illustrative examples of commercial use are distributing products for 15 * commercial advantage and providing services using the software for 16 * commercial advantage. 17 * 18 * If you wish to use this software or functionality therein that may be 19 * covered by patents for commercial use, please contact: 20 * Director of Intellectual Property Licensing 21 * Office of Strategy and Technology 22 * Hewlett-Packard Company 23 * 1501 Page Mill Road 24 * Palo Alto, California 94304 25 * 26 * Redistributions of source code must retain the above copyright notice, 27 * this list of conditions and the following disclaimer. Redistributions 28 * in binary form must reproduce the above copyright notice, this list of 29 * conditions and the following disclaimer in the documentation and/or 30 * other materials provided with the distribution. Neither the name of 31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 32 * contributors may be used to endorse or promote products derived from 33 * this software without specific prior written permission. No right of 34 * sublicense is granted herewith. Derivatives of the software and 35 * output created using the software may be prepared, but only for 36 * Non-Commercial Uses. Derivatives of the software may be shared with 37 * others provided: (i) the others agree to abide by the list of 38 * conditions herein which includes the Non-Commercial Use restrictions; 39 * and (ii) such Derivatives of the software include the above copyright 40 * notice to acknowledge the contribution from this software where 41 * applicable, this list of conditions and the disclaimer below. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * 55 * Authors: Gabe Black 56 */ 57 58#ifndef __ARCH_X86_MISCREGS_HH__ 59#define __ARCH_X86_MISCREGS_HH__ 60 61#include "arch/x86/segmentregs.hh" 62#include "arch/x86/x86_traits.hh" 63#include "base/bitunion.hh" 64 65//These get defined in some system headers (at least termbits.h). That confuses 66//things here significantly. 67#undef CR0 68#undef CR2 69#undef CR3 70 71namespace X86ISA 72{ 73 enum CondFlagBit { 74 CFBit = 1 << 0, 75 PFBit = 1 << 2, 76 ECFBit = 1 << 3, 77 AFBit = 1 << 4, 78 EZFBit = 1 << 5, 79 ZFBit = 1 << 6, 80 SFBit = 1 << 7, 81 DFBit = 1 << 10, 82 OFBit = 1 << 11 83 }; 84 85 enum RFLAGBit { 86 TFBit = 1 << 8, 87 IFBit = 1 << 9, 88 NTBit = 1 << 14, 89 RFBit = 1 << 16, 90 VMBit = 1 << 17, 91 ACBit = 1 << 18, 92 VIFBit = 1 << 19, 93 VIPBit = 1 << 20, 94 IDBit = 1 << 21 95 }; 96 97 enum MiscRegIndex 98 { 99 // Control registers 100 // Most of these are invalid. 101 MISCREG_CR_BASE, 102 MISCREG_CR0 = MISCREG_CR_BASE, 103 MISCREG_CR1, 104 MISCREG_CR2, 105 MISCREG_CR3, 106 MISCREG_CR4, 107 MISCREG_CR5, 108 MISCREG_CR6, 109 MISCREG_CR7, 110 MISCREG_CR8, 111 MISCREG_CR9, 112 MISCREG_CR10, 113 MISCREG_CR11, 114 MISCREG_CR12, 115 MISCREG_CR13, 116 MISCREG_CR14, 117 MISCREG_CR15, 118 119 // Debug registers 120 MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs, 121 MISCREG_DR0 = MISCREG_DR_BASE, 122 MISCREG_DR1, 123 MISCREG_DR2, 124 MISCREG_DR3, 125 MISCREG_DR4, 126 MISCREG_DR5, 127 MISCREG_DR6, 128 MISCREG_DR7, 129 130 // Flags register 131 MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs, 132 133 //Register to keep handy values like the CPU mode in. 134 MISCREG_M5_REG, 135 136 /* 137 * Model Specific Registers 138 */ 139 // Time stamp counter 140 MISCREG_TSC, 141 142 MISCREG_MTRRCAP, 143 144 MISCREG_SYSENTER_CS, 145 MISCREG_SYSENTER_ESP, 146 MISCREG_SYSENTER_EIP, 147 148 MISCREG_MCG_CAP, 149 MISCREG_MCG_STATUS, 150 MISCREG_MCG_CTL, 151 152 MISCREG_DEBUG_CTL_MSR, 153 154 MISCREG_LAST_BRANCH_FROM_IP, 155 MISCREG_LAST_BRANCH_TO_IP, 156 MISCREG_LAST_EXCEPTION_FROM_IP, 157 MISCREG_LAST_EXCEPTION_TO_IP, 158 159 MISCREG_MTRR_PHYS_BASE_BASE, 160 MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE, 161 MISCREG_MTRR_PHYS_BASE_1, 162 MISCREG_MTRR_PHYS_BASE_2, 163 MISCREG_MTRR_PHYS_BASE_3, 164 MISCREG_MTRR_PHYS_BASE_4, 165 MISCREG_MTRR_PHYS_BASE_5, 166 MISCREG_MTRR_PHYS_BASE_6, 167 MISCREG_MTRR_PHYS_BASE_7, 168 MISCREG_MTRR_PHYS_BASE_END, 169 170 MISCREG_MTRR_PHYS_MASK_BASE = MISCREG_MTRR_PHYS_BASE_END, 171 MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE, 172 MISCREG_MTRR_PHYS_MASK_1, 173 MISCREG_MTRR_PHYS_MASK_2, 174 MISCREG_MTRR_PHYS_MASK_3, 175 MISCREG_MTRR_PHYS_MASK_4, 176 MISCREG_MTRR_PHYS_MASK_5, 177 MISCREG_MTRR_PHYS_MASK_6, 178 MISCREG_MTRR_PHYS_MASK_7, 179 MISCREG_MTRR_PHYS_MASK_END, 180 181 MISCREG_MTRR_FIX_64K_00000 = MISCREG_MTRR_PHYS_MASK_END, 182 MISCREG_MTRR_FIX_16K_80000, 183 MISCREG_MTRR_FIX_16K_A0000, 184 MISCREG_MTRR_FIX_4K_C0000, 185 MISCREG_MTRR_FIX_4K_C8000, 186 MISCREG_MTRR_FIX_4K_D0000, 187 MISCREG_MTRR_FIX_4K_D8000, 188 MISCREG_MTRR_FIX_4K_E0000, 189 MISCREG_MTRR_FIX_4K_E8000, 190 MISCREG_MTRR_FIX_4K_F0000, 191 MISCREG_MTRR_FIX_4K_F8000, 192 193 MISCREG_PAT, 194 195 MISCREG_DEF_TYPE, 196 197 MISCREG_MC_CTL_BASE, 198 MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE, 199 MISCREG_MC1_CTL, 200 MISCREG_MC2_CTL, 201 MISCREG_MC3_CTL, 202 MISCREG_MC4_CTL, 203 MISCREG_MC5_CTL, 204 MISCREG_MC6_CTL, 205 MISCREG_MC7_CTL, 206 MISCREG_MC_CTL_END, 207 208 MISCREG_MC_STATUS_BASE = MISCREG_MC_CTL_END, 209 MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE, 210 MISCREG_MC1_STATUS, 211 MISCREG_MC2_STATUS, 212 MISCREG_MC3_STATUS, 213 MISCREG_MC4_STATUS, 214 MISCREG_MC5_STATUS, 215 MISCREG_MC6_STATUS, 216 MISCREG_MC7_STATUS, 217 MISCREG_MC_STATUS_END, 218 219 MISCREG_MC_ADDR_BASE = MISCREG_MC_STATUS_END, 220 MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE, 221 MISCREG_MC1_ADDR, 222 MISCREG_MC2_ADDR, 223 MISCREG_MC3_ADDR, 224 MISCREG_MC4_ADDR, 225 MISCREG_MC5_ADDR, 226 MISCREG_MC6_ADDR, 227 MISCREG_MC7_ADDR, 228 MISCREG_MC_ADDR_END, 229 230 MISCREG_MC_MISC_BASE = MISCREG_MC_ADDR_END, 231 MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE, 232 MISCREG_MC1_MISC, 233 MISCREG_MC2_MISC, 234 MISCREG_MC3_MISC, 235 MISCREG_MC4_MISC, 236 MISCREG_MC5_MISC, 237 MISCREG_MC6_MISC, 238 MISCREG_MC7_MISC, 239 MISCREG_MC_MISC_END, 240 241 // Extended feature enable register 242 MISCREG_EFER = MISCREG_MC_MISC_END, 243 244 MISCREG_STAR, 245 MISCREG_LSTAR, 246 MISCREG_CSTAR, 247 248 MISCREG_SF_MASK, 249 250 MISCREG_KERNEL_GS_BASE, 251 252 MISCREG_TSC_AUX, 253 254 MISCREG_PERF_EVT_SEL_BASE, 255 MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE, 256 MISCREG_PERF_EVT_SEL1, 257 MISCREG_PERF_EVT_SEL2, 258 MISCREG_PERF_EVT_SEL3, 259 MISCREG_PERF_EVT_SEL_END, 260 261 MISCREG_PERF_EVT_CTR_BASE = MISCREG_PERF_EVT_SEL_END, 262 MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE, 263 MISCREG_PERF_EVT_CTR1, 264 MISCREG_PERF_EVT_CTR2, 265 MISCREG_PERF_EVT_CTR3, 266 MISCREG_PERF_EVT_CTR_END, 267 268 MISCREG_SYSCFG = MISCREG_PERF_EVT_CTR_END, 269 270 MISCREG_IORR_BASE_BASE, 271 MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE, 272 MISCREG_IORR_BASE1, 273 MISCREG_IORR_BASE_END, 274 275 MISCREG_IORR_MASK_BASE = MISCREG_IORR_BASE_END, 276 MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE, 277 MISCREG_IORR_MASK1, 278 MISCREG_IORR_MASK_END, 279 280 MISCREG_TOP_MEM = MISCREG_IORR_MASK_END, 281 MISCREG_TOP_MEM2, 282 283 MISCREG_VM_CR, 284 MISCREG_IGNNE, 285 MISCREG_SMM_CTL, 286 MISCREG_VM_HSAVE_PA, 287 288 /* 289 * Segment registers 290 */ 291 // Segment selectors 292 MISCREG_SEG_SEL_BASE, 293 MISCREG_ES = MISCREG_SEG_SEL_BASE, 294 MISCREG_CS, 295 MISCREG_SS, 296 MISCREG_DS, 297 MISCREG_FS, 298 MISCREG_GS, 299 MISCREG_HS, 300 MISCREG_TSL, 301 MISCREG_TSG, 302 MISCREG_LS, 303 MISCREG_MS, 304 MISCREG_TR, 305 MISCREG_IDTR, 306 307 // Hidden segment base field 308 MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS, 309 MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE, 310 MISCREG_CS_BASE, 311 MISCREG_SS_BASE, 312 MISCREG_DS_BASE, 313 MISCREG_FS_BASE, 314 MISCREG_GS_BASE, 315 MISCREG_HS_BASE, 316 MISCREG_TSL_BASE, 317 MISCREG_TSG_BASE, 318 MISCREG_LS_BASE, 319 MISCREG_MS_BASE, 320 MISCREG_TR_BASE, 321 MISCREG_IDTR_BASE, 322 323 // The effective segment base, ie what is actually added to an 324 // address. In 64 bit mode this can be different from the above, 325 // namely 0. 326 MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS, 327 MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE, 328 MISCREG_CS_EFF_BASE, 329 MISCREG_SS_EFF_BASE, 330 MISCREG_DS_EFF_BASE, 331 MISCREG_FS_EFF_BASE, 332 MISCREG_GS_EFF_BASE, 333 MISCREG_HS_EFF_BASE, 334 MISCREG_TSL_EFF_BASE, 335 MISCREG_TSG_EFF_BASE, 336 MISCREG_LS_EFF_BASE, 337 MISCREG_MS_EFF_BASE, 338 MISCREG_TR_EFF_BASE, 339 MISCREG_IDTR_EFF_BASE, 340 341 // Hidden segment limit field 342 MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS, 343 MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE, 344 MISCREG_CS_LIMIT, 345 MISCREG_SS_LIMIT, 346 MISCREG_DS_LIMIT, 347 MISCREG_FS_LIMIT, 348 MISCREG_GS_LIMIT, 349 MISCREG_HS_LIMIT, 350 MISCREG_TSL_LIMIT, 351 MISCREG_TSG_LIMIT, 352 MISCREG_LS_LIMIT, 353 MISCREG_MS_LIMIT, 354 MISCREG_TR_LIMIT, 355 MISCREG_IDTR_LIMIT, 356 357 // Hidden segment limit attributes 358 MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS, 359 MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE, 360 MISCREG_CS_ATTR, 361 MISCREG_SS_ATTR, 362 MISCREG_DS_ATTR, 363 MISCREG_FS_ATTR, 364 MISCREG_GS_ATTR, 365 MISCREG_HS_ATTR, 366 MISCREG_TSL_ATTR, 367 MISCREG_TSG_ATTR, 368 MISCREG_LS_ATTR, 369 MISCREG_MS_ATTR, 370 MISCREG_TR_ATTR, 371 MISCREG_IDTR_ATTR, 372 373 // Floating point control registers 374 MISCREG_X87_TOP = 375 MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS, 376 377 //XXX Add "Model-Specific Registers" 378 379 MISCREG_APIC_BASE, 380 381 // "Fake" MSRs for internally implemented devices 382 MISCREG_PCI_CONFIG_ADDRESS, 383 384 NUM_MISCREGS 385 }; 386 387 static inline MiscRegIndex 388 MISCREG_CR(int index) 389 { 390 assert(index >= 0 && index < NumCRegs); 391 return (MiscRegIndex)(MISCREG_CR_BASE + index); 392 } 393 394 static inline MiscRegIndex 395 MISCREG_DR(int index) 396 { 397 assert(index >= 0 && index < NumDRegs); 398 return (MiscRegIndex)(MISCREG_DR_BASE + index); 399 } 400 401 static inline MiscRegIndex 402 MISCREG_MTRR_PHYS_BASE(int index) 403 { 404 assert(index >= 0 && index < (MISCREG_MTRR_PHYS_BASE_END - 405 MISCREG_MTRR_PHYS_BASE_BASE)); 406 return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index); 407 } 408 409 static inline MiscRegIndex 410 MISCREG_MTRR_PHYS_MASK(int index) 411 { 412 assert(index >= 0 && index < (MISCREG_MTRR_PHYS_MASK_END - 413 MISCREG_MTRR_PHYS_MASK_BASE)); 414 return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index); 415 } 416 417 static inline MiscRegIndex 418 MISCREG_MC_CTL(int index) 419 { 420 assert(index >= 0 && index < (MISCREG_MC_CTL_END - 421 MISCREG_MC_CTL_BASE)); 422 return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index); 423 } 424 425 static inline MiscRegIndex 426 MISCREG_MC_STATUS(int index) 427 { 428 assert(index >= 0 && index < (MISCREG_MC_STATUS_END - 429 MISCREG_MC_STATUS_BASE)); 430 return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index); 431 } 432 433 static inline MiscRegIndex 434 MISCREG_MC_ADDR(int index) 435 { 436 assert(index >= 0 && index < (MISCREG_MC_ADDR_END - 437 MISCREG_MC_ADDR_BASE)); 438 return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index); 439 } 440 441 static inline MiscRegIndex 442 MISCREG_MC_MISC(int index) 443 { 444 assert(index >= 0 && index < (MISCREG_MC_MISC_END - 445 MISCREG_MC_MISC_BASE)); 446 return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index); 447 } 448 449 static inline MiscRegIndex 450 MISCREG_PERF_EVT_SEL(int index) 451 { 452 assert(index >= 0 && index < (MISCREG_PERF_EVT_SEL_END - 453 MISCREG_PERF_EVT_SEL_BASE)); 454 return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index); 455 } 456 457 static inline MiscRegIndex 458 MISCREG_PERF_EVT_CTR(int index) 459 { 460 assert(index >= 0 && index < (MISCREG_PERF_EVT_CTR_END - 461 MISCREG_PERF_EVT_CTR_BASE)); 462 return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index); 463 } 464 465 static inline MiscRegIndex 466 MISCREG_IORR_BASE(int index) 467 { 468 assert(index >= 0 && index < (MISCREG_IORR_BASE_END - 469 MISCREG_IORR_BASE_BASE)); 470 return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index); 471 } 472 473 static inline MiscRegIndex 474 MISCREG_IORR_MASK(int index) 475 { 476 assert(index >= 0 && index < (MISCREG_IORR_MASK_END - 477 MISCREG_IORR_MASK_BASE)); 478 return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index); 479 } 480 481 static inline MiscRegIndex 482 MISCREG_SEG_SEL(int index) 483 { 484 assert(index >= 0 && index < NUM_SEGMENTREGS); 485 return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index); 486 } 487 488 static inline MiscRegIndex 489 MISCREG_SEG_BASE(int index) 490 { 491 assert(index >= 0 && index < NUM_SEGMENTREGS); 492 return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index); 493 } 494 495 static inline MiscRegIndex 496 MISCREG_SEG_EFF_BASE(int index) 497 { 498 assert(index >= 0 && index < NUM_SEGMENTREGS); 499 return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index); 500 } 501 502 static inline MiscRegIndex 503 MISCREG_SEG_LIMIT(int index) 504 { 505 assert(index >= 0 && index < NUM_SEGMENTREGS); 506 return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index); 507 } 508 509 static inline MiscRegIndex 510 MISCREG_SEG_ATTR(int index) 511 { 512 assert(index >= 0 && index < NUM_SEGMENTREGS); 513 return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index); 514 } 515 516 /** 517 * A type to describe the condition code bits of the RFLAGS register, 518 * plus two flags, EZF and ECF, which are only visible to microcode. 519 */ 520 BitUnion64(CCFlagBits) 521 Bitfield<11> of; 522 Bitfield<7> sf; 523 Bitfield<6> zf; 524 Bitfield<5> ezf; 525 Bitfield<4> af; 526 Bitfield<3> ecf; 527 Bitfield<2> pf; 528 Bitfield<0> cf; 529 EndBitUnion(CCFlagBits) 530 531 /** 532 * RFLAGS 533 */ 534 BitUnion64(RFLAGS) 535 Bitfield<21> id; // ID Flag 536 Bitfield<20> vip; // Virtual Interrupt Pending 537 Bitfield<19> vif; // Virtual Interrupt Flag 538 Bitfield<18> ac; // Alignment Check 539 Bitfield<17> vm; // Virtual-8086 Mode 540 Bitfield<16> rf; // Resume Flag 541 Bitfield<14> nt; // Nested Task 542 Bitfield<13, 12> iopl; // I/O Privilege Level 543 Bitfield<11> of; // Overflow Flag 544 Bitfield<10> df; // Direction Flag 545 Bitfield<9> intf; // Interrupt Flag 546 Bitfield<8> tf; // Trap Flag 547 Bitfield<7> sf; // Sign Flag 548 Bitfield<6> zf; // Zero Flag 549 Bitfield<4> af; // Auxiliary Flag 550 Bitfield<2> pf; // Parity Flag 551 Bitfield<0> cf; // Carry Flag 552 EndBitUnion(RFLAGS) 553 554 BitUnion64(HandyM5Reg) 555 Bitfield<0> mode; 556 Bitfield<3, 1> submode; 557 Bitfield<5, 4> cpl; 558 Bitfield<6> paging; 559 Bitfield<7> prot; 560 Bitfield<9, 8> defOp; 561 Bitfield<11, 10> altOp; 562 Bitfield<13, 12> defAddr; 563 Bitfield<15, 14> altAddr; 564 Bitfield<17, 16> stack; 565 EndBitUnion(HandyM5Reg) 566 567 /** 568 * Control registers 569 */ 570 BitUnion64(CR0) 571 Bitfield<31> pg; // Paging 572 Bitfield<30> cd; // Cache Disable 573 Bitfield<29> nw; // Not Writethrough 574 Bitfield<18> am; // Alignment Mask 575 Bitfield<16> wp; // Write Protect 576 Bitfield<5> ne; // Numeric Error 577 Bitfield<4> et; // Extension Type 578 Bitfield<3> ts; // Task Switched 579 Bitfield<2> em; // Emulation 580 Bitfield<1> mp; // Monitor Coprocessor 581 Bitfield<0> pe; // Protection Enabled 582 EndBitUnion(CR0) 583 584 // Page Fault Virtual Address 585 BitUnion64(CR2) 586 Bitfield<31, 0> legacy; 587 EndBitUnion(CR2) 588 589 BitUnion64(CR3) 590 Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table 591 // Base Address 592 Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table 593 // Base Address 594 Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table 595 // Base Address 596 Bitfield<4> pcd; // Page-Level Cache Disable 597 Bitfield<3> pwt; // Page-Level Writethrough 598 EndBitUnion(CR3) 599 600 BitUnion64(CR4) 601 Bitfield<10> osxmmexcpt; // Operating System Unmasked 602 // Exception Support 603 Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support 604 Bitfield<8> pce; // Performance-Monitoring Counter Enable 605 Bitfield<7> pge; // Page-Global Enable 606 Bitfield<6> mce; // Machine Check Enable 607 Bitfield<5> pae; // Physical-Address Extension 608 Bitfield<4> pse; // Page Size Extensions 609 Bitfield<3> de; // Debugging Extensions 610 Bitfield<2> tsd; // Time Stamp Disable 611 Bitfield<1> pvi; // Protected-Mode Virtual Interrupts 612 Bitfield<0> vme; // Virtual-8086 Mode Extensions 613 EndBitUnion(CR4) 614 615 BitUnion64(CR8) 616 Bitfield<3, 0> tpr; // Task Priority Register 617 EndBitUnion(CR8) 618 619 BitUnion64(DR6) 620 Bitfield<0> b0; 621 Bitfield<1> b1; 622 Bitfield<2> b2; 623 Bitfield<3> b3; 624 Bitfield<13> bd; 625 Bitfield<14> bs; 626 Bitfield<15> bt; 627 EndBitUnion(DR6) 628 629 BitUnion64(DR7) 630 Bitfield<0> l0; 631 Bitfield<1> g0; 632 Bitfield<2> l1; 633 Bitfield<3> g1; 634 Bitfield<4> l2; 635 Bitfield<5> g2; 636 Bitfield<6> l3; 637 Bitfield<7> g3; 638 Bitfield<8> le; 639 Bitfield<9> ge; 640 Bitfield<13> gd; 641 Bitfield<17, 16> rw0; 642 Bitfield<19, 18> len0; 643 Bitfield<21, 20> rw1; 644 Bitfield<23, 22> len1; 645 Bitfield<25, 24> rw2; 646 Bitfield<27, 26> len2; 647 Bitfield<29, 28> rw3; 648 Bitfield<31, 30> len3; 649 EndBitUnion(DR7) 650 651 // MTRR capabilities 652 BitUnion64(MTRRcap) 653 Bitfield<7, 0> vcnt; // Variable-Range Register Count 654 Bitfield<8> fix; // Fixed-Range Registers 655 Bitfield<10> wc; // Write-Combining 656 EndBitUnion(MTRRcap) 657 658 /** 659 * SYSENTER configuration registers 660 */ 661 BitUnion64(SysenterCS) 662 Bitfield<15, 0> targetCS; 663 EndBitUnion(SysenterCS) 664 665 BitUnion64(SysenterESP) 666 Bitfield<31, 0> targetESP; 667 EndBitUnion(SysenterESP) 668 669 BitUnion64(SysenterEIP) 670 Bitfield<31, 0> targetEIP; 671 EndBitUnion(SysenterEIP) 672 673 /** 674 * Global machine check registers 675 */ 676 BitUnion64(McgCap) 677 Bitfield<7, 0> count; // Number of error reporting register banks 678 Bitfield<8> MCGCP; // MCG_CTL register present. 679 EndBitUnion(McgCap) 680 681 BitUnion64(McgStatus) 682 Bitfield<0> ripv; // Restart-IP valid 683 Bitfield<1> eipv; // Error-IP valid 684 Bitfield<2> mcip; // Machine check in-progress 685 EndBitUnion(McgStatus) 686 687 BitUnion64(DebugCtlMsr) 688 Bitfield<0> lbr; // Last-branch record 689 Bitfield<1> btf; // Branch single step 690 Bitfield<2> pb0; // Performance monitoring pin control 0 691 Bitfield<3> pb1; // Performance monitoring pin control 1 692 Bitfield<4> pb2; // Performance monitoring pin control 2 693 Bitfield<5> pb3; // Performance monitoring pin control 3 694 /*uint64_t pb(int index) 695 { 696 return bits(__data, index + 2); 697 }*/ 698 EndBitUnion(DebugCtlMsr) 699 700 BitUnion64(MtrrPhysBase) 701 Bitfield<7, 0> type; // Default memory type 702 Bitfield<51, 12> physbase; // Range physical base address 703 EndBitUnion(MtrrPhysBase) 704 705 BitUnion64(MtrrPhysMask) 706 Bitfield<11> valid; // MTRR pair enable 707 Bitfield<51, 12> physmask; // Range physical mask 708 EndBitUnion(MtrrPhysMask) 709 710 BitUnion64(MtrrFixed) 711 /*uint64_t type(int index) 712 { 713 return bits(__data, index * 8 + 7, index * 8); 714 }*/ 715 EndBitUnion(MtrrFixed) 716 717 BitUnion64(Pat) 718 /*uint64_t pa(int index) 719 { 720 return bits(__data, index * 8 + 2, index * 8); 721 }*/ 722 EndBitUnion(Pat) 723 724 BitUnion64(MtrrDefType) 725 Bitfield<7, 0> type; // Default type 726 Bitfield<10> fe; // Fixed range enable 727 Bitfield<11> e; // MTRR enable 728 EndBitUnion(MtrrDefType) 729 730 /** 731 * Machine check 732 */ 733 BitUnion64(McStatus) 734 Bitfield<15,0> mcaErrorCode; 735 Bitfield<31,16> modelSpecificCode; 736 Bitfield<56,32> otherInfo; 737 Bitfield<57> pcc; // Processor-context corrupt 738 Bitfield<58> addrv; // Error-address register valid 739 Bitfield<59> miscv; // Miscellaneous-error register valid 740 Bitfield<60> en; // Error condition enabled 741 Bitfield<61> uc; // Uncorrected error 742 Bitfield<62> over; // Status register overflow 743 Bitfield<63> val; // Valid 744 EndBitUnion(McStatus) 745 746 BitUnion64(McCtl) 747 /*uint64_t en(int index) 748 { 749 return bits(__data, index); 750 }*/ 751 EndBitUnion(McCtl) 752 753 // Extended feature enable register 754 BitUnion64(Efer) 755 Bitfield<0> sce; // System call extensions 756 Bitfield<8> lme; // Long mode enable 757 Bitfield<10> lma; // Long mode active 758 Bitfield<11> nxe; // No-execute enable 759 Bitfield<12> svme; // Secure virtual machine enable 760 Bitfield<14> ffxsr; // Fast fxsave/fxrstor 761 EndBitUnion(Efer) 762 763 BitUnion64(Star) 764 Bitfield<31,0> targetEip; 765 Bitfield<47,32> syscallCsAndSs; 766 Bitfield<63,48> sysretCsAndSs; 767 EndBitUnion(Star) 768 769 BitUnion64(SfMask) 770 Bitfield<31,0> mask; 771 EndBitUnion(SfMask) 772 773 BitUnion64(PerfEvtSel) 774 Bitfield<7,0> eventMask; 775 Bitfield<15,8> unitMask; 776 Bitfield<16> usr; // User mode 777 Bitfield<17> os; // Operating-system mode 778 Bitfield<18> e; // Edge detect 779 Bitfield<19> pc; // Pin control 780 Bitfield<20> intEn; // Interrupt enable 781 Bitfield<22> en; // Counter enable 782 Bitfield<23> inv; // Invert mask 783 Bitfield<31,24> counterMask; 784 EndBitUnion(PerfEvtSel) 785 786 BitUnion32(Syscfg) 787 Bitfield<18> mfde; // MtrrFixDramEn 788 Bitfield<19> mfdm; // MtrrFixDramModEn 789 Bitfield<20> mvdm; // MtrrVarDramEn 790 Bitfield<21> tom2; // MtrrTom2En 791 EndBitUnion(Syscfg) 792 793 BitUnion64(IorrBase) 794 Bitfield<3> wr; // WrMem Enable 795 Bitfield<4> rd; // RdMem Enable 796 Bitfield<51,12> physbase; // Range physical base address 797 EndBitUnion(IorrBase) 798 799 BitUnion64(IorrMask) 800 Bitfield<11> v; // I/O register pair enable (valid) 801 Bitfield<51,12> physmask; // Range physical mask 802 EndBitUnion(IorrMask) 803 804 BitUnion64(Tom) 805 Bitfield<51,23> physAddr; // Top of memory physical address 806 EndBitUnion(Tom) 807 808 BitUnion64(VmCrMsr) 809 Bitfield<0> dpd; 810 Bitfield<1> rInit; 811 Bitfield<2> disA20M; 812 EndBitUnion(VmCrMsr) 813 814 BitUnion64(IgnneMsr) 815 Bitfield<0> ignne; 816 EndBitUnion(IgnneMsr) 817 818 BitUnion64(SmmCtlMsr) 819 Bitfield<0> dismiss; 820 Bitfield<1> enter; 821 Bitfield<2> smiCycle; 822 Bitfield<3> exit; 823 Bitfield<4> rsmCycle; 824 EndBitUnion(SmmCtlMsr) 825 826 /** 827 * Segment Selector 828 */ 829 BitUnion64(SegSelector) 830 // The following bitfield is not defined in the ISA, but it's useful 831 // when checking selectors in larger data types to make sure they 832 // aren't too large. 833 Bitfield<63, 3> esi; // Extended selector 834 Bitfield<15, 3> si; // Selector Index 835 Bitfield<2> ti; // Table Indicator 836 Bitfield<1, 0> rpl; // Requestor Privilege Level 837 EndBitUnion(SegSelector) 838 839 /** 840 * Segment Descriptors 841 */ 842 843 BitUnion64(SegDescriptor) 844 Bitfield<63, 56> baseHigh; 845 Bitfield<39, 16> baseLow; 846 Bitfield<55> g; // Granularity 847 Bitfield<54> d; // Default Operand Size 848 Bitfield<54> b; // Default Operand Size 849 Bitfield<53> l; // Long Attribute Bit 850 Bitfield<52> avl; // Available To Software 851 Bitfield<51, 48> limitHigh; 852 Bitfield<15, 0> limitLow; 853 Bitfield<47> p; // Present 854 Bitfield<46, 45> dpl; // Descriptor Privilege-Level 855 Bitfield<44> s; // System 856 SubBitUnion(type, 43, 40) 857 // Specifies whether this descriptor is for code or data. 858 Bitfield<43> codeOrData; 859 860 // These bit fields are for code segments 861 Bitfield<42> c; // Conforming 862 Bitfield<41> r; // Readable 863 864 // These bit fields are for data segments 865 Bitfield<42> e; // Expand-Down 866 Bitfield<41> w; // Writable 867 868 // This is used for both code and data segments. 869 Bitfield<40> a; // Accessed 870 EndSubBitUnion(type) 871 EndBitUnion(SegDescriptor) 872 873 BitUnion64(SegAttr) 874 Bitfield<1, 0> dpl; 875 Bitfield<2> unusable; 876 Bitfield<3> defaultSize; 877 Bitfield<4> longMode; 878 Bitfield<5> avl; 879 Bitfield<6> granularity; 880 Bitfield<7> present; 881 Bitfield<11, 8> type; 882 Bitfield<12> writable; 883 Bitfield<13> readable; 884 Bitfield<14> expandDown; 885 Bitfield<15> system; 886 EndBitUnion(SegAttr) 887 888 BitUnion64(GateDescriptor) 889 Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset 890 Bitfield<15, 0> offsetLow; // Target Code-Segment Offset 891 Bitfield<31, 16> selector; // Target Code-Segment Selector 892 Bitfield<47> p; // Present 893 Bitfield<46, 45> dpl; // Descriptor Privilege-Level 894 Bitfield<43, 40> type; 895 Bitfield<36, 32> count; // Parameter Count 896 EndBitUnion(GateDescriptor) 897 898 /** 899 * Descriptor-Table Registers 900 */ 901 BitUnion64(GDTR) 902 EndBitUnion(GDTR) 903 904 BitUnion64(IDTR) 905 EndBitUnion(IDTR) 906 907 BitUnion64(LDTR) 908 EndBitUnion(LDTR) 909 910 /** 911 * Task Register 912 */ 913 BitUnion64(TR) 914 EndBitUnion(TR) 915 916 917 /** 918 * Local APIC Base Register 919 */ 920 BitUnion64(LocalApicBase) 921 Bitfield<51, 12> base; 922 Bitfield<11> enable; 923 Bitfield<8> bsp; 924 EndBitUnion(LocalApicBase) 925}; 926 927#endif // __ARCH_X86_INTREGS_HH__ 928