misc.hh revision 6141
112067Snikos.nikoleris@arm.com/* 27586SAli.Saidi@arm.com * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 37586SAli.Saidi@arm.com * All rights reserved. 47586SAli.Saidi@arm.com * 57586SAli.Saidi@arm.com * Redistribution and use of this software in source and binary forms, 67586SAli.Saidi@arm.com * with or without modification, are permitted provided that the 77586SAli.Saidi@arm.com * following conditions are met: 87586SAli.Saidi@arm.com * 97586SAli.Saidi@arm.com * The software must be used only for Non-Commercial Use which means any 107586SAli.Saidi@arm.com * use which is NOT directed to receiving any direct monetary 117586SAli.Saidi@arm.com * compensation for, or commercial advantage from such use. Illustrative 127586SAli.Saidi@arm.com * examples of non-commercial use are academic research, personal study, 137905SBrad.Beckmann@amd.com * teaching, education and corporate research & development. 145323Sgblack@eecs.umich.edu * Illustrative examples of commercial use are distributing products for 152934Sktlim@umich.edu * commercial advantage and providing services using the software for 162934Sktlim@umich.edu * commercial advantage. 172934Sktlim@umich.edu * 182934Sktlim@umich.edu * If you wish to use this software or functionality therein that may be 192934Sktlim@umich.edu * covered by patents for commercial use, please contact: 202934Sktlim@umich.edu * Director of Intellectual Property Licensing 212934Sktlim@umich.edu * Office of Strategy and Technology 222934Sktlim@umich.edu * Hewlett-Packard Company 232934Sktlim@umich.edu * 1501 Page Mill Road 242934Sktlim@umich.edu * Palo Alto, California 94304 252934Sktlim@umich.edu * 262934Sktlim@umich.edu * Redistributions of source code must retain the above copyright notice, 272934Sktlim@umich.edu * this list of conditions and the following disclaimer. Redistributions 282934Sktlim@umich.edu * in binary form must reproduce the above copyright notice, this list of 292934Sktlim@umich.edu * conditions and the following disclaimer in the documentation and/or 302934Sktlim@umich.edu * other materials provided with the distribution. Neither the name of 312934Sktlim@umich.edu * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 322934Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 332934Sktlim@umich.edu * this software without specific prior written permission. No right of 342934Sktlim@umich.edu * sublicense is granted herewith. Derivatives of the software and 352934Sktlim@umich.edu * output created using the software may be prepared, but only for 362934Sktlim@umich.edu * Non-Commercial Uses. Derivatives of the software may be shared with 372934Sktlim@umich.edu * others provided: (i) the others agree to abide by the list of 382934Sktlim@umich.edu * conditions herein which includes the Non-Commercial Use restrictions; 392934Sktlim@umich.edu * and (ii) such Derivatives of the software include the above copyright 402934Sktlim@umich.edu * notice to acknowledge the contribution from this software where 412934Sktlim@umich.edu * applicable, this list of conditions and the disclaimer below. 422934Sktlim@umich.edu * 432995Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 4410046Snilay@cs.wisc.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 4511688Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 462934Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 4710747SChris.Emmons@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 4810747SChris.Emmons@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 4910747SChris.Emmons@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 5010747SChris.Emmons@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 5110747SChris.Emmons@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 5210747SChris.Emmons@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 5310747SChris.Emmons@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 5410747SChris.Emmons@arm.com * 5510747SChris.Emmons@arm.com * Authors: Gabe Black 5612026Sweipingliao@google.com */ 5712026Sweipingliao@google.com 5810747SChris.Emmons@arm.com#ifndef __ARCH_X86_MISCREGS_HH__ 5910747SChris.Emmons@arm.com#define __ARCH_X86_MISCREGS_HH__ 602934Sktlim@umich.edu 612934Sktlim@umich.edu#include "arch/x86/segmentregs.hh" 622934Sktlim@umich.edu#include "arch/x86/x86_traits.hh" 632934Sktlim@umich.edu#include "base/bitunion.hh" 642934Sktlim@umich.edu 652934Sktlim@umich.edu//These get defined in some system headers (at least termbits.h). That confuses 662934Sktlim@umich.edu//things here significantly. 6710720Sandreas.hansson@arm.com#undef CR0 686122SSteve.Reinhardt@amd.com#undef CR2 696122SSteve.Reinhardt@amd.com#undef CR3 706122SSteve.Reinhardt@amd.com 7110594Sgabeblack@google.comnamespace X86ISA 7210594Sgabeblack@google.com{ 7310697SCurtis.Dunham@arm.com enum CondFlagBit { 7410594Sgabeblack@google.com CFBit = 1 << 0, 7510594Sgabeblack@google.com PFBit = 1 << 2, 7610594Sgabeblack@google.com ECFBit = 1 << 3, 7710594Sgabeblack@google.com AFBit = 1 << 4, 7810594Sgabeblack@google.com EZFBit = 1 << 5, 7910118Snilay@cs.wisc.edu ZFBit = 1 << 6, 804520Ssaidi@eecs.umich.edu SFBit = 1 << 7, 814982Ssaidi@eecs.umich.edu DFBit = 1 << 10, 824520Ssaidi@eecs.umich.edu OFBit = 1 << 11 834520Ssaidi@eecs.umich.edu }; 842934Sktlim@umich.edu 852934Sktlim@umich.edu enum RFLAGBit { 863005Sstever@eecs.umich.edu TFBit = 1 << 8, 873005Sstever@eecs.umich.edu IFBit = 1 << 9, 883304Sstever@eecs.umich.edu NTBit = 1 << 14, 892995Ssaidi@eecs.umich.edu RFBit = 1 << 16, 9010118Snilay@cs.wisc.edu VMBit = 1 << 17, 9110118Snilay@cs.wisc.edu ACBit = 1 << 18, 9210118Snilay@cs.wisc.edu VIFBit = 1 << 19, 9310118Snilay@cs.wisc.edu VIPBit = 1 << 20, 9410720Sandreas.hansson@arm.com IDBit = 1 << 21 9510118Snilay@cs.wisc.edu }; 9610118Snilay@cs.wisc.edu 9710118Snilay@cs.wisc.edu enum MiscRegIndex 9810118Snilay@cs.wisc.edu { 9910118Snilay@cs.wisc.edu // Control registers 10010118Snilay@cs.wisc.edu // Most of these are invalid. 10110118Snilay@cs.wisc.edu MISCREG_CR_BASE, 10210118Snilay@cs.wisc.edu MISCREG_CR0 = MISCREG_CR_BASE, 10310118Snilay@cs.wisc.edu MISCREG_CR1, 10410118Snilay@cs.wisc.edu MISCREG_CR2, 10510118Snilay@cs.wisc.edu MISCREG_CR3, 10610118Snilay@cs.wisc.edu MISCREG_CR4, 10710118Snilay@cs.wisc.edu MISCREG_CR5, 10810118Snilay@cs.wisc.edu MISCREG_CR6, 10910118Snilay@cs.wisc.edu MISCREG_CR7, 11010118Snilay@cs.wisc.edu MISCREG_CR8, 11110118Snilay@cs.wisc.edu MISCREG_CR9, 1128713Sandreas.hansson@arm.com MISCREG_CR10, 11310118Snilay@cs.wisc.edu MISCREG_CR11, 11410118Snilay@cs.wisc.edu MISCREG_CR12, 11510118Snilay@cs.wisc.edu MISCREG_CR13, 11610118Snilay@cs.wisc.edu MISCREG_CR14, 11710118Snilay@cs.wisc.edu MISCREG_CR15, 11810118Snilay@cs.wisc.edu 11910118Snilay@cs.wisc.edu // Debug registers 12010118Snilay@cs.wisc.edu MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs, 1219826Sandreas.hansson@arm.com MISCREG_DR0 = MISCREG_DR_BASE, 1222934Sktlim@umich.edu MISCREG_DR1, 1232934Sktlim@umich.edu MISCREG_DR2, 1242995Ssaidi@eecs.umich.edu MISCREG_DR3, 1252934Sktlim@umich.edu MISCREG_DR4, 1266765SBrad.Beckmann@amd.com MISCREG_DR5, 1276765SBrad.Beckmann@amd.com MISCREG_DR6, 1286765SBrad.Beckmann@amd.com MISCREG_DR7, 1296765SBrad.Beckmann@amd.com 1306765SBrad.Beckmann@amd.com // Flags register 1316765SBrad.Beckmann@amd.com MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs, 1326765SBrad.Beckmann@amd.com 1336765SBrad.Beckmann@amd.com //Register to keep handy values like the CPU mode in. 13410594Sgabeblack@google.com MISCREG_M5_REG, 13510594Sgabeblack@google.com 13610594Sgabeblack@google.com /* 1376765SBrad.Beckmann@amd.com * Model Specific Registers 1386765SBrad.Beckmann@amd.com */ 1396765SBrad.Beckmann@amd.com // Time stamp counter 14011182Spalle@lyckegaard.dk MISCREG_TSC, 1418713Sandreas.hansson@arm.com 1428713Sandreas.hansson@arm.com MISCREG_MTRRCAP, 1438713Sandreas.hansson@arm.com 1448713Sandreas.hansson@arm.com MISCREG_SYSENTER_CS, 1454486Sbinkertn@umich.edu MISCREG_SYSENTER_ESP, 1464486Sbinkertn@umich.edu MISCREG_SYSENTER_EIP, 1474486Sbinkertn@umich.edu 1484486Sbinkertn@umich.edu MISCREG_MCG_CAP, 1494486Sbinkertn@umich.edu MISCREG_MCG_STATUS, 1504486Sbinkertn@umich.edu MISCREG_MCG_CTL, 1514486Sbinkertn@umich.edu 1523584Ssaidi@eecs.umich.edu MISCREG_DEBUG_CTL_MSR, 1533584Ssaidi@eecs.umich.edu 1543584Ssaidi@eecs.umich.edu MISCREG_LAST_BRANCH_FROM_IP, 1553584Ssaidi@eecs.umich.edu MISCREG_LAST_BRANCH_TO_IP, 1563584Ssaidi@eecs.umich.edu MISCREG_LAST_EXCEPTION_FROM_IP, 15710720Sandreas.hansson@arm.com MISCREG_LAST_EXCEPTION_TO_IP, 1589036Sandreas.hansson@arm.com 1599164Sandreas.hansson@arm.com MISCREG_MTRR_PHYS_BASE_BASE, 1603743Sgblack@eecs.umich.edu MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE, 1614104Ssaidi@eecs.umich.edu MISCREG_MTRR_PHYS_BASE_1, 1623743Sgblack@eecs.umich.edu MISCREG_MTRR_PHYS_BASE_2, 1639826Sandreas.hansson@arm.com MISCREG_MTRR_PHYS_BASE_3, 1649826Sandreas.hansson@arm.com MISCREG_MTRR_PHYS_BASE_4, 1658839Sandreas.hansson@arm.com MISCREG_MTRR_PHYS_BASE_5, 1668839Sandreas.hansson@arm.com MISCREG_MTRR_PHYS_BASE_6, 1678839Sandreas.hansson@arm.com MISCREG_MTRR_PHYS_BASE_7, 1688839Sandreas.hansson@arm.com 1698839Sandreas.hansson@arm.com MISCREG_MTRR_PHYS_MASK_BASE, 1708839Sandreas.hansson@arm.com MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE, 1713584Ssaidi@eecs.umich.edu MISCREG_MTRR_PHYS_MASK_1, 1723898Ssaidi@eecs.umich.edu MISCREG_MTRR_PHYS_MASK_2, 17311563Sjakub@jermar.eu MISCREG_MTRR_PHYS_MASK_3, 1748839Sandreas.hansson@arm.com MISCREG_MTRR_PHYS_MASK_4, 1758713Sandreas.hansson@arm.com MISCREG_MTRR_PHYS_MASK_5, 1768713Sandreas.hansson@arm.com MISCREG_MTRR_PHYS_MASK_6, 1778713Sandreas.hansson@arm.com MISCREG_MTRR_PHYS_MASK_7, 1788713Sandreas.hansson@arm.com 1798713Sandreas.hansson@arm.com MISCREG_MTRR_FIX_64K_00000, 1808713Sandreas.hansson@arm.com MISCREG_MTRR_FIX_16K_80000, 1818713Sandreas.hansson@arm.com MISCREG_MTRR_FIX_16K_A0000, 1828713Sandreas.hansson@arm.com MISCREG_MTRR_FIX_4K_C0000, 1838713Sandreas.hansson@arm.com MISCREG_MTRR_FIX_4K_C8000, 1848713Sandreas.hansson@arm.com MISCREG_MTRR_FIX_4K_D0000, 1858713Sandreas.hansson@arm.com MISCREG_MTRR_FIX_4K_D8000, 1868713Sandreas.hansson@arm.com MISCREG_MTRR_FIX_4K_E0000, 1878713Sandreas.hansson@arm.com MISCREG_MTRR_FIX_4K_E8000, 1888713Sandreas.hansson@arm.com MISCREG_MTRR_FIX_4K_F0000, 1898713Sandreas.hansson@arm.com MISCREG_MTRR_FIX_4K_F8000, 1908713Sandreas.hansson@arm.com 1918713Sandreas.hansson@arm.com MISCREG_PAT, 1928713Sandreas.hansson@arm.com 1938713Sandreas.hansson@arm.com MISCREG_DEF_TYPE, 1944103Ssaidi@eecs.umich.edu 1954103Ssaidi@eecs.umich.edu MISCREG_MC_CTL_BASE, 1964103Ssaidi@eecs.umich.edu MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE, 1973745Sgblack@eecs.umich.edu MISCREG_MC1_CTL, 1983745Sgblack@eecs.umich.edu MISCREG_MC2_CTL, 1993745Sgblack@eecs.umich.edu MISCREG_MC3_CTL, 2003584Ssaidi@eecs.umich.edu MISCREG_MC4_CTL, 2018839Sandreas.hansson@arm.com MISCREG_MC5_CTL, 2028706Sandreas.hansson@arm.com MISCREG_MC6_CTL, 2033584Ssaidi@eecs.umich.edu MISCREG_MC7_CTL, 2043584Ssaidi@eecs.umich.edu 20510588Sgabeblack@google.com MISCREG_MC_STATUS_BASE, 20610780SCurtis.Dunham@arm.com MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE, 20712475Sglenn.bergmans@arm.com MISCREG_MC1_STATUS, 20812475Sglenn.bergmans@arm.com MISCREG_MC2_STATUS, 2098061SAli.Saidi@ARM.com MISCREG_MC3_STATUS, 2108061SAli.Saidi@ARM.com MISCREG_MC4_STATUS, 21111238Sandreas.sandberg@arm.com MISCREG_MC5_STATUS, 21211238Sandreas.sandberg@arm.com MISCREG_MC6_STATUS, 21311238Sandreas.sandberg@arm.com MISCREG_MC7_STATUS, 21411238Sandreas.sandberg@arm.com 21511238Sandreas.sandberg@arm.com MISCREG_MC_ADDR_BASE, 21611238Sandreas.sandberg@arm.com MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE, 21711238Sandreas.sandberg@arm.com MISCREG_MC1_ADDR, 21811238Sandreas.sandberg@arm.com MISCREG_MC2_ADDR, 21911238Sandreas.sandberg@arm.com MISCREG_MC3_ADDR, 22011238Sandreas.sandberg@arm.com MISCREG_MC4_ADDR, 22111238Sandreas.sandberg@arm.com MISCREG_MC5_ADDR, 22211238Sandreas.sandberg@arm.com MISCREG_MC6_ADDR, 22311238Sandreas.sandberg@arm.com MISCREG_MC7_ADDR, 22411238Sandreas.sandberg@arm.com 22511297Sandreas.sandberg@arm.com MISCREG_MC_MISC_BASE, 22611297Sandreas.sandberg@arm.com MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE, 2277586SAli.Saidi@arm.com MISCREG_MC1_MISC, 2287586SAli.Saidi@arm.com MISCREG_MC2_MISC, 2297586SAli.Saidi@arm.com MISCREG_MC3_MISC, 2307586SAli.Saidi@arm.com MISCREG_MC4_MISC, 2317586SAli.Saidi@arm.com MISCREG_MC5_MISC, 2327586SAli.Saidi@arm.com MISCREG_MC6_MISC, 2337586SAli.Saidi@arm.com MISCREG_MC7_MISC, 2347586SAli.Saidi@arm.com 2357586SAli.Saidi@arm.com // Extended feature enable register 2367586SAli.Saidi@arm.com MISCREG_EFER, 23710720Sandreas.hansson@arm.com 23811598Sandreas.sandberg@arm.com MISCREG_STAR, 23911598Sandreas.sandberg@arm.com MISCREG_LSTAR, 24011598Sandreas.sandberg@arm.com MISCREG_CSTAR, 24111598Sandreas.sandberg@arm.com 24211598Sandreas.sandberg@arm.com MISCREG_SF_MASK, 24311598Sandreas.sandberg@arm.com 2447586SAli.Saidi@arm.com MISCREG_KERNEL_GS_BASE, 2457586SAli.Saidi@arm.com 2467586SAli.Saidi@arm.com MISCREG_TSC_AUX, 24711238Sandreas.sandberg@arm.com 24811238Sandreas.sandberg@arm.com MISCREG_PERF_EVT_SEL_BASE, 24911238Sandreas.sandberg@arm.com MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE, 25011238Sandreas.sandberg@arm.com MISCREG_PERF_EVT_SEL1, 25111238Sandreas.sandberg@arm.com MISCREG_PERF_EVT_SEL2, 25211238Sandreas.sandberg@arm.com MISCREG_PERF_EVT_SEL3, 25312475Sglenn.bergmans@arm.com 25411238Sandreas.sandberg@arm.com MISCREG_PERF_EVT_CTR_BASE, 25511238Sandreas.sandberg@arm.com MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE, 25611238Sandreas.sandberg@arm.com MISCREG_PERF_EVT_CTR1, 25711238Sandreas.sandberg@arm.com MISCREG_PERF_EVT_CTR2, 25811238Sandreas.sandberg@arm.com MISCREG_PERF_EVT_CTR3, 25911238Sandreas.sandberg@arm.com 26011238Sandreas.sandberg@arm.com MISCREG_SYSCFG, 26110512SAli.Saidi@ARM.com 26210512SAli.Saidi@ARM.com MISCREG_IORR_BASE_BASE, 26310512SAli.Saidi@ARM.com MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE, 2647586SAli.Saidi@arm.com MISCREG_IORR_BASE1, 26510353SGeoffrey.Blake@arm.com 26610353SGeoffrey.Blake@arm.com MISCREG_IORR_MASK_BASE, 26710353SGeoffrey.Blake@arm.com MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE, 26811297Sandreas.sandberg@arm.com MISCREG_IORR_MASK1, 26911297Sandreas.sandberg@arm.com 27011297Sandreas.sandberg@arm.com MISCREG_TOP_MEM, 27111297Sandreas.sandberg@arm.com MISCREG_TOP_MEM2, 27211297Sandreas.sandberg@arm.com 27311297Sandreas.sandberg@arm.com MISCREG_VM_CR, 27411297Sandreas.sandberg@arm.com MISCREG_IGNNE, 27510357SAli.Saidi@ARM.com MISCREG_SMM_CTL, 27611297Sandreas.sandberg@arm.com MISCREG_VM_HSAVE_PA, 2778528SAli.Saidi@ARM.com 27811297Sandreas.sandberg@arm.com /* 27911297Sandreas.sandberg@arm.com * Segment registers 28011297Sandreas.sandberg@arm.com */ 2818528SAli.Saidi@ARM.com // Segment selectors 28210507SAli.Saidi@ARM.com MISCREG_SEG_SEL_BASE, 28310507SAli.Saidi@ARM.com MISCREG_ES = MISCREG_SEG_SEL_BASE, 28410507SAli.Saidi@ARM.com MISCREG_CS, 28510507SAli.Saidi@ARM.com MISCREG_SS, 28610507SAli.Saidi@ARM.com MISCREG_DS, 28710507SAli.Saidi@ARM.com MISCREG_FS, 28810507SAli.Saidi@ARM.com MISCREG_GS, 28910507SAli.Saidi@ARM.com MISCREG_HS, 29010507SAli.Saidi@ARM.com MISCREG_TSL, 29110507SAli.Saidi@ARM.com MISCREG_TSG, 29210507SAli.Saidi@ARM.com MISCREG_LS, 29310507SAli.Saidi@ARM.com MISCREG_MS, 29410507SAli.Saidi@ARM.com MISCREG_TR, 29510507SAli.Saidi@ARM.com MISCREG_IDTR, 29610507SAli.Saidi@ARM.com 29710507SAli.Saidi@ARM.com // Hidden segment base field 29810507SAli.Saidi@ARM.com MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS, 29910507SAli.Saidi@ARM.com MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE, 30012079Sgedare@rtems.org MISCREG_CS_BASE, 30112079Sgedare@rtems.org MISCREG_SS_BASE, 3028061SAli.Saidi@ARM.com MISCREG_DS_BASE, 3038061SAli.Saidi@ARM.com MISCREG_FS_BASE, 3048061SAli.Saidi@ARM.com MISCREG_GS_BASE, 3058061SAli.Saidi@ARM.com MISCREG_HS_BASE, 30611238Sandreas.sandberg@arm.com MISCREG_TSL_BASE, 30711238Sandreas.sandberg@arm.com MISCREG_TSG_BASE, 30810161Satgutier@umich.edu MISCREG_LS_BASE, 30912475Sglenn.bergmans@arm.com MISCREG_MS_BASE, 3109929SAli.Saidi@ARM.com MISCREG_TR_BASE, 31111238Sandreas.sandberg@arm.com MISCREG_IDTR_BASE, 31211238Sandreas.sandberg@arm.com 31311238Sandreas.sandberg@arm.com // The effective segment base, ie what is actually added to an 31411238Sandreas.sandberg@arm.com // address. In 64 bit mode this can be different from the above, 31510071Satgutier@umich.edu // namely 0. 31610594Sgabeblack@google.com MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS, 31710594Sgabeblack@google.com MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE, 31810594Sgabeblack@google.com MISCREG_CS_EFF_BASE, 31910697SCurtis.Dunham@arm.com MISCREG_SS_EFF_BASE, 32010071Satgutier@umich.edu MISCREG_DS_EFF_BASE, 32110780SCurtis.Dunham@arm.com MISCREG_FS_EFF_BASE, 32210780SCurtis.Dunham@arm.com MISCREG_GS_EFF_BASE, 32310780SCurtis.Dunham@arm.com MISCREG_HS_EFF_BASE, 32410780SCurtis.Dunham@arm.com MISCREG_TSL_EFF_BASE, 32510780SCurtis.Dunham@arm.com MISCREG_TSG_EFF_BASE, 32611598Sandreas.sandberg@arm.com MISCREG_LS_EFF_BASE, 32710780SCurtis.Dunham@arm.com MISCREG_MS_EFF_BASE, 32810780SCurtis.Dunham@arm.com MISCREG_TR_EFF_BASE, 32910780SCurtis.Dunham@arm.com MISCREG_IDTR_EFF_BASE, 3308528SAli.Saidi@ARM.com 3318528SAli.Saidi@ARM.com // Hidden segment limit field 3328287SAli.Saidi@ARM.com MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS, 33310747SChris.Emmons@arm.com MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE, 33410747SChris.Emmons@arm.com MISCREG_CS_LIMIT, 33510747SChris.Emmons@arm.com MISCREG_SS_LIMIT, 33610747SChris.Emmons@arm.com MISCREG_DS_LIMIT, 33710747SChris.Emmons@arm.com MISCREG_FS_LIMIT, 33810747SChris.Emmons@arm.com MISCREG_GS_LIMIT, 33910735Srb639@drexel.edu MISCREG_HS_LIMIT, 34010747SChris.Emmons@arm.com MISCREG_TSL_LIMIT, 34110747SChris.Emmons@arm.com MISCREG_TSG_LIMIT, 34210747SChris.Emmons@arm.com MISCREG_LS_LIMIT, 34310747SChris.Emmons@arm.com MISCREG_MS_LIMIT, 34410747SChris.Emmons@arm.com MISCREG_TR_LIMIT, 34510747SChris.Emmons@arm.com MISCREG_IDTR_LIMIT, 34610747SChris.Emmons@arm.com 34710747SChris.Emmons@arm.com // Hidden segment limit attributes 34810747SChris.Emmons@arm.com MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS, 34910747SChris.Emmons@arm.com MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE, 35010747SChris.Emmons@arm.com MISCREG_CS_ATTR, 35110747SChris.Emmons@arm.com MISCREG_SS_ATTR, 35210747SChris.Emmons@arm.com MISCREG_DS_ATTR, 35310747SChris.Emmons@arm.com MISCREG_FS_ATTR, 35412026Sweipingliao@google.com MISCREG_GS_ATTR, 35512026Sweipingliao@google.com MISCREG_HS_ATTR, 35612026Sweipingliao@google.com MISCREG_TSL_ATTR, 35712026Sweipingliao@google.com MISCREG_TSG_ATTR, 35812026Sweipingliao@google.com MISCREG_LS_ATTR, 35912026Sweipingliao@google.com MISCREG_MS_ATTR, 36012026Sweipingliao@google.com MISCREG_TR_ATTR, 36112026Sweipingliao@google.com MISCREG_IDTR_ATTR, 36210747SChris.Emmons@arm.com 36310594Sgabeblack@google.com // Floating point control registers 36410747SChris.Emmons@arm.com MISCREG_X87_TOP = 36510780SCurtis.Dunham@arm.com MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS, 36610780SCurtis.Dunham@arm.com 36710780SCurtis.Dunham@arm.com //XXX Add "Model-Specific Registers" 36810780SCurtis.Dunham@arm.com 36910780SCurtis.Dunham@arm.com MISCREG_APIC_BASE, 37010780SCurtis.Dunham@arm.com 37110780SCurtis.Dunham@arm.com // "Fake" MSRs for internally implemented devices 37210780SCurtis.Dunham@arm.com MISCREG_PCI_CONFIG_ADDRESS, 37310780SCurtis.Dunham@arm.com 37410780SCurtis.Dunham@arm.com NUM_MISCREGS 37510780SCurtis.Dunham@arm.com }; 37610780SCurtis.Dunham@arm.com 37710780SCurtis.Dunham@arm.com static inline MiscRegIndex 37810780SCurtis.Dunham@arm.com MISCREG_CR(int index) 37910780SCurtis.Dunham@arm.com { 38010780SCurtis.Dunham@arm.com return (MiscRegIndex)(MISCREG_CR_BASE + index); 38111598Sandreas.sandberg@arm.com } 38211598Sandreas.sandberg@arm.com 38311598Sandreas.sandberg@arm.com static inline MiscRegIndex 38411598Sandreas.sandberg@arm.com MISCREG_DR(int index) 38511598Sandreas.sandberg@arm.com { 38611598Sandreas.sandberg@arm.com return (MiscRegIndex)(MISCREG_DR_BASE + index); 38711598Sandreas.sandberg@arm.com } 38811598Sandreas.sandberg@arm.com 38910780SCurtis.Dunham@arm.com static inline MiscRegIndex 39010780SCurtis.Dunham@arm.com MISCREG_MTRR_PHYS_BASE(int index) 39111598Sandreas.sandberg@arm.com { 39211598Sandreas.sandberg@arm.com return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index); 39311297Sandreas.sandberg@arm.com } 39411297Sandreas.sandberg@arm.com 39511297Sandreas.sandberg@arm.com static inline MiscRegIndex 39611598Sandreas.sandberg@arm.com MISCREG_MTRR_PHYS_MASK(int index) 39711598Sandreas.sandberg@arm.com { 39811598Sandreas.sandberg@arm.com return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index); 39911297Sandreas.sandberg@arm.com } 4007586SAli.Saidi@arm.com 4017586SAli.Saidi@arm.com static inline MiscRegIndex 4027949SAli.Saidi@ARM.com MISCREG_MC_CTL(int index) 4037586SAli.Saidi@arm.com { 40411598Sandreas.sandberg@arm.com return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index); 40511598Sandreas.sandberg@arm.com } 4068706Sandreas.hansson@arm.com 40711599Sandreas.sandberg@arm.com static inline MiscRegIndex 40812067Snikos.nikoleris@arm.com MISCREG_MC_STATUS(int index) 40912067Snikos.nikoleris@arm.com { 41012067Snikos.nikoleris@arm.com return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index); 41112067Snikos.nikoleris@arm.com } 41212067Snikos.nikoleris@arm.com 41312067Snikos.nikoleris@arm.com static inline MiscRegIndex 41411599Sandreas.sandberg@arm.com MISCREG_MC_ADDR(int index) 4157586SAli.Saidi@arm.com { 4167586SAli.Saidi@arm.com return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index); 4177586SAli.Saidi@arm.com } 41810594Sgabeblack@google.com 4195222Sksewell@umich.edu static inline MiscRegIndex 4205222Sksewell@umich.edu MISCREG_MC_MISC(int index) 4215222Sksewell@umich.edu { 4225222Sksewell@umich.edu return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index); 4235222Sksewell@umich.edu } 4245222Sksewell@umich.edu 4255222Sksewell@umich.edu static inline MiscRegIndex 4265222Sksewell@umich.edu MISCREG_PERF_EVT_SEL(int index) 4275222Sksewell@umich.edu { 4285222Sksewell@umich.edu return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index); 42910720Sandreas.hansson@arm.com } 4309036Sandreas.hansson@arm.com 4319164Sandreas.hansson@arm.com static inline MiscRegIndex 4329826Sandreas.hansson@arm.com MISCREG_PERF_EVT_CTR(int index) 4338839Sandreas.hansson@arm.com { 4348839Sandreas.hansson@arm.com return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index); 4355222Sksewell@umich.edu } 4365222Sksewell@umich.edu 4375222Sksewell@umich.edu static inline MiscRegIndex 4385222Sksewell@umich.edu MISCREG_IORR_BASE(int index) 4395222Sksewell@umich.edu { 4405222Sksewell@umich.edu return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index); 4418839Sandreas.hansson@arm.com } 4428839Sandreas.hansson@arm.com 4438839Sandreas.hansson@arm.com static inline MiscRegIndex 4448839Sandreas.hansson@arm.com MISCREG_IORR_MASK(int index) 4455222Sksewell@umich.edu { 4465222Sksewell@umich.edu return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index); 4475222Sksewell@umich.edu } 4485222Sksewell@umich.edu 4495478Snate@binkert.org static inline MiscRegIndex 4505222Sksewell@umich.edu MISCREG_SEG_SEL(int index) 4515222Sksewell@umich.edu { 45210594Sgabeblack@google.com return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index); 45310594Sgabeblack@google.com } 45410594Sgabeblack@google.com 4555222Sksewell@umich.edu static inline MiscRegIndex 4568839Sandreas.hansson@arm.com MISCREG_SEG_BASE(int index) 4578706Sandreas.hansson@arm.com { 4585222Sksewell@umich.edu return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index); 4595222Sksewell@umich.edu } 4605323Sgblack@eecs.umich.edu 4615357Sgblack@eecs.umich.edu static inline MiscRegIndex 4628323Ssteve.reinhardt@amd.com MISCREG_SEG_EFF_BASE(int index) 4635323Sgblack@eecs.umich.edu { 4648858Sgblack@eecs.umich.edu return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index); 4658713Sandreas.hansson@arm.com } 4668713Sandreas.hansson@arm.com 4678713Sandreas.hansson@arm.com static inline MiscRegIndex 4688713Sandreas.hansson@arm.com MISCREG_SEG_LIMIT(int index) 4698713Sandreas.hansson@arm.com { 4708713Sandreas.hansson@arm.com return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index); 4719036Sandreas.hansson@arm.com } 4727905SBrad.Beckmann@amd.com 4737905SBrad.Beckmann@amd.com static inline MiscRegIndex 47410720Sandreas.hansson@arm.com MISCREG_SEG_ATTR(int index) 4759164Sandreas.hansson@arm.com { 4768839Sandreas.hansson@arm.com return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index); 4778839Sandreas.hansson@arm.com } 47810438Smajiuyue@ncic.ac.cn 47910438Smajiuyue@ncic.ac.cn /** 48010438Smajiuyue@ncic.ac.cn * A type to describe the condition code bits of the RFLAGS register, 48110438Smajiuyue@ncic.ac.cn * plus two flags, EZF and ECF, which are only visible to microcode. 48210438Smajiuyue@ncic.ac.cn */ 48310438Smajiuyue@ncic.ac.cn BitUnion64(CCFlagBits) 4848713Sandreas.hansson@arm.com Bitfield<11> of; 4858713Sandreas.hansson@arm.com Bitfield<7> sf; 48610438Smajiuyue@ncic.ac.cn Bitfield<6> zf; 4878713Sandreas.hansson@arm.com Bitfield<5> ezf; 4888713Sandreas.hansson@arm.com Bitfield<4> af; 4898713Sandreas.hansson@arm.com Bitfield<3> ecf; 4908713Sandreas.hansson@arm.com Bitfield<2> pf; 4918713Sandreas.hansson@arm.com Bitfield<0> cf; 4928713Sandreas.hansson@arm.com EndBitUnion(CCFlagBits) 4938713Sandreas.hansson@arm.com 4948713Sandreas.hansson@arm.com /** 4959164Sandreas.hansson@arm.com * RFLAGS 4968839Sandreas.hansson@arm.com */ 4978839Sandreas.hansson@arm.com BitUnion64(RFLAGS) 4988815Sgblack@eecs.umich.edu Bitfield<21> id; // ID Flag 4998815Sgblack@eecs.umich.edu Bitfield<20> vip; // Virtual Interrupt Pending 5008858Sgblack@eecs.umich.edu Bitfield<19> vif; // Virtual Interrupt Flag 5018858Sgblack@eecs.umich.edu Bitfield<18> ac; // Alignment Check 5027905SBrad.Beckmann@amd.com Bitfield<17> vm; // Virtual-8086 Mode 5037905SBrad.Beckmann@amd.com Bitfield<16> rf; // Resume Flag 5047905SBrad.Beckmann@amd.com Bitfield<14> nt; // Nested Task 5057905SBrad.Beckmann@amd.com Bitfield<13, 12> iopl; // I/O Privilege Level 5068839Sandreas.hansson@arm.com Bitfield<11> of; // Overflow Flag 5078706Sandreas.hansson@arm.com Bitfield<10> df; // Direction Flag 5087905SBrad.Beckmann@amd.com Bitfield<9> intf; // Interrupt Flag 5097905SBrad.Beckmann@amd.com Bitfield<8> tf; // Trap Flag 51010720Sandreas.hansson@arm.com Bitfield<7> sf; // Sign Flag 5117905SBrad.Beckmann@amd.com Bitfield<6> zf; // Zero Flag 5128929Snilay@cs.wisc.edu Bitfield<4> af; // Auxiliary Flag 5138929Snilay@cs.wisc.edu Bitfield<2> pf; // Parity Flag 5148929Snilay@cs.wisc.edu Bitfield<0> cf; // Carry Flag 51510118Snilay@cs.wisc.edu EndBitUnion(RFLAGS) 5167905SBrad.Beckmann@amd.com 5177905SBrad.Beckmann@amd.com BitUnion64(HandyM5Reg) 51810588Sgabeblack@google.com Bitfield<0> mode; 5195613Sgblack@eecs.umich.edu Bitfield<3, 1> submode; 5205613Sgblack@eecs.umich.edu Bitfield<5, 4> cpl; 5215613Sgblack@eecs.umich.edu Bitfield<6> paging; 5225133Sgblack@eecs.umich.edu Bitfield<7> prot; 5235133Sgblack@eecs.umich.edu EndBitUnion(HandyM5Reg) 5245133Sgblack@eecs.umich.edu 5255133Sgblack@eecs.umich.edu /** 5265133Sgblack@eecs.umich.edu * Control registers 5276802Sgblack@eecs.umich.edu */ 5286802Sgblack@eecs.umich.edu BitUnion64(CR0) 5295133Sgblack@eecs.umich.edu Bitfield<31> pg; // Paging 53010041Snilay@cs.wisc.edu Bitfield<30> cd; // Cache Disable 53110041Snilay@cs.wisc.edu Bitfield<29> nw; // Not Writethrough 53210041Snilay@cs.wisc.edu Bitfield<18> am; // Alignment Mask 53310041Snilay@cs.wisc.edu Bitfield<16> wp; // Write Protect 53410041Snilay@cs.wisc.edu Bitfield<5> ne; // Numeric Error 53510041Snilay@cs.wisc.edu Bitfield<4> et; // Extension Type 53610041Snilay@cs.wisc.edu Bitfield<3> ts; // Task Switched 53710041Snilay@cs.wisc.edu Bitfield<2> em; // Emulation 53810046Snilay@cs.wisc.edu Bitfield<1> mp; // Monitor Coprocessor 53910046Snilay@cs.wisc.edu Bitfield<0> pe; // Protection Enabled 54010046Snilay@cs.wisc.edu EndBitUnion(CR0) 54110046Snilay@cs.wisc.edu 54210041Snilay@cs.wisc.edu // Page Fault Virtual Address 54310041Snilay@cs.wisc.edu BitUnion64(CR2) 5445613Sgblack@eecs.umich.edu Bitfield<31, 0> legacy; 5455613Sgblack@eecs.umich.edu EndBitUnion(CR2) 5465638Sgblack@eecs.umich.edu 5477905SBrad.Beckmann@amd.com BitUnion64(CR3) 5487905SBrad.Beckmann@amd.com Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table 5497905SBrad.Beckmann@amd.com // Base Address 5507905SBrad.Beckmann@amd.com Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table 5517905SBrad.Beckmann@amd.com // Base Address 5528858Sgblack@eecs.umich.edu Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table 5535613Sgblack@eecs.umich.edu // Base Address 5545613Sgblack@eecs.umich.edu Bitfield<4> pcd; // Page-Level Cache Disable 5555613Sgblack@eecs.umich.edu Bitfield<3> pwt; // Page-Level Writethrough 5565841Sgblack@eecs.umich.edu EndBitUnion(CR3) 5575841Sgblack@eecs.umich.edu 5585841Sgblack@eecs.umich.edu BitUnion64(CR4) 5595841Sgblack@eecs.umich.edu Bitfield<10> osxmmexcpt; // Operating System Unmasked 5605841Sgblack@eecs.umich.edu // Exception Support 5615841Sgblack@eecs.umich.edu Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support 5625841Sgblack@eecs.umich.edu Bitfield<8> pce; // Performance-Monitoring Counter Enable 5635615Sgblack@eecs.umich.edu Bitfield<7> pge; // Page-Global Enable 5645615Sgblack@eecs.umich.edu Bitfield<6> mce; // Machine Check Enable 5655615Sgblack@eecs.umich.edu Bitfield<5> pae; // Physical-Address Extension 5665615Sgblack@eecs.umich.edu Bitfield<4> pse; // Page Size Extensions 5675641Sgblack@eecs.umich.edu Bitfield<3> de; // Debugging Extensions 5688323Ssteve.reinhardt@amd.com Bitfield<2> tsd; // Time Stamp Disable 5698323Ssteve.reinhardt@amd.com Bitfield<1> pvi; // Protected-Mode Virtual Interrupts 5706135Sgblack@eecs.umich.edu Bitfield<0> vme; // Virtual-8086 Mode Extensions 5716135Sgblack@eecs.umich.edu EndBitUnion(CR4) 5726135Sgblack@eecs.umich.edu 5736135Sgblack@eecs.umich.edu BitUnion64(CR8) 5746135Sgblack@eecs.umich.edu Bitfield<3, 0> tpr; // Task Priority Register 5756135Sgblack@eecs.umich.edu EndBitUnion(CR8) 5768323Ssteve.reinhardt@amd.com 5775644Sgblack@eecs.umich.edu BitUnion64(DR6) 5786135Sgblack@eecs.umich.edu Bitfield<0> b0; 5795644Sgblack@eecs.umich.edu Bitfield<1> b1; 5805644Sgblack@eecs.umich.edu Bitfield<2> b2; 5815644Sgblack@eecs.umich.edu Bitfield<3> b3; 5826135Sgblack@eecs.umich.edu Bitfield<13> bd; 5838323Ssteve.reinhardt@amd.com Bitfield<14> bs; 58410437Smajiuyue@ncic.ac.cn Bitfield<15> bt; 58510437Smajiuyue@ncic.ac.cn EndBitUnion(DR6) 58610437Smajiuyue@ncic.ac.cn 58711481Sbaz21@cam.ac.uk BitUnion64(DR7) 58810437Smajiuyue@ncic.ac.cn Bitfield<0> l0; 58911481Sbaz21@cam.ac.uk Bitfield<1> g0; 5908323Ssteve.reinhardt@amd.com Bitfield<2> l1; 59110437Smajiuyue@ncic.ac.cn Bitfield<3> g1; 59210437Smajiuyue@ncic.ac.cn Bitfield<4> l2; 5938323Ssteve.reinhardt@amd.com Bitfield<5> g2; 5945843Sgblack@eecs.umich.edu Bitfield<6> l3; 5955843Sgblack@eecs.umich.edu Bitfield<7> g3; 5965843Sgblack@eecs.umich.edu Bitfield<8> le; 5975843Sgblack@eecs.umich.edu Bitfield<9> ge; 59810437Smajiuyue@ncic.ac.cn Bitfield<13> gd; 5995843Sgblack@eecs.umich.edu Bitfield<17, 16> rw0; 6006044Sgblack@eecs.umich.edu Bitfield<19, 18> len0; 6015843Sgblack@eecs.umich.edu Bitfield<21, 20> rw1; 6028323Ssteve.reinhardt@amd.com Bitfield<23, 22> len1; 6036135Sgblack@eecs.umich.edu Bitfield<25, 24> rw2; 6046135Sgblack@eecs.umich.edu Bitfield<27, 26> len2; 6056135Sgblack@eecs.umich.edu Bitfield<29, 28> rw3; 6066135Sgblack@eecs.umich.edu Bitfield<31, 30> len3; 6076135Sgblack@eecs.umich.edu EndBitUnion(DR7) 60810437Smajiuyue@ncic.ac.cn 6096135Sgblack@eecs.umich.edu // MTRR capabilities 6106135Sgblack@eecs.umich.edu BitUnion64(MTRRcap) 6116135Sgblack@eecs.umich.edu Bitfield<7, 0> vcnt; // Variable-Range Register Count 6128323Ssteve.reinhardt@amd.com Bitfield<8> fix; // Fixed-Range Registers 6136135Sgblack@eecs.umich.edu Bitfield<10> wc; // Write-Combining 6146135Sgblack@eecs.umich.edu EndBitUnion(MTRRcap) 6156135Sgblack@eecs.umich.edu 6166135Sgblack@eecs.umich.edu /** 61710437Smajiuyue@ncic.ac.cn * SYSENTER configuration registers 6186135Sgblack@eecs.umich.edu */ 6196135Sgblack@eecs.umich.edu BitUnion64(SysenterCS) 6206135Sgblack@eecs.umich.edu Bitfield<15, 0> targetCS; 6218323Ssteve.reinhardt@amd.com EndBitUnion(SysenterCS) 6226135Sgblack@eecs.umich.edu 6236135Sgblack@eecs.umich.edu BitUnion64(SysenterESP) 6246135Sgblack@eecs.umich.edu Bitfield<31, 0> targetESP; 6256135Sgblack@eecs.umich.edu EndBitUnion(SysenterESP) 6268323Ssteve.reinhardt@amd.com 6278323Ssteve.reinhardt@amd.com BitUnion64(SysenterEIP) 6285641Sgblack@eecs.umich.edu Bitfield<31, 0> targetEIP; 62910594Sgabeblack@google.com EndBitUnion(SysenterEIP) 63010594Sgabeblack@google.com 6315613Sgblack@eecs.umich.edu /** 6325613Sgblack@eecs.umich.edu * Global machine check registers 6337905SBrad.Beckmann@amd.com */ 6349826Sandreas.hansson@arm.com BitUnion64(McgCap) 6355613Sgblack@eecs.umich.edu Bitfield<7, 0> count; // Number of error reporting register banks 6365450Sgblack@eecs.umich.edu Bitfield<8> MCGCP; // MCG_CTL register present. 6375450Sgblack@eecs.umich.edu EndBitUnion(McgCap) 6389826Sandreas.hansson@arm.com 6399232Sandreas.hansson@arm.com BitUnion64(McgStatus) 64010041Snilay@cs.wisc.edu Bitfield<0> ripv; // Restart-IP valid 6415450Sgblack@eecs.umich.edu Bitfield<1> eipv; // Error-IP valid 64210041Snilay@cs.wisc.edu Bitfield<2> mcip; // Machine check in-progress 6438323Ssteve.reinhardt@amd.com EndBitUnion(McgStatus) 6448323Ssteve.reinhardt@amd.com 6459622Snilay@cs.wisc.edu BitUnion64(DebugCtlMsr) 6469622Snilay@cs.wisc.edu Bitfield<0> lbr; // Last-branch record 64710041Snilay@cs.wisc.edu Bitfield<1> btf; // Branch single step 6488323Ssteve.reinhardt@amd.com Bitfield<2> pb0; // Performance monitoring pin control 0 64910041Snilay@cs.wisc.edu Bitfield<3> pb1; // Performance monitoring pin control 1 6509898Sandreas@sandberg.pp.se Bitfield<4> pb2; // Performance monitoring pin control 2 6518323Ssteve.reinhardt@amd.com Bitfield<5> pb3; // Performance monitoring pin control 3 6525450Sgblack@eecs.umich.edu /*uint64_t pb(int index) 65310438Smajiuyue@ncic.ac.cn { 65410438Smajiuyue@ncic.ac.cn return bits(__data, index + 2); 65510438Smajiuyue@ncic.ac.cn }*/ 65610438Smajiuyue@ncic.ac.cn EndBitUnion(DebugCtlMsr) 65710438Smajiuyue@ncic.ac.cn 65810438Smajiuyue@ncic.ac.cn BitUnion64(MtrrPhysBase) 65910438Smajiuyue@ncic.ac.cn Bitfield<7, 0> type; // Default memory type 66010438Smajiuyue@ncic.ac.cn Bitfield<51, 12> physbase; // Range physical base address 66110438Smajiuyue@ncic.ac.cn EndBitUnion(MtrrPhysBase) 66210438Smajiuyue@ncic.ac.cn 66310438Smajiuyue@ncic.ac.cn BitUnion64(MtrrPhysMask) 66410041Snilay@cs.wisc.edu Bitfield<11> valid; // MTRR pair enable 66510041Snilay@cs.wisc.edu Bitfield<51, 12> physmask; // Range physical mask 66610041Snilay@cs.wisc.edu EndBitUnion(MtrrPhysMask) 66710041Snilay@cs.wisc.edu 66810041Snilay@cs.wisc.edu BitUnion64(MtrrFixed) 66910041Snilay@cs.wisc.edu /*uint64_t type(int index) 67010041Snilay@cs.wisc.edu { 67110041Snilay@cs.wisc.edu return bits(__data, index * 8 + 7, index * 8); 67210041Snilay@cs.wisc.edu }*/ 67310041Snilay@cs.wisc.edu EndBitUnion(MtrrFixed) 6745330Sgblack@eecs.umich.edu 67510594Sgabeblack@google.com BitUnion64(Pat) 67610594Sgabeblack@google.com /*uint64_t pa(int index) 67710594Sgabeblack@google.com { 67810003Ssteve.reinhardt@amd.com return bits(__data, index * 8 + 2, index * 8); 6795133Sgblack@eecs.umich.edu }*/ 6805133Sgblack@eecs.umich.edu EndBitUnion(Pat) 6813584Ssaidi@eecs.umich.edu 6828801Sgblack@eecs.umich.edu BitUnion64(MtrrDefType) 6838801Sgblack@eecs.umich.edu Bitfield<7, 0> type; // Default type 6842995Ssaidi@eecs.umich.edu Bitfield<10> fe; // Fixed range enable 6852995Ssaidi@eecs.umich.edu Bitfield<11> e; // MTRR enable 6864981Ssaidi@eecs.umich.edu EndBitUnion(MtrrDefType) 6874981Ssaidi@eecs.umich.edu 6888661SAli.Saidi@ARM.com /** 6898661SAli.Saidi@ARM.com * Machine check 6908661SAli.Saidi@ARM.com */ 6918661SAli.Saidi@ARM.com BitUnion64(McStatus) 6928661SAli.Saidi@ARM.com Bitfield<15,0> mcaErrorCode; 6938661SAli.Saidi@ARM.com Bitfield<31,16> modelSpecificCode; 6948661SAli.Saidi@ARM.com Bitfield<56,32> otherInfo; 6958661SAli.Saidi@ARM.com Bitfield<57> pcc; // Processor-context corrupt 6968661SAli.Saidi@ARM.com Bitfield<58> addrv; // Error-address register valid 6973025Ssaidi@eecs.umich.edu Bitfield<59> miscv; // Miscellaneous-error register valid 6983025Ssaidi@eecs.umich.edu Bitfield<60> en; // Error condition enabled 6993025Ssaidi@eecs.umich.edu Bitfield<61> uc; // Uncorrected error 7002934Sktlim@umich.edu Bitfield<62> over; // Status register overflow 7012934Sktlim@umich.edu Bitfield<63> val; // Valid 70211291Sgabor.dozsa@arm.com EndBitUnion(McStatus) 70311291Sgabor.dozsa@arm.com 70411291Sgabor.dozsa@arm.com BitUnion64(McCtl) 70511291Sgabor.dozsa@arm.com /*uint64_t en(int index) 70611291Sgabor.dozsa@arm.com { 70711291Sgabor.dozsa@arm.com return bits(__data, index); 70811291Sgabor.dozsa@arm.com }*/ 70911291Sgabor.dozsa@arm.com EndBitUnion(McCtl) 71011291Sgabor.dozsa@arm.com 71111291Sgabor.dozsa@arm.com // Extended feature enable register 71211291Sgabor.dozsa@arm.com BitUnion64(Efer) 71311291Sgabor.dozsa@arm.com Bitfield<0> sce; // System call extensions 71411291Sgabor.dozsa@arm.com Bitfield<8> lme; // Long mode enable 71511291Sgabor.dozsa@arm.com Bitfield<10> lma; // Long mode active 71611291Sgabor.dozsa@arm.com Bitfield<11> nxe; // No-execute enable 71711291Sgabor.dozsa@arm.com Bitfield<12> svme; // Secure virtual machine enable 71811291Sgabor.dozsa@arm.com Bitfield<14> ffxsr; // Fast fxsave/fxrstor 71911291Sgabor.dozsa@arm.com EndBitUnion(Efer) 72011291Sgabor.dozsa@arm.com 72111291Sgabor.dozsa@arm.com BitUnion64(Star) 72211291Sgabor.dozsa@arm.com Bitfield<31,0> targetEip; 72311291Sgabor.dozsa@arm.com Bitfield<47,32> syscallCsAndSs; 72411291Sgabor.dozsa@arm.com Bitfield<63,48> sysretCsAndSs; 72511291Sgabor.dozsa@arm.com EndBitUnion(Star) 72611291Sgabor.dozsa@arm.com 72711291Sgabor.dozsa@arm.com BitUnion64(SfMask) 72811291Sgabor.dozsa@arm.com Bitfield<31,0> mask; 72911291Sgabor.dozsa@arm.com EndBitUnion(SfMask) 73011291Sgabor.dozsa@arm.com 73111291Sgabor.dozsa@arm.com BitUnion64(PerfEvtSel) 73211291Sgabor.dozsa@arm.com Bitfield<7,0> eventMask; 73311291Sgabor.dozsa@arm.com Bitfield<15,8> unitMask; 73411291Sgabor.dozsa@arm.com Bitfield<16> usr; // User mode 73511291Sgabor.dozsa@arm.com Bitfield<17> os; // Operating-system mode 73611291Sgabor.dozsa@arm.com Bitfield<18> e; // Edge detect 73711291Sgabor.dozsa@arm.com Bitfield<19> pc; // Pin control 738 Bitfield<20> intEn; // Interrupt enable 739 Bitfield<22> en; // Counter enable 740 Bitfield<23> inv; // Invert mask 741 Bitfield<31,24> counterMask; 742 EndBitUnion(PerfEvtSel) 743 744 BitUnion32(Syscfg) 745 Bitfield<18> mfde; // MtrrFixDramEn 746 Bitfield<19> mfdm; // MtrrFixDramModEn 747 Bitfield<20> mvdm; // MtrrVarDramEn 748 Bitfield<21> tom2; // MtrrTom2En 749 EndBitUnion(Syscfg) 750 751 BitUnion64(IorrBase) 752 Bitfield<3> wr; // WrMem Enable 753 Bitfield<4> rd; // RdMem Enable 754 Bitfield<51,12> physbase; // Range physical base address 755 EndBitUnion(IorrBase) 756 757 BitUnion64(IorrMask) 758 Bitfield<11> v; // I/O register pair enable (valid) 759 Bitfield<51,12> physmask; // Range physical mask 760 EndBitUnion(IorrMask) 761 762 BitUnion64(Tom) 763 Bitfield<51,23> physAddr; // Top of memory physical address 764 EndBitUnion(Tom) 765 766 BitUnion64(VmCrMsr) 767 Bitfield<0> dpd; 768 Bitfield<1> rInit; 769 Bitfield<2> disA20M; 770 EndBitUnion(VmCrMsr) 771 772 BitUnion64(IgnneMsr) 773 Bitfield<0> ignne; 774 EndBitUnion(IgnneMsr) 775 776 BitUnion64(SmmCtlMsr) 777 Bitfield<0> dismiss; 778 Bitfield<1> enter; 779 Bitfield<2> smiCycle; 780 Bitfield<3> exit; 781 Bitfield<4> rsmCycle; 782 EndBitUnion(SmmCtlMsr) 783 784 /** 785 * Segment Selector 786 */ 787 BitUnion64(SegSelector) 788 // The following bitfield is not defined in the ISA, but it's useful 789 // when checking selectors in larger data types to make sure they 790 // aren't too large. 791 Bitfield<63, 3> esi; // Extended selector 792 Bitfield<15, 3> si; // Selector Index 793 Bitfield<2> ti; // Table Indicator 794 Bitfield<1, 0> rpl; // Requestor Privilege Level 795 EndBitUnion(SegSelector) 796 797 /** 798 * Segment Descriptors 799 */ 800 801 BitUnion64(SegDescriptor) 802 Bitfield<63, 56> baseHigh; 803 Bitfield<39, 16> baseLow; 804 Bitfield<55> g; // Granularity 805 Bitfield<54> d; // Default Operand Size 806 Bitfield<54> b; // Default Operand Size 807 Bitfield<53> l; // Long Attribute Bit 808 Bitfield<52> avl; // Available To Software 809 Bitfield<51, 48> limitHigh; 810 Bitfield<15, 0> limitLow; 811 Bitfield<47> p; // Present 812 Bitfield<46, 45> dpl; // Descriptor Privilege-Level 813 Bitfield<44> s; // System 814 SubBitUnion(type, 43, 40) 815 // Specifies whether this descriptor is for code or data. 816 Bitfield<43> codeOrData; 817 818 // These bit fields are for code segments 819 Bitfield<42> c; // Conforming 820 Bitfield<41> r; // Readable 821 822 // These bit fields are for data segments 823 Bitfield<42> e; // Expand-Down 824 Bitfield<41> w; // Writable 825 826 // This is used for both code and data segments. 827 Bitfield<40> a; // Accessed 828 EndSubBitUnion(type) 829 EndBitUnion(SegDescriptor) 830 831 BitUnion64(SegAttr) 832 Bitfield<0> writable; 833 Bitfield<1> readable; 834 Bitfield<2> expandDown; 835 Bitfield<4, 3> dpl; 836 Bitfield<5> defaultSize; 837 Bitfield<6> longMode; 838 EndBitUnion(SegAttr) 839 840 BitUnion64(GateDescriptor) 841 Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset 842 Bitfield<15, 0> offsetLow; // Target Code-Segment Offset 843 Bitfield<31, 16> selector; // Target Code-Segment Selector 844 Bitfield<47> p; // Present 845 Bitfield<46, 45> dpl; // Descriptor Privilege-Level 846 Bitfield<43, 40> type; 847 Bitfield<36, 32> count; // Parameter Count 848 EndBitUnion(GateDescriptor) 849 850 /** 851 * Descriptor-Table Registers 852 */ 853 BitUnion64(GDTR) 854 EndBitUnion(GDTR) 855 856 BitUnion64(IDTR) 857 EndBitUnion(IDTR) 858 859 BitUnion64(LDTR) 860 EndBitUnion(LDTR) 861 862 /** 863 * Task Register 864 */ 865 BitUnion64(TR) 866 EndBitUnion(TR) 867 868 869 /** 870 * Local APIC Base Register 871 */ 872 BitUnion64(LocalApicBase) 873 Bitfield<51, 12> base; 874 Bitfield<11> enable; 875 Bitfield<8> bsp; 876 EndBitUnion(LocalApicBase) 877}; 878 879#endif // __ARCH_X86_INTREGS_HH__ 880