misc.hh revision 5429
17151Sgblack@eecs.umich.edu/* 27151Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 37151Sgblack@eecs.umich.edu * All rights reserved. 47151Sgblack@eecs.umich.edu * 57151Sgblack@eecs.umich.edu * Redistribution and use of this software in source and binary forms, 67151Sgblack@eecs.umich.edu * with or without modification, are permitted provided that the 77151Sgblack@eecs.umich.edu * following conditions are met: 87151Sgblack@eecs.umich.edu * 97151Sgblack@eecs.umich.edu * The software must be used only for Non-Commercial Use which means any 107151Sgblack@eecs.umich.edu * use which is NOT directed to receiving any direct monetary 117151Sgblack@eecs.umich.edu * compensation for, or commercial advantage from such use. Illustrative 127151Sgblack@eecs.umich.edu * examples of non-commercial use are academic research, personal study, 137151Sgblack@eecs.umich.edu * teaching, education and corporate research & development. 147151Sgblack@eecs.umich.edu * Illustrative examples of commercial use are distributing products for 157151Sgblack@eecs.umich.edu * commercial advantage and providing services using the software for 167151Sgblack@eecs.umich.edu * commercial advantage. 177151Sgblack@eecs.umich.edu * 187151Sgblack@eecs.umich.edu * If you wish to use this software or functionality therein that may be 197151Sgblack@eecs.umich.edu * covered by patents for commercial use, please contact: 207151Sgblack@eecs.umich.edu * Director of Intellectual Property Licensing 217151Sgblack@eecs.umich.edu * Office of Strategy and Technology 227151Sgblack@eecs.umich.edu * Hewlett-Packard Company 237151Sgblack@eecs.umich.edu * 1501 Page Mill Road 247151Sgblack@eecs.umich.edu * Palo Alto, California 94304 257151Sgblack@eecs.umich.edu * 267151Sgblack@eecs.umich.edu * Redistributions of source code must retain the above copyright notice, 277151Sgblack@eecs.umich.edu * this list of conditions and the following disclaimer. Redistributions 287151Sgblack@eecs.umich.edu * in binary form must reproduce the above copyright notice, this list of 297151Sgblack@eecs.umich.edu * conditions and the following disclaimer in the documentation and/or 307151Sgblack@eecs.umich.edu * other materials provided with the distribution. Neither the name of 317151Sgblack@eecs.umich.edu * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 327151Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 337151Sgblack@eecs.umich.edu * this software without specific prior written permission. No right of 347151Sgblack@eecs.umich.edu * sublicense is granted herewith. Derivatives of the software and 357151Sgblack@eecs.umich.edu * output created using the software may be prepared, but only for 367151Sgblack@eecs.umich.edu * Non-Commercial Uses. Derivatives of the software may be shared with 377151Sgblack@eecs.umich.edu * others provided: (i) the others agree to abide by the list of 387151Sgblack@eecs.umich.edu * conditions herein which includes the Non-Commercial Use restrictions; 397151Sgblack@eecs.umich.edu * and (ii) such Derivatives of the software include the above copyright 407151Sgblack@eecs.umich.edu * notice to acknowledge the contribution from this software where 417151Sgblack@eecs.umich.edu * applicable, this list of conditions and the disclaimer below. 427151Sgblack@eecs.umich.edu * 437151Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 447151Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 457151Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 467151Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 477151Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 487151Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 497720Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 507720Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 517720Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 527720Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 537151Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 547151Sgblack@eecs.umich.edu * 557151Sgblack@eecs.umich.edu * Authors: Gabe Black 567720Sgblack@eecs.umich.edu */ 577720Sgblack@eecs.umich.edu 587720Sgblack@eecs.umich.edu#ifndef __ARCH_X86_MISCREGS_HH__ 597594SGene.Wu@arm.com#define __ARCH_X86_MISCREGS_HH__ 607151Sgblack@eecs.umich.edu 617151Sgblack@eecs.umich.edu#include "arch/x86/segmentregs.hh" 627151Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh" 637151Sgblack@eecs.umich.edu#include "base/bitunion.hh" 647151Sgblack@eecs.umich.edu 657151Sgblack@eecs.umich.edu//These get defined in some system headers (at least termbits.h). That confuses 667151Sgblack@eecs.umich.edu//things here significantly. 677151Sgblack@eecs.umich.edu#undef CR0 687151Sgblack@eecs.umich.edu#undef CR2 697151Sgblack@eecs.umich.edu#undef CR3 707151Sgblack@eecs.umich.edu 717720Sgblack@eecs.umich.edunamespace X86ISA 727720Sgblack@eecs.umich.edu{ 737151Sgblack@eecs.umich.edu enum CondFlagBit { 747151Sgblack@eecs.umich.edu CFBit = 1 << 0, 757151Sgblack@eecs.umich.edu PFBit = 1 << 2, 767720Sgblack@eecs.umich.edu ECFBit = 1 << 3, 777151Sgblack@eecs.umich.edu AFBit = 1 << 4, 787151Sgblack@eecs.umich.edu EZFBit = 1 << 5, 797151Sgblack@eecs.umich.edu ZFBit = 1 << 6, 807151Sgblack@eecs.umich.edu SFBit = 1 << 7, 817151Sgblack@eecs.umich.edu DFBit = 1 << 10, 827151Sgblack@eecs.umich.edu OFBit = 1 << 11 837151Sgblack@eecs.umich.edu }; 847151Sgblack@eecs.umich.edu 857151Sgblack@eecs.umich.edu enum RFLAGBit { 867151Sgblack@eecs.umich.edu TFBit = 1 << 8, 877151Sgblack@eecs.umich.edu IFBit = 1 << 9, 887720Sgblack@eecs.umich.edu NTBit = 1 << 14, 897720Sgblack@eecs.umich.edu RFBit = 1 << 16, 907602SGene.Wu@arm.com VMBit = 1 << 17, 917602SGene.Wu@arm.com ACBit = 1 << 18, 927602SGene.Wu@arm.com VIFBit = 1 << 19, 937151Sgblack@eecs.umich.edu VIPBit = 1 << 20, 947151Sgblack@eecs.umich.edu IDBit = 1 << 21 957282Sgblack@eecs.umich.edu }; 967151Sgblack@eecs.umich.edu 977151Sgblack@eecs.umich.edu enum MiscRegIndex 987151Sgblack@eecs.umich.edu { 997151Sgblack@eecs.umich.edu // Control registers 1007151Sgblack@eecs.umich.edu // Most of these are invalid. 1017151Sgblack@eecs.umich.edu MISCREG_CR_BASE, 1027151Sgblack@eecs.umich.edu MISCREG_CR0 = MISCREG_CR_BASE, 1037151Sgblack@eecs.umich.edu MISCREG_CR1, 1047720Sgblack@eecs.umich.edu MISCREG_CR2, 1057720Sgblack@eecs.umich.edu MISCREG_CR3, 1067720Sgblack@eecs.umich.edu MISCREG_CR4, 1077594SGene.Wu@arm.com MISCREG_CR5, 1087151Sgblack@eecs.umich.edu MISCREG_CR6, 1097151Sgblack@eecs.umich.edu MISCREG_CR7, 1107151Sgblack@eecs.umich.edu MISCREG_CR8, 1117720Sgblack@eecs.umich.edu MISCREG_CR9, 1127720Sgblack@eecs.umich.edu MISCREG_CR10, 1137720Sgblack@eecs.umich.edu MISCREG_CR11, 1147594SGene.Wu@arm.com MISCREG_CR12, 1157151Sgblack@eecs.umich.edu MISCREG_CR13, 1167151Sgblack@eecs.umich.edu MISCREG_CR14, 1177151Sgblack@eecs.umich.edu MISCREG_CR15, 1187282Sgblack@eecs.umich.edu 1197282Sgblack@eecs.umich.edu // Debug registers 1207282Sgblack@eecs.umich.edu MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs, 1217720Sgblack@eecs.umich.edu MISCREG_DR0 = MISCREG_DR_BASE, 1227720Sgblack@eecs.umich.edu MISCREG_DR1, 1237282Sgblack@eecs.umich.edu MISCREG_DR2, 1247282Sgblack@eecs.umich.edu MISCREG_DR3, 1257720Sgblack@eecs.umich.edu MISCREG_DR4, 1267282Sgblack@eecs.umich.edu MISCREG_DR5, 1277282Sgblack@eecs.umich.edu MISCREG_DR6, 1287151Sgblack@eecs.umich.edu MISCREG_DR7, 1297151Sgblack@eecs.umich.edu 1307151Sgblack@eecs.umich.edu // Flags register 1317151Sgblack@eecs.umich.edu MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs, 1327151Sgblack@eecs.umich.edu 1337151Sgblack@eecs.umich.edu //Register to keep handy values like the CPU mode in. 1347151Sgblack@eecs.umich.edu MISCREG_M5_REG, 1357151Sgblack@eecs.umich.edu 1367151Sgblack@eecs.umich.edu /* 1377151Sgblack@eecs.umich.edu * Model Specific Registers 1387151Sgblack@eecs.umich.edu */ 1397151Sgblack@eecs.umich.edu // Time stamp counter 1407151Sgblack@eecs.umich.edu MISCREG_TSC, 1417151Sgblack@eecs.umich.edu 1427151Sgblack@eecs.umich.edu MISCREG_MTRRCAP, 1437720Sgblack@eecs.umich.edu 1447720Sgblack@eecs.umich.edu MISCREG_SYSENTER_CS, 1457720Sgblack@eecs.umich.edu MISCREG_SYSENTER_ESP, 1467720Sgblack@eecs.umich.edu MISCREG_SYSENTER_EIP, 1477151Sgblack@eecs.umich.edu 1487151Sgblack@eecs.umich.edu MISCREG_MCG_CAP, 1497151Sgblack@eecs.umich.edu MISCREG_MCG_STATUS, 1507151Sgblack@eecs.umich.edu MISCREG_MCG_CTL, 1517151Sgblack@eecs.umich.edu 1527151Sgblack@eecs.umich.edu MISCREG_DEBUG_CTL_MSR, 1537151Sgblack@eecs.umich.edu 1547151Sgblack@eecs.umich.edu MISCREG_LAST_BRANCH_FROM_IP, 1557151Sgblack@eecs.umich.edu MISCREG_LAST_BRANCH_TO_IP, 1567151Sgblack@eecs.umich.edu MISCREG_LAST_EXCEPTION_FROM_IP, 1577151Sgblack@eecs.umich.edu MISCREG_LAST_EXCEPTION_TO_IP, 1587294Sgblack@eecs.umich.edu 1597294Sgblack@eecs.umich.edu MISCREG_MTRR_PHYS_BASE_BASE, 1607294Sgblack@eecs.umich.edu MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE, 1617294Sgblack@eecs.umich.edu MISCREG_MTRR_PHYS_BASE_1, 1627294Sgblack@eecs.umich.edu MISCREG_MTRR_PHYS_BASE_2, 1637294Sgblack@eecs.umich.edu MISCREG_MTRR_PHYS_BASE_3, 1647720Sgblack@eecs.umich.edu MISCREG_MTRR_PHYS_BASE_4, 1657720Sgblack@eecs.umich.edu MISCREG_MTRR_PHYS_BASE_5, 1667720Sgblack@eecs.umich.edu MISCREG_MTRR_PHYS_BASE_6, 1677720Sgblack@eecs.umich.edu MISCREG_MTRR_PHYS_BASE_7, 1687720Sgblack@eecs.umich.edu 1697151Sgblack@eecs.umich.edu MISCREG_MTRR_PHYS_MASK_BASE, 1707151Sgblack@eecs.umich.edu MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE, 1717294Sgblack@eecs.umich.edu MISCREG_MTRR_PHYS_MASK_1, 1727294Sgblack@eecs.umich.edu MISCREG_MTRR_PHYS_MASK_2, 1737294Sgblack@eecs.umich.edu MISCREG_MTRR_PHYS_MASK_3, 1747294Sgblack@eecs.umich.edu MISCREG_MTRR_PHYS_MASK_4, 1757294Sgblack@eecs.umich.edu MISCREG_MTRR_PHYS_MASK_5, 1767294Sgblack@eecs.umich.edu MISCREG_MTRR_PHYS_MASK_6, 1777720Sgblack@eecs.umich.edu MISCREG_MTRR_PHYS_MASK_7, 1787720Sgblack@eecs.umich.edu 1797720Sgblack@eecs.umich.edu MISCREG_MTRR_FIX_64K_00000, 1807720Sgblack@eecs.umich.edu MISCREG_MTRR_FIX_16K_80000, 1817720Sgblack@eecs.umich.edu MISCREG_MTRR_FIX_16K_A0000, 1827151Sgblack@eecs.umich.edu MISCREG_MTRR_FIX_4K_C0000, 1837151Sgblack@eecs.umich.edu MISCREG_MTRR_FIX_4K_C8000, 1847151Sgblack@eecs.umich.edu MISCREG_MTRR_FIX_4K_D0000, 1857151Sgblack@eecs.umich.edu MISCREG_MTRR_FIX_4K_D8000, 1867151Sgblack@eecs.umich.edu MISCREG_MTRR_FIX_4K_E0000, 1877151Sgblack@eecs.umich.edu MISCREG_MTRR_FIX_4K_E8000, 1887151Sgblack@eecs.umich.edu MISCREG_MTRR_FIX_4K_F0000, 1897151Sgblack@eecs.umich.edu MISCREG_MTRR_FIX_4K_F8000, 1907151Sgblack@eecs.umich.edu 1917151Sgblack@eecs.umich.edu MISCREG_PAT, 1927151Sgblack@eecs.umich.edu 193 MISCREG_DEF_TYPE, 194 195 MISCREG_MC_CTL_BASE, 196 MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE, 197 MISCREG_MC1_CTL, 198 MISCREG_MC2_CTL, 199 MISCREG_MC3_CTL, 200 MISCREG_MC4_CTL, 201 MISCREG_MC5_CTL, 202 MISCREG_MC6_CTL, 203 MISCREG_MC7_CTL, 204 205 MISCREG_MC_STATUS_BASE, 206 MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE, 207 MISCREG_MC1_STATUS, 208 MISCREG_MC2_STATUS, 209 MISCREG_MC3_STATUS, 210 MISCREG_MC4_STATUS, 211 MISCREG_MC5_STATUS, 212 MISCREG_MC6_STATUS, 213 MISCREG_MC7_STATUS, 214 215 MISCREG_MC_ADDR_BASE, 216 MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE, 217 MISCREG_MC1_ADDR, 218 MISCREG_MC2_ADDR, 219 MISCREG_MC3_ADDR, 220 MISCREG_MC4_ADDR, 221 MISCREG_MC5_ADDR, 222 MISCREG_MC6_ADDR, 223 MISCREG_MC7_ADDR, 224 225 MISCREG_MC_MISC_BASE, 226 MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE, 227 MISCREG_MC1_MISC, 228 MISCREG_MC2_MISC, 229 MISCREG_MC3_MISC, 230 MISCREG_MC4_MISC, 231 MISCREG_MC5_MISC, 232 MISCREG_MC6_MISC, 233 MISCREG_MC7_MISC, 234 235 // Extended feature enable register 236 MISCREG_EFER, 237 238 MISCREG_STAR, 239 MISCREG_LSTAR, 240 MISCREG_CSTAR, 241 242 MISCREG_SF_MASK, 243 244 MISCREG_KERNEL_GS_BASE, 245 246 MISCREG_TSC_AUX, 247 248 MISCREG_PERF_EVT_SEL_BASE, 249 MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE, 250 MISCREG_PERF_EVT_SEL1, 251 MISCREG_PERF_EVT_SEL2, 252 MISCREG_PERF_EVT_SEL3, 253 254 MISCREG_PERF_EVT_CTR_BASE, 255 MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE, 256 MISCREG_PERF_EVT_CTR1, 257 MISCREG_PERF_EVT_CTR2, 258 MISCREG_PERF_EVT_CTR3, 259 260 MISCREG_SYSCFG, 261 262 MISCREG_IORR_BASE_BASE, 263 MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE, 264 MISCREG_IORR_BASE1, 265 266 MISCREG_IORR_MASK_BASE, 267 MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE, 268 MISCREG_IORR_MASK1, 269 270 MISCREG_TOP_MEM, 271 MISCREG_TOP_MEM2, 272 273 MISCREG_VM_CR, 274 MISCREG_IGNNE, 275 MISCREG_SMM_CTL, 276 MISCREG_VM_HSAVE_PA, 277 278 /* 279 * Segment registers 280 */ 281 // Segment selectors 282 MISCREG_SEG_SEL_BASE, 283 MISCREG_ES = MISCREG_SEG_SEL_BASE, 284 MISCREG_CS, 285 MISCREG_SS, 286 MISCREG_DS, 287 MISCREG_FS, 288 MISCREG_GS, 289 MISCREG_HS, 290 MISCREG_TSL, 291 MISCREG_TSG, 292 MISCREG_LS, 293 MISCREG_MS, 294 MISCREG_TR, 295 MISCREG_IDTR, 296 297 // Hidden segment base field 298 MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS, 299 MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE, 300 MISCREG_CS_BASE, 301 MISCREG_SS_BASE, 302 MISCREG_DS_BASE, 303 MISCREG_FS_BASE, 304 MISCREG_GS_BASE, 305 MISCREG_HS_BASE, 306 MISCREG_TSL_BASE, 307 MISCREG_TSG_BASE, 308 MISCREG_LS_BASE, 309 MISCREG_MS_BASE, 310 MISCREG_TR_BASE, 311 MISCREG_IDTR_BASE, 312 313 // The effective segment base, ie what is actually added to an 314 // address. In 64 bit mode this can be different from the above, 315 // namely 0. 316 MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS, 317 MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE, 318 MISCREG_CS_EFF_BASE, 319 MISCREG_SS_EFF_BASE, 320 MISCREG_DS_EFF_BASE, 321 MISCREG_FS_EFF_BASE, 322 MISCREG_GS_EFF_BASE, 323 MISCREG_HS_EFF_BASE, 324 MISCREG_TSL_EFF_BASE, 325 MISCREG_TSG_EFF_BASE, 326 MISCREG_LS_EFF_BASE, 327 MISCREG_MS_EFF_BASE, 328 MISCREG_TR_EFF_BASE, 329 MISCREG_IDTR_EFF_BASE, 330 331 // Hidden segment limit field 332 MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS, 333 MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE, 334 MISCREG_CS_LIMIT, 335 MISCREG_SS_LIMIT, 336 MISCREG_DS_LIMIT, 337 MISCREG_FS_LIMIT, 338 MISCREG_GS_LIMIT, 339 MISCREG_HS_LIMIT, 340 MISCREG_TSL_LIMIT, 341 MISCREG_TSG_LIMIT, 342 MISCREG_LS_LIMIT, 343 MISCREG_MS_LIMIT, 344 MISCREG_TR_LIMIT, 345 MISCREG_IDTR_LIMIT, 346 347 // Hidden segment limit attributes 348 MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS, 349 MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE, 350 MISCREG_CS_ATTR, 351 MISCREG_SS_ATTR, 352 MISCREG_DS_ATTR, 353 MISCREG_FS_ATTR, 354 MISCREG_GS_ATTR, 355 MISCREG_HS_ATTR, 356 MISCREG_TSL_ATTR, 357 MISCREG_TSG_ATTR, 358 MISCREG_LS_ATTR, 359 MISCREG_MS_ATTR, 360 MISCREG_TR_ATTR, 361 MISCREG_IDTR_ATTR, 362 363 // Floating point control registers 364 MISCREG_X87_TOP = 365 MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS, 366 367 //XXX Add "Model-Specific Registers" 368 369 MISCREG_APIC_BASE, 370 371 MISCREG_APIC_START, 372 MISCREG_APIC_ID = MISCREG_APIC_START, 373 MISCREG_APIC_VERSION, 374 MISCREG_APIC_TASK_PRIORITY, 375 MISCREG_APIC_ARBITRATION_PRIORITY, 376 MISCREG_APIC_PROCESSOR_PRIORITY, 377 MISCREG_APIC_EOI, 378 MISCREG_APIC_LOGICAL_DESTINATION, 379 MISCREG_APIC_DESTINATION_FORMAT, 380 MISCREG_APIC_SPURIOUS_INTERRUPT_VECTOR, 381 382 MISCREG_APIC_IN_SERVICE_BASE, 383 384 MISCREG_APIC_TRIGGER_MODE_BASE = MISCREG_APIC_IN_SERVICE_BASE + 16, 385 386 MISCREG_APIC_INTERRUPT_REQUEST_BASE = 387 MISCREG_APIC_TRIGGER_MODE_BASE + 16, 388 389 MISCREG_APIC_ERROR_STATUS = MISCREG_APIC_INTERRUPT_REQUEST_BASE + 16, 390 MISCREG_APIC_INTERRUPT_COMMAND_LOW, 391 MISCREG_APIC_INTERRUPT_COMMAND_HIGH, 392 MISCREG_APIC_LVT_TIMER, 393 MISCREG_APIC_LVT_THERMAL_SENSOR, 394 MISCREG_APIC_LVT_PERFORMANCE_MONITORING_COUNTERS, 395 MISCREG_APIC_LVT_LINT0, 396 MISCREG_APIC_LVT_LINT1, 397 MISCREG_APIC_LVT_ERROR, 398 MISCREG_APIC_INITIAL_COUNT, 399 MISCREG_APIC_CURRENT_COUNT, 400 MISCREG_APIC_DIVIDE_COUNT, 401 MISCREG_APIC_END = MISCREG_APIC_DIVIDE_COUNT, 402 403 MISCREG_APIC_INTERNAL_STATE, 404 405 // "Fake" MSRs for internally implemented devices 406 MISCREG_PCI_CONFIG_ADDRESS, 407 408 NUM_MISCREGS 409 }; 410 411 static inline MiscRegIndex 412 MISCREG_CR(int index) 413 { 414 return (MiscRegIndex)(MISCREG_CR_BASE + index); 415 } 416 417 static inline MiscRegIndex 418 MISCREG_DR(int index) 419 { 420 return (MiscRegIndex)(MISCREG_DR_BASE + index); 421 } 422 423 static inline MiscRegIndex 424 MISCREG_MTRR_PHYS_BASE(int index) 425 { 426 return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index); 427 } 428 429 static inline MiscRegIndex 430 MISCREG_MTRR_PHYS_MASK(int index) 431 { 432 return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index); 433 } 434 435 static inline MiscRegIndex 436 MISCREG_MC_CTL(int index) 437 { 438 return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index); 439 } 440 441 static inline MiscRegIndex 442 MISCREG_MC_STATUS(int index) 443 { 444 return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index); 445 } 446 447 static inline MiscRegIndex 448 MISCREG_MC_ADDR(int index) 449 { 450 return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index); 451 } 452 453 static inline MiscRegIndex 454 MISCREG_MC_MISC(int index) 455 { 456 return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index); 457 } 458 459 static inline MiscRegIndex 460 MISCREG_PERF_EVT_SEL(int index) 461 { 462 return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index); 463 } 464 465 static inline MiscRegIndex 466 MISCREG_PERF_EVT_CTR(int index) 467 { 468 return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index); 469 } 470 471 static inline MiscRegIndex 472 MISCREG_IORR_BASE(int index) 473 { 474 return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index); 475 } 476 477 static inline MiscRegIndex 478 MISCREG_IORR_MASK(int index) 479 { 480 return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index); 481 } 482 483 static inline MiscRegIndex 484 MISCREG_SEG_SEL(int index) 485 { 486 return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index); 487 } 488 489 static inline MiscRegIndex 490 MISCREG_SEG_BASE(int index) 491 { 492 return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index); 493 } 494 495 static inline MiscRegIndex 496 MISCREG_SEG_EFF_BASE(int index) 497 { 498 return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index); 499 } 500 501 static inline MiscRegIndex 502 MISCREG_SEG_LIMIT(int index) 503 { 504 return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index); 505 } 506 507 static inline MiscRegIndex 508 MISCREG_SEG_ATTR(int index) 509 { 510 return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index); 511 } 512 513 static inline MiscRegIndex 514 MISCREG_APIC_IN_SERVICE(int index) 515 { 516 return (MiscRegIndex)(MISCREG_APIC_IN_SERVICE_BASE + index); 517 } 518 519 static inline MiscRegIndex 520 MISCREG_APIC_TRIGGER_MODE(int index) 521 { 522 return (MiscRegIndex)(MISCREG_APIC_TRIGGER_MODE_BASE + index); 523 } 524 525 static inline MiscRegIndex 526 MISCREG_APIC_INTERRUPT_REQUEST(int index) 527 { 528 return (MiscRegIndex)(MISCREG_APIC_INTERRUPT_REQUEST_BASE + index); 529 } 530 531 /** 532 * A type to describe the condition code bits of the RFLAGS register, 533 * plus two flags, EZF and ECF, which are only visible to microcode. 534 */ 535 BitUnion64(CCFlagBits) 536 Bitfield<11> of; 537 Bitfield<7> sf; 538 Bitfield<6> zf; 539 Bitfield<5> ezf; 540 Bitfield<4> af; 541 Bitfield<3> ecf; 542 Bitfield<2> pf; 543 Bitfield<0> cf; 544 EndBitUnion(CCFlagBits) 545 546 /** 547 * RFLAGS 548 */ 549 BitUnion64(RFLAGS) 550 Bitfield<21> id; // ID Flag 551 Bitfield<20> vip; // Virtual Interrupt Pending 552 Bitfield<19> vif; // Virtual Interrupt Flag 553 Bitfield<18> ac; // Alignment Check 554 Bitfield<17> vm; // Virtual-8086 Mode 555 Bitfield<16> rf; // Resume Flag 556 Bitfield<14> nt; // Nested Task 557 Bitfield<13, 12> iopl; // I/O Privilege Level 558 Bitfield<11> of; // Overflow Flag 559 Bitfield<10> df; // Direction Flag 560 Bitfield<9> intf; // Interrupt Flag 561 Bitfield<8> tf; // Trap Flag 562 Bitfield<7> sf; // Sign Flag 563 Bitfield<6> zf; // Zero Flag 564 Bitfield<4> af; // Auxiliary Flag 565 Bitfield<2> pf; // Parity Flag 566 Bitfield<0> cf; // Carry Flag 567 EndBitUnion(RFLAGS) 568 569 BitUnion64(HandyM5Reg) 570 Bitfield<0> mode; 571 Bitfield<3, 1> submode; 572 Bitfield<5, 4> cpl; 573 EndBitUnion(HandyM5Reg) 574 575 /** 576 * Control registers 577 */ 578 BitUnion64(CR0) 579 Bitfield<31> pg; // Paging 580 Bitfield<30> cd; // Cache Disable 581 Bitfield<29> nw; // Not Writethrough 582 Bitfield<18> am; // Alignment Mask 583 Bitfield<16> wp; // Write Protect 584 Bitfield<5> ne; // Numeric Error 585 Bitfield<4> et; // Extension Type 586 Bitfield<3> ts; // Task Switched 587 Bitfield<2> em; // Emulation 588 Bitfield<1> mp; // Monitor Coprocessor 589 Bitfield<0> pe; // Protection Enabled 590 EndBitUnion(CR0) 591 592 // Page Fault Virtual Address 593 BitUnion64(CR2) 594 Bitfield<31, 0> legacy; 595 EndBitUnion(CR2) 596 597 BitUnion64(CR3) 598 Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table 599 // Base Address 600 Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table 601 // Base Address 602 Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table 603 // Base Address 604 Bitfield<4> pcd; // Page-Level Cache Disable 605 Bitfield<3> pwt; // Page-Level Writethrough 606 EndBitUnion(CR3) 607 608 BitUnion64(CR4) 609 Bitfield<10> osxmmexcpt; // Operating System Unmasked 610 // Exception Support 611 Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support 612 Bitfield<8> pce; // Performance-Monitoring Counter Enable 613 Bitfield<7> pge; // Page-Global Enable 614 Bitfield<6> mce; // Machine Check Enable 615 Bitfield<5> pae; // Physical-Address Extension 616 Bitfield<4> pse; // Page Size Extensions 617 Bitfield<3> de; // Debugging Extensions 618 Bitfield<2> tsd; // Time Stamp Disable 619 Bitfield<1> pvi; // Protected-Mode Virtual Interrupts 620 Bitfield<0> vme; // Virtual-8086 Mode Extensions 621 EndBitUnion(CR4) 622 623 BitUnion64(CR8) 624 Bitfield<3, 0> tpr; // Task Priority Register 625 EndBitUnion(CR8) 626 627 // MTRR capabilities 628 BitUnion64(MTRRcap) 629 Bitfield<7, 0> vcnt; // Variable-Range Register Count 630 Bitfield<8> fix; // Fixed-Range Registers 631 Bitfield<10> wc; // Write-Combining 632 EndBitUnion(MTRRcap) 633 634 /** 635 * SYSENTER configuration registers 636 */ 637 BitUnion64(SysenterCS) 638 Bitfield<15, 0> targetCS; 639 EndBitUnion(SysenterCS) 640 641 BitUnion64(SysenterESP) 642 Bitfield<31, 0> targetESP; 643 EndBitUnion(SysenterESP) 644 645 BitUnion64(SysenterEIP) 646 Bitfield<31, 0> targetEIP; 647 EndBitUnion(SysenterEIP) 648 649 /** 650 * Global machine check registers 651 */ 652 BitUnion64(McgCap) 653 Bitfield<7, 0> count; // Number of error reporting register banks 654 Bitfield<8> MCGCP; // MCG_CTL register present. 655 EndBitUnion(McgCap) 656 657 BitUnion64(McgStatus) 658 Bitfield<0> ripv; // Restart-IP valid 659 Bitfield<1> eipv; // Error-IP valid 660 Bitfield<2> mcip; // Machine check in-progress 661 EndBitUnion(McgStatus) 662 663 BitUnion64(DebugCtlMsr) 664 Bitfield<0> lbr; // Last-branch record 665 Bitfield<1> btf; // Branch single step 666 Bitfield<2> pb0; // Performance monitoring pin control 0 667 Bitfield<3> pb1; // Performance monitoring pin control 1 668 Bitfield<4> pb2; // Performance monitoring pin control 2 669 Bitfield<5> pb3; // Performance monitoring pin control 3 670 /*uint64_t pb(int index) 671 { 672 return bits(__data, index + 2); 673 }*/ 674 EndBitUnion(DebugCtlMsr) 675 676 BitUnion64(MtrrPhysBase) 677 Bitfield<7, 0> type; // Default memory type 678 Bitfield<51, 12> physbase; // Range physical base address 679 EndBitUnion(MtrrPhysBase) 680 681 BitUnion64(MtrrPhysMask) 682 Bitfield<11> valid; // MTRR pair enable 683 Bitfield<51, 12> physmask; // Range physical mask 684 EndBitUnion(MtrrPhysMask) 685 686 BitUnion64(MtrrFixed) 687 /*uint64_t type(int index) 688 { 689 return bits(__data, index * 8 + 7, index * 8); 690 }*/ 691 EndBitUnion(MtrrFixed) 692 693 BitUnion64(Pat) 694 /*uint64_t pa(int index) 695 { 696 return bits(__data, index * 8 + 2, index * 8); 697 }*/ 698 EndBitUnion(Pat) 699 700 BitUnion64(MtrrDefType) 701 Bitfield<7, 0> type; // Default type 702 Bitfield<10> fe; // Fixed range enable 703 Bitfield<11> e; // MTRR enable 704 EndBitUnion(MtrrDefType) 705 706 /** 707 * Machine check 708 */ 709 BitUnion64(McStatus) 710 Bitfield<15,0> mcaErrorCode; 711 Bitfield<31,16> modelSpecificCode; 712 Bitfield<56,32> otherInfo; 713 Bitfield<57> pcc; // Processor-context corrupt 714 Bitfield<58> addrv; // Error-address register valid 715 Bitfield<59> miscv; // Miscellaneous-error register valid 716 Bitfield<60> en; // Error condition enabled 717 Bitfield<61> uc; // Uncorrected error 718 Bitfield<62> over; // Status register overflow 719 Bitfield<63> val; // Valid 720 EndBitUnion(McStatus) 721 722 BitUnion64(McCtl) 723 /*uint64_t en(int index) 724 { 725 return bits(__data, index); 726 }*/ 727 EndBitUnion(McCtl) 728 729 // Extended feature enable register 730 BitUnion64(Efer) 731 Bitfield<0> sce; // System call extensions 732 Bitfield<8> lme; // Long mode enable 733 Bitfield<10> lma; // Long mode active 734 Bitfield<11> nxe; // No-execute enable 735 Bitfield<12> svme; // Secure virtual machine enable 736 Bitfield<14> ffxsr; // Fast fxsave/fxrstor 737 EndBitUnion(Efer) 738 739 BitUnion64(Star) 740 Bitfield<31,0> targetEip; 741 Bitfield<47,32> syscallCsAndSs; 742 Bitfield<63,48> sysretCsAndSs; 743 EndBitUnion(Star) 744 745 BitUnion64(SfMask) 746 Bitfield<31,0> mask; 747 EndBitUnion(SfMask) 748 749 BitUnion64(PerfEvtSel) 750 Bitfield<7,0> eventMask; 751 Bitfield<15,8> unitMask; 752 Bitfield<16> usr; // User mode 753 Bitfield<17> os; // Operating-system mode 754 Bitfield<18> e; // Edge detect 755 Bitfield<19> pc; // Pin control 756 Bitfield<20> intEn; // Interrupt enable 757 Bitfield<22> en; // Counter enable 758 Bitfield<23> inv; // Invert mask 759 Bitfield<31,24> counterMask; 760 EndBitUnion(PerfEvtSel) 761 762 BitUnion32(Syscfg) 763 Bitfield<18> mfde; // MtrrFixDramEn 764 Bitfield<19> mfdm; // MtrrFixDramModEn 765 Bitfield<20> mvdm; // MtrrVarDramEn 766 Bitfield<21> tom2; // MtrrTom2En 767 EndBitUnion(Syscfg) 768 769 BitUnion64(IorrBase) 770 Bitfield<3> wr; // WrMem Enable 771 Bitfield<4> rd; // RdMem Enable 772 Bitfield<51,12> physbase; // Range physical base address 773 EndBitUnion(IorrBase) 774 775 BitUnion64(IorrMask) 776 Bitfield<11> v; // I/O register pair enable (valid) 777 Bitfield<51,12> physmask; // Range physical mask 778 EndBitUnion(IorrMask) 779 780 BitUnion64(Tom) 781 Bitfield<51,23> physAddr; // Top of memory physical address 782 EndBitUnion(Tom) 783 784 BitUnion64(VmCrMsr) 785 Bitfield<0> dpd; 786 Bitfield<1> rInit; 787 Bitfield<2> disA20M; 788 EndBitUnion(VmCrMsr) 789 790 BitUnion64(IgnneMsr) 791 Bitfield<0> ignne; 792 EndBitUnion(IgnneMsr) 793 794 BitUnion64(SmmCtlMsr) 795 Bitfield<0> dismiss; 796 Bitfield<1> enter; 797 Bitfield<2> smiCycle; 798 Bitfield<3> exit; 799 Bitfield<4> rsmCycle; 800 EndBitUnion(SmmCtlMsr) 801 802 /** 803 * Segment Selector 804 */ 805 BitUnion64(SegSelector) 806 // The following bitfield is not defined in the ISA, but it's useful 807 // when checking selectors in larger data types to make sure they 808 // aren't too large. 809 Bitfield<63, 3> esi; // Extended selector 810 Bitfield<15, 3> si; // Selector Index 811 Bitfield<2> ti; // Table Indicator 812 Bitfield<1, 0> rpl; // Requestor Privilege Level 813 EndBitUnion(SegSelector) 814 815 /** 816 * Segment Descriptors 817 */ 818 819 BitUnion64(SegDescriptor) 820 Bitfield<63, 56> baseHigh; 821 Bitfield<39, 16> baseLow; 822 Bitfield<55> g; // Granularity 823 Bitfield<54> d; // Default Operand Size 824 Bitfield<54> b; // Default Operand Size 825 Bitfield<53> l; // Long Attribute Bit 826 Bitfield<52> avl; // Available To Software 827 Bitfield<51, 48> limitHigh; 828 Bitfield<15, 0> limitLow; 829 Bitfield<47> p; // Present 830 Bitfield<46, 45> dpl; // Descriptor Privilege-Level 831 Bitfield<44> s; // System 832 SubBitUnion(type, 43, 40) 833 // Specifies whether this descriptor is for code or data. 834 Bitfield<43> codeOrData; 835 836 // These bit fields are for code segments 837 Bitfield<42> c; // Conforming 838 Bitfield<41> r; // Readable 839 840 // These bit fields are for data segments 841 Bitfield<42> e; // Expand-Down 842 Bitfield<41> w; // Writable 843 844 // This is used for both code and data segments. 845 Bitfield<40> a; // Accessed 846 EndSubBitUnion(type) 847 EndBitUnion(SegDescriptor) 848 849 BitUnion64(SegAttr) 850 Bitfield<0> writable; 851 Bitfield<1> readable; 852 Bitfield<2> expandDown; 853 Bitfield<4, 3> dpl; 854 Bitfield<5> defaultSize; 855 Bitfield<6> longMode; 856 EndBitUnion(SegAttr) 857 858 BitUnion64(GateDescriptor) 859 Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset 860 Bitfield<15, 0> offsetLow; // Target Code-Segment Offset 861 Bitfield<31, 16> selector; // Target Code-Segment Selector 862 Bitfield<47> p; // Present 863 Bitfield<46, 45> dpl; // Descriptor Privilege-Level 864 Bitfield<43, 40> type; 865 Bitfield<36, 32> count; // Parameter Count 866 EndBitUnion(GateDescriptor) 867 868 /** 869 * Descriptor-Table Registers 870 */ 871 BitUnion64(GDTR) 872 EndBitUnion(GDTR) 873 874 BitUnion64(IDTR) 875 EndBitUnion(IDTR) 876 877 BitUnion64(LDTR) 878 EndBitUnion(LDTR) 879 880 /** 881 * Task Register 882 */ 883 BitUnion64(TR) 884 EndBitUnion(TR) 885 886 887 /** 888 * Local APIC Base Register 889 */ 890 BitUnion64(LocalApicBase) 891 Bitfield<51, 12> base; 892 Bitfield<11> enable; 893 Bitfield<8> bsp; 894 EndBitUnion(LocalApicBase) 895}; 896 897#endif // __ARCH_X86_INTREGS_HH__ 898