misc.hh revision 5419
1/* 2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * 9 * The software must be used only for Non-Commercial Use which means any 10 * use which is NOT directed to receiving any direct monetary 11 * compensation for, or commercial advantage from such use. Illustrative 12 * examples of non-commercial use are academic research, personal study, 13 * teaching, education and corporate research & development. 14 * Illustrative examples of commercial use are distributing products for 15 * commercial advantage and providing services using the software for 16 * commercial advantage. 17 * 18 * If you wish to use this software or functionality therein that may be 19 * covered by patents for commercial use, please contact: 20 * Director of Intellectual Property Licensing 21 * Office of Strategy and Technology 22 * Hewlett-Packard Company 23 * 1501 Page Mill Road 24 * Palo Alto, California 94304 25 * 26 * Redistributions of source code must retain the above copyright notice, 27 * this list of conditions and the following disclaimer. Redistributions 28 * in binary form must reproduce the above copyright notice, this list of 29 * conditions and the following disclaimer in the documentation and/or 30 * other materials provided with the distribution. Neither the name of 31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 32 * contributors may be used to endorse or promote products derived from 33 * this software without specific prior written permission. No right of 34 * sublicense is granted herewith. Derivatives of the software and 35 * output created using the software may be prepared, but only for 36 * Non-Commercial Uses. Derivatives of the software may be shared with 37 * others provided: (i) the others agree to abide by the list of 38 * conditions herein which includes the Non-Commercial Use restrictions; 39 * and (ii) such Derivatives of the software include the above copyright 40 * notice to acknowledge the contribution from this software where 41 * applicable, this list of conditions and the disclaimer below. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * 55 * Authors: Gabe Black 56 */ 57 58#ifndef __ARCH_X86_MISCREGS_HH__ 59#define __ARCH_X86_MISCREGS_HH__ 60 61#include "arch/x86/segmentregs.hh" 62#include "arch/x86/x86_traits.hh" 63#include "base/bitunion.hh" 64 65//These get defined in some system headers (at least termbits.h). That confuses 66//things here significantly. 67#undef CR0 68#undef CR2 69#undef CR3 70 71namespace X86ISA 72{ 73 enum CondFlagBit { 74 CFBit = 1 << 0, 75 PFBit = 1 << 2, 76 ECFBit = 1 << 3, 77 AFBit = 1 << 4, 78 EZFBit = 1 << 5, 79 ZFBit = 1 << 6, 80 SFBit = 1 << 7, 81 DFBit = 1 << 10, 82 OFBit = 1 << 11 83 }; 84 85 enum MiscRegIndex 86 { 87 // Control registers 88 // Most of these are invalid. 89 MISCREG_CR_BASE, 90 MISCREG_CR0 = MISCREG_CR_BASE, 91 MISCREG_CR1, 92 MISCREG_CR2, 93 MISCREG_CR3, 94 MISCREG_CR4, 95 MISCREG_CR5, 96 MISCREG_CR6, 97 MISCREG_CR7, 98 MISCREG_CR8, 99 MISCREG_CR9, 100 MISCREG_CR10, 101 MISCREG_CR11, 102 MISCREG_CR12, 103 MISCREG_CR13, 104 MISCREG_CR14, 105 MISCREG_CR15, 106 107 // Debug registers 108 MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs, 109 MISCREG_DR0 = MISCREG_DR_BASE, 110 MISCREG_DR1, 111 MISCREG_DR2, 112 MISCREG_DR3, 113 MISCREG_DR4, 114 MISCREG_DR5, 115 MISCREG_DR6, 116 MISCREG_DR7, 117 118 // Flags register 119 MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs, 120 121 /* 122 * Model Specific Registers 123 */ 124 // Time stamp counter 125 MISCREG_TSC, 126 127 MISCREG_MTRRCAP, 128 129 MISCREG_SYSENTER_CS, 130 MISCREG_SYSENTER_ESP, 131 MISCREG_SYSENTER_EIP, 132 133 MISCREG_MCG_CAP, 134 MISCREG_MCG_STATUS, 135 MISCREG_MCG_CTL, 136 137 MISCREG_DEBUG_CTL_MSR, 138 139 MISCREG_LAST_BRANCH_FROM_IP, 140 MISCREG_LAST_BRANCH_TO_IP, 141 MISCREG_LAST_EXCEPTION_FROM_IP, 142 MISCREG_LAST_EXCEPTION_TO_IP, 143 144 MISCREG_MTRR_PHYS_BASE_BASE, 145 MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE, 146 MISCREG_MTRR_PHYS_BASE_1, 147 MISCREG_MTRR_PHYS_BASE_2, 148 MISCREG_MTRR_PHYS_BASE_3, 149 MISCREG_MTRR_PHYS_BASE_4, 150 MISCREG_MTRR_PHYS_BASE_5, 151 MISCREG_MTRR_PHYS_BASE_6, 152 MISCREG_MTRR_PHYS_BASE_7, 153 154 MISCREG_MTRR_PHYS_MASK_BASE, 155 MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE, 156 MISCREG_MTRR_PHYS_MASK_1, 157 MISCREG_MTRR_PHYS_MASK_2, 158 MISCREG_MTRR_PHYS_MASK_3, 159 MISCREG_MTRR_PHYS_MASK_4, 160 MISCREG_MTRR_PHYS_MASK_5, 161 MISCREG_MTRR_PHYS_MASK_6, 162 MISCREG_MTRR_PHYS_MASK_7, 163 164 MISCREG_MTRR_FIX_64K_00000, 165 MISCREG_MTRR_FIX_16K_80000, 166 MISCREG_MTRR_FIX_16K_A0000, 167 MISCREG_MTRR_FIX_4K_C0000, 168 MISCREG_MTRR_FIX_4K_C8000, 169 MISCREG_MTRR_FIX_4K_D0000, 170 MISCREG_MTRR_FIX_4K_D8000, 171 MISCREG_MTRR_FIX_4K_E0000, 172 MISCREG_MTRR_FIX_4K_E8000, 173 MISCREG_MTRR_FIX_4K_F0000, 174 MISCREG_MTRR_FIX_4K_F8000, 175 176 MISCREG_PAT, 177 178 MISCREG_DEF_TYPE, 179 180 MISCREG_MC_CTL_BASE, 181 MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE, 182 MISCREG_MC1_CTL, 183 MISCREG_MC2_CTL, 184 MISCREG_MC3_CTL, 185 MISCREG_MC4_CTL, 186 MISCREG_MC5_CTL, 187 MISCREG_MC6_CTL, 188 MISCREG_MC7_CTL, 189 190 MISCREG_MC_STATUS_BASE, 191 MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE, 192 MISCREG_MC1_STATUS, 193 MISCREG_MC2_STATUS, 194 MISCREG_MC3_STATUS, 195 MISCREG_MC4_STATUS, 196 MISCREG_MC5_STATUS, 197 MISCREG_MC6_STATUS, 198 MISCREG_MC7_STATUS, 199 200 MISCREG_MC_ADDR_BASE, 201 MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE, 202 MISCREG_MC1_ADDR, 203 MISCREG_MC2_ADDR, 204 MISCREG_MC3_ADDR, 205 MISCREG_MC4_ADDR, 206 MISCREG_MC5_ADDR, 207 MISCREG_MC6_ADDR, 208 MISCREG_MC7_ADDR, 209 210 MISCREG_MC_MISC_BASE, 211 MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE, 212 MISCREG_MC1_MISC, 213 MISCREG_MC2_MISC, 214 MISCREG_MC3_MISC, 215 MISCREG_MC4_MISC, 216 MISCREG_MC5_MISC, 217 MISCREG_MC6_MISC, 218 MISCREG_MC7_MISC, 219 220 // Extended feature enable register 221 MISCREG_EFER, 222 223 MISCREG_STAR, 224 MISCREG_LSTAR, 225 MISCREG_CSTAR, 226 227 MISCREG_SF_MASK, 228 229 MISCREG_KERNEL_GS_BASE, 230 231 MISCREG_TSC_AUX, 232 233 MISCREG_PERF_EVT_SEL_BASE, 234 MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE, 235 MISCREG_PERF_EVT_SEL1, 236 MISCREG_PERF_EVT_SEL2, 237 MISCREG_PERF_EVT_SEL3, 238 239 MISCREG_PERF_EVT_CTR_BASE, 240 MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE, 241 MISCREG_PERF_EVT_CTR1, 242 MISCREG_PERF_EVT_CTR2, 243 MISCREG_PERF_EVT_CTR3, 244 245 MISCREG_SYSCFG, 246 247 MISCREG_IORR_BASE_BASE, 248 MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE, 249 MISCREG_IORR_BASE1, 250 251 MISCREG_IORR_MASK_BASE, 252 MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE, 253 MISCREG_IORR_MASK1, 254 255 MISCREG_TOP_MEM, 256 MISCREG_TOP_MEM2, 257 258 MISCREG_VM_CR, 259 MISCREG_IGNNE, 260 MISCREG_SMM_CTL, 261 MISCREG_VM_HSAVE_PA, 262 263 /* 264 * Segment registers 265 */ 266 // Segment selectors 267 MISCREG_SEG_SEL_BASE, 268 MISCREG_ES = MISCREG_SEG_SEL_BASE, 269 MISCREG_CS, 270 MISCREG_SS, 271 MISCREG_DS, 272 MISCREG_FS, 273 MISCREG_GS, 274 MISCREG_HS, 275 MISCREG_TSL, 276 MISCREG_TSG, 277 MISCREG_LS, 278 MISCREG_MS, 279 MISCREG_TR, 280 MISCREG_IDTR, 281 282 // Hidden segment base field 283 MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS, 284 MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE, 285 MISCREG_CS_BASE, 286 MISCREG_SS_BASE, 287 MISCREG_DS_BASE, 288 MISCREG_FS_BASE, 289 MISCREG_GS_BASE, 290 MISCREG_HS_BASE, 291 MISCREG_TSL_BASE, 292 MISCREG_TSG_BASE, 293 MISCREG_LS_BASE, 294 MISCREG_MS_BASE, 295 MISCREG_TR_BASE, 296 MISCREG_IDTR_BASE, 297 298 // The effective segment base, ie what is actually added to an 299 // address. In 64 bit mode this can be different from the above, 300 // namely 0. 301 MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS, 302 MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE, 303 MISCREG_CS_EFF_BASE, 304 MISCREG_SS_EFF_BASE, 305 MISCREG_DS_EFF_BASE, 306 MISCREG_FS_EFF_BASE, 307 MISCREG_GS_EFF_BASE, 308 MISCREG_HS_EFF_BASE, 309 MISCREG_TSL_EFF_BASE, 310 MISCREG_TSG_EFF_BASE, 311 MISCREG_LS_EFF_BASE, 312 MISCREG_MS_EFF_BASE, 313 MISCREG_TR_EFF_BASE, 314 MISCREG_IDTR_EFF_BASE, 315 316 // Hidden segment limit field 317 MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS, 318 MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE, 319 MISCREG_CS_LIMIT, 320 MISCREG_SS_LIMIT, 321 MISCREG_DS_LIMIT, 322 MISCREG_FS_LIMIT, 323 MISCREG_GS_LIMIT, 324 MISCREG_HS_LIMIT, 325 MISCREG_TSL_LIMIT, 326 MISCREG_TSG_LIMIT, 327 MISCREG_LS_LIMIT, 328 MISCREG_MS_LIMIT, 329 MISCREG_TR_LIMIT, 330 MISCREG_IDTR_LIMIT, 331 332 // Hidden segment limit attributes 333 MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS, 334 MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE, 335 MISCREG_CS_ATTR, 336 MISCREG_SS_ATTR, 337 MISCREG_DS_ATTR, 338 MISCREG_FS_ATTR, 339 MISCREG_GS_ATTR, 340 MISCREG_HS_ATTR, 341 MISCREG_TSL_ATTR, 342 MISCREG_TSG_ATTR, 343 MISCREG_LS_ATTR, 344 MISCREG_MS_ATTR, 345 MISCREG_TR_ATTR, 346 MISCREG_IDTR_ATTR, 347 348 // Floating point control registers 349 MISCREG_X87_TOP = 350 MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS, 351 352 //XXX Add "Model-Specific Registers" 353 354 MISCREG_APIC_BASE, 355 356 MISCREG_APIC_START, 357 MISCREG_APIC_ID = MISCREG_APIC_START, 358 MISCREG_APIC_VERSION, 359 MISCREG_APIC_TASK_PRIORITY, 360 MISCREG_APIC_ARBITRATION_PRIORITY, 361 MISCREG_APIC_PROCESSOR_PRIORITY, 362 MISCREG_APIC_EOI, 363 MISCREG_APIC_LOGICAL_DESTINATION, 364 MISCREG_APIC_DESTINATION_FORMAT, 365 MISCREG_APIC_SPURIOUS_INTERRUPT_VECTOR, 366 367 MISCREG_APIC_IN_SERVICE_BASE, 368 369 MISCREG_APIC_TRIGGER_MODE_BASE = MISCREG_APIC_IN_SERVICE_BASE + 16, 370 371 MISCREG_APIC_INTERRUPT_REQUEST_BASE = 372 MISCREG_APIC_TRIGGER_MODE_BASE + 16, 373 374 MISCREG_APIC_ERROR_STATUS = MISCREG_APIC_INTERRUPT_REQUEST_BASE + 16, 375 MISCREG_APIC_INTERRUPT_COMMAND_LOW, 376 MISCREG_APIC_INTERRUPT_COMMAND_HIGH, 377 MISCREG_APIC_LVT_TIMER, 378 MISCREG_APIC_LVT_THERMAL_SENSOR, 379 MISCREG_APIC_LVT_PERFORMANCE_MONITORING_COUNTERS, 380 MISCREG_APIC_LVT_LINT0, 381 MISCREG_APIC_LVT_LINT1, 382 MISCREG_APIC_LVT_ERROR, 383 MISCREG_APIC_INITIAL_COUNT, 384 MISCREG_APIC_CURRENT_COUNT, 385 MISCREG_APIC_DIVIDE_COUNT, 386 MISCREG_APIC_END = MISCREG_APIC_DIVIDE_COUNT, 387 388 MISCREG_APIC_INTERNAL_STATE, 389 390 // "Fake" MSRs for internally implemented devices 391 MISCREG_PCI_CONFIG_ADDRESS, 392 393 NUM_MISCREGS 394 }; 395 396 static inline MiscRegIndex 397 MISCREG_CR(int index) 398 { 399 return (MiscRegIndex)(MISCREG_CR_BASE + index); 400 } 401 402 static inline MiscRegIndex 403 MISCREG_DR(int index) 404 { 405 return (MiscRegIndex)(MISCREG_DR_BASE + index); 406 } 407 408 static inline MiscRegIndex 409 MISCREG_MTRR_PHYS_BASE(int index) 410 { 411 return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index); 412 } 413 414 static inline MiscRegIndex 415 MISCREG_MTRR_PHYS_MASK(int index) 416 { 417 return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index); 418 } 419 420 static inline MiscRegIndex 421 MISCREG_MC_CTL(int index) 422 { 423 return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index); 424 } 425 426 static inline MiscRegIndex 427 MISCREG_MC_STATUS(int index) 428 { 429 return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index); 430 } 431 432 static inline MiscRegIndex 433 MISCREG_MC_ADDR(int index) 434 { 435 return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index); 436 } 437 438 static inline MiscRegIndex 439 MISCREG_MC_MISC(int index) 440 { 441 return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index); 442 } 443 444 static inline MiscRegIndex 445 MISCREG_PERF_EVT_SEL(int index) 446 { 447 return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index); 448 } 449 450 static inline MiscRegIndex 451 MISCREG_PERF_EVT_CTR(int index) 452 { 453 return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index); 454 } 455 456 static inline MiscRegIndex 457 MISCREG_IORR_BASE(int index) 458 { 459 return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index); 460 } 461 462 static inline MiscRegIndex 463 MISCREG_IORR_MASK(int index) 464 { 465 return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index); 466 } 467 468 static inline MiscRegIndex 469 MISCREG_SEG_SEL(int index) 470 { 471 return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index); 472 } 473 474 static inline MiscRegIndex 475 MISCREG_SEG_BASE(int index) 476 { 477 return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index); 478 } 479 480 static inline MiscRegIndex 481 MISCREG_SEG_EFF_BASE(int index) 482 { 483 return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index); 484 } 485 486 static inline MiscRegIndex 487 MISCREG_SEG_LIMIT(int index) 488 { 489 return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index); 490 } 491 492 static inline MiscRegIndex 493 MISCREG_SEG_ATTR(int index) 494 { 495 return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index); 496 } 497 498 static inline MiscRegIndex 499 MISCREG_APIC_IN_SERVICE(int index) 500 { 501 return (MiscRegIndex)(MISCREG_APIC_IN_SERVICE_BASE + index); 502 } 503 504 static inline MiscRegIndex 505 MISCREG_APIC_TRIGGER_MODE(int index) 506 { 507 return (MiscRegIndex)(MISCREG_APIC_TRIGGER_MODE_BASE + index); 508 } 509 510 static inline MiscRegIndex 511 MISCREG_APIC_INTERRUPT_REQUEST(int index) 512 { 513 return (MiscRegIndex)(MISCREG_APIC_INTERRUPT_REQUEST_BASE + index); 514 } 515 516 /** 517 * A type to describe the condition code bits of the RFLAGS register, 518 * plus two flags, EZF and ECF, which are only visible to microcode. 519 */ 520 BitUnion64(CCFlagBits) 521 Bitfield<11> of; 522 Bitfield<7> sf; 523 Bitfield<6> zf; 524 Bitfield<5> ezf; 525 Bitfield<4> af; 526 Bitfield<3> ecf; 527 Bitfield<2> pf; 528 Bitfield<0> cf; 529 EndBitUnion(CCFlagBits) 530 531 /** 532 * RFLAGS 533 */ 534 BitUnion64(RFLAGS) 535 Bitfield<21> id; // ID Flag 536 Bitfield<20> vip; // Virtual Interrupt Pending 537 Bitfield<19> vif; // Virtual Interrupt Flag 538 Bitfield<18> ac; // Alignment Check 539 Bitfield<17> vm; // Virtual-8086 Mode 540 Bitfield<16> rf; // Resume Flag 541 Bitfield<14> nt; // Nested Task 542 Bitfield<13, 12> iopl; // I/O Privilege Level 543 Bitfield<11> of; // Overflow Flag 544 Bitfield<10> df; // Direction Flag 545 Bitfield<9> intf; // Interrupt Flag 546 Bitfield<8> tf; // Trap Flag 547 Bitfield<7> sf; // Sign Flag 548 Bitfield<6> zf; // Zero Flag 549 Bitfield<4> af; // Auxiliary Flag 550 Bitfield<2> pf; // Parity Flag 551 Bitfield<0> cf; // Carry Flag 552 EndBitUnion(RFLAGS) 553 554 /** 555 * Control registers 556 */ 557 BitUnion64(CR0) 558 Bitfield<31> pg; // Paging 559 Bitfield<30> cd; // Cache Disable 560 Bitfield<29> nw; // Not Writethrough 561 Bitfield<18> am; // Alignment Mask 562 Bitfield<16> wp; // Write Protect 563 Bitfield<5> ne; // Numeric Error 564 Bitfield<4> et; // Extension Type 565 Bitfield<3> ts; // Task Switched 566 Bitfield<2> em; // Emulation 567 Bitfield<1> mp; // Monitor Coprocessor 568 Bitfield<0> pe; // Protection Enabled 569 EndBitUnion(CR0) 570 571 // Page Fault Virtual Address 572 BitUnion64(CR2) 573 Bitfield<31, 0> legacy; 574 EndBitUnion(CR2) 575 576 BitUnion64(CR3) 577 Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table 578 // Base Address 579 Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table 580 // Base Address 581 Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table 582 // Base Address 583 Bitfield<4> pcd; // Page-Level Cache Disable 584 Bitfield<3> pwt; // Page-Level Writethrough 585 EndBitUnion(CR3) 586 587 BitUnion64(CR4) 588 Bitfield<10> osxmmexcpt; // Operating System Unmasked 589 // Exception Support 590 Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support 591 Bitfield<8> pce; // Performance-Monitoring Counter Enable 592 Bitfield<7> pge; // Page-Global Enable 593 Bitfield<6> mce; // Machine Check Enable 594 Bitfield<5> pae; // Physical-Address Extension 595 Bitfield<4> pse; // Page Size Extensions 596 Bitfield<3> de; // Debugging Extensions 597 Bitfield<2> tsd; // Time Stamp Disable 598 Bitfield<1> pvi; // Protected-Mode Virtual Interrupts 599 Bitfield<0> vme; // Virtual-8086 Mode Extensions 600 EndBitUnion(CR4) 601 602 BitUnion64(CR8) 603 Bitfield<3, 0> tpr; // Task Priority Register 604 EndBitUnion(CR8) 605 606 // MTRR capabilities 607 BitUnion64(MTRRcap) 608 Bitfield<7, 0> vcnt; // Variable-Range Register Count 609 Bitfield<8> fix; // Fixed-Range Registers 610 Bitfield<10> wc; // Write-Combining 611 EndBitUnion(MTRRcap) 612 613 /** 614 * SYSENTER configuration registers 615 */ 616 BitUnion64(SysenterCS) 617 Bitfield<15, 0> targetCS; 618 EndBitUnion(SysenterCS) 619 620 BitUnion64(SysenterESP) 621 Bitfield<31, 0> targetESP; 622 EndBitUnion(SysenterESP) 623 624 BitUnion64(SysenterEIP) 625 Bitfield<31, 0> targetEIP; 626 EndBitUnion(SysenterEIP) 627 628 /** 629 * Global machine check registers 630 */ 631 BitUnion64(McgCap) 632 Bitfield<7, 0> count; // Number of error reporting register banks 633 Bitfield<8> MCGCP; // MCG_CTL register present. 634 EndBitUnion(McgCap) 635 636 BitUnion64(McgStatus) 637 Bitfield<0> ripv; // Restart-IP valid 638 Bitfield<1> eipv; // Error-IP valid 639 Bitfield<2> mcip; // Machine check in-progress 640 EndBitUnion(McgStatus) 641 642 BitUnion64(DebugCtlMsr) 643 Bitfield<0> lbr; // Last-branch record 644 Bitfield<1> btf; // Branch single step 645 Bitfield<2> pb0; // Performance monitoring pin control 0 646 Bitfield<3> pb1; // Performance monitoring pin control 1 647 Bitfield<4> pb2; // Performance monitoring pin control 2 648 Bitfield<5> pb3; // Performance monitoring pin control 3 649 /*uint64_t pb(int index) 650 { 651 return bits(__data, index + 2); 652 }*/ 653 EndBitUnion(DebugCtlMsr) 654 655 BitUnion64(MtrrPhysBase) 656 Bitfield<7, 0> type; // Default memory type 657 Bitfield<51, 12> physbase; // Range physical base address 658 EndBitUnion(MtrrPhysBase) 659 660 BitUnion64(MtrrPhysMask) 661 Bitfield<11> valid; // MTRR pair enable 662 Bitfield<51, 12> physmask; // Range physical mask 663 EndBitUnion(MtrrPhysMask) 664 665 BitUnion64(MtrrFixed) 666 /*uint64_t type(int index) 667 { 668 return bits(__data, index * 8 + 7, index * 8); 669 }*/ 670 EndBitUnion(MtrrFixed) 671 672 BitUnion64(Pat) 673 /*uint64_t pa(int index) 674 { 675 return bits(__data, index * 8 + 2, index * 8); 676 }*/ 677 EndBitUnion(Pat) 678 679 BitUnion64(MtrrDefType) 680 Bitfield<7, 0> type; // Default type 681 Bitfield<10> fe; // Fixed range enable 682 Bitfield<11> e; // MTRR enable 683 EndBitUnion(MtrrDefType) 684 685 /** 686 * Machine check 687 */ 688 BitUnion64(McStatus) 689 Bitfield<15,0> mcaErrorCode; 690 Bitfield<31,16> modelSpecificCode; 691 Bitfield<56,32> otherInfo; 692 Bitfield<57> pcc; // Processor-context corrupt 693 Bitfield<58> addrv; // Error-address register valid 694 Bitfield<59> miscv; // Miscellaneous-error register valid 695 Bitfield<60> en; // Error condition enabled 696 Bitfield<61> uc; // Uncorrected error 697 Bitfield<62> over; // Status register overflow 698 Bitfield<63> val; // Valid 699 EndBitUnion(McStatus) 700 701 BitUnion64(McCtl) 702 /*uint64_t en(int index) 703 { 704 return bits(__data, index); 705 }*/ 706 EndBitUnion(McCtl) 707 708 // Extended feature enable register 709 BitUnion64(Efer) 710 Bitfield<0> sce; // System call extensions 711 Bitfield<8> lme; // Long mode enable 712 Bitfield<10> lma; // Long mode active 713 Bitfield<11> nxe; // No-execute enable 714 Bitfield<12> svme; // Secure virtual machine enable 715 Bitfield<14> ffxsr; // Fast fxsave/fxrstor 716 EndBitUnion(Efer) 717 718 BitUnion64(Star) 719 Bitfield<31,0> targetEip; 720 Bitfield<47,32> syscallCsAndSs; 721 Bitfield<63,48> sysretCsAndSs; 722 EndBitUnion(Star) 723 724 BitUnion64(SfMask) 725 Bitfield<31,0> mask; 726 EndBitUnion(SfMask) 727 728 BitUnion64(PerfEvtSel) 729 Bitfield<7,0> eventMask; 730 Bitfield<15,8> unitMask; 731 Bitfield<16> usr; // User mode 732 Bitfield<17> os; // Operating-system mode 733 Bitfield<18> e; // Edge detect 734 Bitfield<19> pc; // Pin control 735 Bitfield<20> intEn; // Interrupt enable 736 Bitfield<22> en; // Counter enable 737 Bitfield<23> inv; // Invert mask 738 Bitfield<31,24> counterMask; 739 EndBitUnion(PerfEvtSel) 740 741 BitUnion32(Syscfg) 742 Bitfield<18> mfde; // MtrrFixDramEn 743 Bitfield<19> mfdm; // MtrrFixDramModEn 744 Bitfield<20> mvdm; // MtrrVarDramEn 745 Bitfield<21> tom2; // MtrrTom2En 746 EndBitUnion(Syscfg) 747 748 BitUnion64(IorrBase) 749 Bitfield<3> wr; // WrMem Enable 750 Bitfield<4> rd; // RdMem Enable 751 Bitfield<51,12> physbase; // Range physical base address 752 EndBitUnion(IorrBase) 753 754 BitUnion64(IorrMask) 755 Bitfield<11> v; // I/O register pair enable (valid) 756 Bitfield<51,12> physmask; // Range physical mask 757 EndBitUnion(IorrMask) 758 759 BitUnion64(Tom) 760 Bitfield<51,23> physAddr; // Top of memory physical address 761 EndBitUnion(Tom) 762 763 BitUnion64(VmCrMsr) 764 Bitfield<0> dpd; 765 Bitfield<1> rInit; 766 Bitfield<2> disA20M; 767 EndBitUnion(VmCrMsr) 768 769 BitUnion64(IgnneMsr) 770 Bitfield<0> ignne; 771 EndBitUnion(IgnneMsr) 772 773 BitUnion64(SmmCtlMsr) 774 Bitfield<0> dismiss; 775 Bitfield<1> enter; 776 Bitfield<2> smiCycle; 777 Bitfield<3> exit; 778 Bitfield<4> rsmCycle; 779 EndBitUnion(SmmCtlMsr) 780 781 /** 782 * Segment Selector 783 */ 784 BitUnion64(SegSelector) 785 // The following bitfield is not defined in the ISA, but it's useful 786 // when checking selectors in larger data types to make sure they 787 // aren't too large. 788 Bitfield<63, 3> esi; // Extended selector 789 Bitfield<15, 3> si; // Selector Index 790 Bitfield<2> ti; // Table Indicator 791 Bitfield<1, 0> rpl; // Requestor Privilege Level 792 EndBitUnion(SegSelector) 793 794 /** 795 * Segment Descriptors 796 */ 797 798 BitUnion64(SegDescriptor) 799 Bitfield<63, 56> baseHigh; 800 Bitfield<39, 16> baseLow; 801 Bitfield<55> g; // Granularity 802 Bitfield<54> d; // Default Operand Size 803 Bitfield<54> b; // Default Operand Size 804 Bitfield<53> l; // Long Attribute Bit 805 Bitfield<52> avl; // Available To Software 806 Bitfield<51, 48> limitHigh; 807 Bitfield<15, 0> limitLow; 808 Bitfield<47> p; // Present 809 Bitfield<46, 45> dpl; // Descriptor Privilege-Level 810 Bitfield<44> s; // System 811 SubBitUnion(type, 43, 40) 812 // Specifies whether this descriptor is for code or data. 813 Bitfield<43> codeOrData; 814 815 // These bit fields are for code segments 816 Bitfield<42> c; // Conforming 817 Bitfield<41> r; // Readable 818 819 // These bit fields are for data segments 820 Bitfield<42> e; // Expand-Down 821 Bitfield<41> w; // Writable 822 823 // This is used for both code and data segments. 824 Bitfield<40> a; // Accessed 825 EndSubBitUnion(type) 826 EndBitUnion(SegDescriptor) 827 828 BitUnion64(SegAttr) 829 Bitfield<0> writable; 830 Bitfield<1> readable; 831 Bitfield<2> expandDown; 832 Bitfield<4, 3> dpl; 833 Bitfield<5> defaultSize; 834 Bitfield<6> longMode; 835 EndBitUnion(SegAttr) 836 837 BitUnion64(GateDescriptor) 838 Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset 839 Bitfield<15, 0> offsetLow; // Target Code-Segment Offset 840 Bitfield<31, 16> selector; // Target Code-Segment Selector 841 Bitfield<47> p; // Present 842 Bitfield<46, 45> dpl; // Descriptor Privilege-Level 843 Bitfield<43, 40> type; 844 Bitfield<36, 32> count; // Parameter Count 845 EndBitUnion(GateDescriptor) 846 847 /** 848 * Descriptor-Table Registers 849 */ 850 BitUnion64(GDTR) 851 EndBitUnion(GDTR) 852 853 BitUnion64(IDTR) 854 EndBitUnion(IDTR) 855 856 BitUnion64(LDTR) 857 EndBitUnion(LDTR) 858 859 /** 860 * Task Register 861 */ 862 BitUnion64(TR) 863 EndBitUnion(TR) 864 865 866 /** 867 * Local APIC Base Register 868 */ 869 BitUnion64(LocalApicBase) 870 Bitfield<51, 12> base; 871 Bitfield<11> enable; 872 Bitfield<8> bsp; 873 EndBitUnion(LocalApicBase) 874}; 875 876#endif // __ARCH_X86_INTREGS_HH__ 877