misc.hh revision 7629
14684SN/A/* 25419SN/A * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 34684SN/A * All rights reserved. 44684SN/A * 57087SN/A * The license below extends only to copyright in the software and shall 67087SN/A * not be construed as granting a license to any other intellectual 77087SN/A * property including but not limited to intellectual property relating 87087SN/A * to a hardware implementation of the functionality of the software 97087SN/A * licensed hereunder. You may use the software subject to the license 107087SN/A * terms below provided that you ensure that this notice is replicated 117087SN/A * unmodified and in its entirety in all distributions of the software, 127087SN/A * modified or unmodified, in source code or in binary form. 134684SN/A * 147087SN/A * Redistribution and use in source and binary forms, with or without 157087SN/A * modification, are permitted provided that the following conditions are 167087SN/A * met: redistributions of source code must retain the above copyright 177087SN/A * notice, this list of conditions and the following disclaimer; 187087SN/A * redistributions in binary form must reproduce the above copyright 197087SN/A * notice, this list of conditions and the following disclaimer in the 207087SN/A * documentation and/or other materials provided with the distribution; 217087SN/A * neither the name of the copyright holders nor the names of its 224684SN/A * contributors may be used to endorse or promote products derived from 237087SN/A * this software without specific prior written permission. 244684SN/A * 254684SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 264684SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 274684SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 284684SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 294684SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 304684SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 314684SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 324684SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 334684SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 344684SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 354684SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 364684SN/A * 374684SN/A * Authors: Gabe Black 384684SN/A */ 394684SN/A 404684SN/A#ifndef __ARCH_X86_MISCREGS_HH__ 414684SN/A#define __ARCH_X86_MISCREGS_HH__ 424684SN/A 437629Sgblack@eecs.umich.edu#include "arch/x86/regs/segment.hh" 445025SN/A#include "arch/x86/x86_traits.hh" 454684SN/A#include "base/bitunion.hh" 464684SN/A 475086SN/A//These get defined in some system headers (at least termbits.h). That confuses 485086SN/A//things here significantly. 495086SN/A#undef CR0 505086SN/A#undef CR2 515086SN/A#undef CR3 525086SN/A 534684SN/Anamespace X86ISA 544684SN/A{ 554684SN/A enum CondFlagBit { 564684SN/A CFBit = 1 << 0, 574684SN/A PFBit = 1 << 2, 584684SN/A ECFBit = 1 << 3, 594684SN/A AFBit = 1 << 4, 604684SN/A EZFBit = 1 << 5, 614684SN/A ZFBit = 1 << 6, 624684SN/A SFBit = 1 << 7, 634868SN/A DFBit = 1 << 10, 644684SN/A OFBit = 1 << 11 654684SN/A }; 664684SN/A 675426SN/A enum RFLAGBit { 685426SN/A TFBit = 1 << 8, 695426SN/A IFBit = 1 << 9, 705426SN/A NTBit = 1 << 14, 715426SN/A RFBit = 1 << 16, 725426SN/A VMBit = 1 << 17, 735426SN/A ACBit = 1 << 18, 745426SN/A VIFBit = 1 << 19, 755426SN/A VIPBit = 1 << 20, 765426SN/A IDBit = 1 << 21 775426SN/A }; 785426SN/A 794700SN/A enum MiscRegIndex 804700SN/A { 814700SN/A // Control registers 824700SN/A // Most of these are invalid. 834862SN/A MISCREG_CR_BASE, 844862SN/A MISCREG_CR0 = MISCREG_CR_BASE, 854700SN/A MISCREG_CR1, 864700SN/A MISCREG_CR2, 874700SN/A MISCREG_CR3, 884700SN/A MISCREG_CR4, 894700SN/A MISCREG_CR5, 904700SN/A MISCREG_CR6, 914700SN/A MISCREG_CR7, 924700SN/A MISCREG_CR8, 934700SN/A MISCREG_CR9, 944700SN/A MISCREG_CR10, 954700SN/A MISCREG_CR11, 964700SN/A MISCREG_CR12, 974700SN/A MISCREG_CR13, 984700SN/A MISCREG_CR14, 994700SN/A MISCREG_CR15, 1004700SN/A 1014700SN/A // Debug registers 1025025SN/A MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs, 1034862SN/A MISCREG_DR0 = MISCREG_DR_BASE, 1044700SN/A MISCREG_DR1, 1054700SN/A MISCREG_DR2, 1064700SN/A MISCREG_DR3, 1074700SN/A MISCREG_DR4, 1084700SN/A MISCREG_DR5, 1094700SN/A MISCREG_DR6, 1104700SN/A MISCREG_DR7, 1114700SN/A 1124700SN/A // Flags register 1135025SN/A MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs, 1144700SN/A 1155429SN/A //Register to keep handy values like the CPU mode in. 1165429SN/A MISCREG_M5_REG, 1175429SN/A 1185138SN/A /* 1195138SN/A * Model Specific Registers 1205138SN/A */ 1215138SN/A // Time stamp counter 1225138SN/A MISCREG_TSC, 1235138SN/A 1245138SN/A MISCREG_MTRRCAP, 1255138SN/A 1265138SN/A MISCREG_SYSENTER_CS, 1275138SN/A MISCREG_SYSENTER_ESP, 1285138SN/A MISCREG_SYSENTER_EIP, 1295138SN/A 1305138SN/A MISCREG_MCG_CAP, 1315138SN/A MISCREG_MCG_STATUS, 1325138SN/A MISCREG_MCG_CTL, 1335138SN/A 1345138SN/A MISCREG_DEBUG_CTL_MSR, 1355138SN/A 1365138SN/A MISCREG_LAST_BRANCH_FROM_IP, 1375138SN/A MISCREG_LAST_BRANCH_TO_IP, 1385138SN/A MISCREG_LAST_EXCEPTION_FROM_IP, 1395138SN/A MISCREG_LAST_EXCEPTION_TO_IP, 1405138SN/A 1415138SN/A MISCREG_MTRR_PHYS_BASE_BASE, 1425138SN/A MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE, 1435138SN/A MISCREG_MTRR_PHYS_BASE_1, 1445138SN/A MISCREG_MTRR_PHYS_BASE_2, 1455138SN/A MISCREG_MTRR_PHYS_BASE_3, 1465138SN/A MISCREG_MTRR_PHYS_BASE_4, 1475138SN/A MISCREG_MTRR_PHYS_BASE_5, 1485138SN/A MISCREG_MTRR_PHYS_BASE_6, 1495138SN/A MISCREG_MTRR_PHYS_BASE_7, 1506346SN/A MISCREG_MTRR_PHYS_BASE_END, 1515138SN/A 1526346SN/A MISCREG_MTRR_PHYS_MASK_BASE = MISCREG_MTRR_PHYS_BASE_END, 1535138SN/A MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE, 1545138SN/A MISCREG_MTRR_PHYS_MASK_1, 1555138SN/A MISCREG_MTRR_PHYS_MASK_2, 1565138SN/A MISCREG_MTRR_PHYS_MASK_3, 1575138SN/A MISCREG_MTRR_PHYS_MASK_4, 1585138SN/A MISCREG_MTRR_PHYS_MASK_5, 1595138SN/A MISCREG_MTRR_PHYS_MASK_6, 1605138SN/A MISCREG_MTRR_PHYS_MASK_7, 1616346SN/A MISCREG_MTRR_PHYS_MASK_END, 1625138SN/A 1636346SN/A MISCREG_MTRR_FIX_64K_00000 = MISCREG_MTRR_PHYS_MASK_END, 1645138SN/A MISCREG_MTRR_FIX_16K_80000, 1655138SN/A MISCREG_MTRR_FIX_16K_A0000, 1665138SN/A MISCREG_MTRR_FIX_4K_C0000, 1675149SN/A MISCREG_MTRR_FIX_4K_C8000, 1685138SN/A MISCREG_MTRR_FIX_4K_D0000, 1695138SN/A MISCREG_MTRR_FIX_4K_D8000, 1705138SN/A MISCREG_MTRR_FIX_4K_E0000, 1715138SN/A MISCREG_MTRR_FIX_4K_E8000, 1725138SN/A MISCREG_MTRR_FIX_4K_F0000, 1735138SN/A MISCREG_MTRR_FIX_4K_F8000, 1745138SN/A 1755138SN/A MISCREG_PAT, 1765138SN/A 1775138SN/A MISCREG_DEF_TYPE, 1785138SN/A 1795138SN/A MISCREG_MC_CTL_BASE, 1805138SN/A MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE, 1815138SN/A MISCREG_MC1_CTL, 1825138SN/A MISCREG_MC2_CTL, 1835138SN/A MISCREG_MC3_CTL, 1845138SN/A MISCREG_MC4_CTL, 1855419SN/A MISCREG_MC5_CTL, 1865419SN/A MISCREG_MC6_CTL, 1875419SN/A MISCREG_MC7_CTL, 1886346SN/A MISCREG_MC_CTL_END, 1895138SN/A 1906346SN/A MISCREG_MC_STATUS_BASE = MISCREG_MC_CTL_END, 1915138SN/A MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE, 1925138SN/A MISCREG_MC1_STATUS, 1935138SN/A MISCREG_MC2_STATUS, 1945138SN/A MISCREG_MC3_STATUS, 1955138SN/A MISCREG_MC4_STATUS, 1965419SN/A MISCREG_MC5_STATUS, 1975419SN/A MISCREG_MC6_STATUS, 1985419SN/A MISCREG_MC7_STATUS, 1996346SN/A MISCREG_MC_STATUS_END, 2005138SN/A 2016346SN/A MISCREG_MC_ADDR_BASE = MISCREG_MC_STATUS_END, 2025138SN/A MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE, 2035138SN/A MISCREG_MC1_ADDR, 2045138SN/A MISCREG_MC2_ADDR, 2055138SN/A MISCREG_MC3_ADDR, 2065138SN/A MISCREG_MC4_ADDR, 2075419SN/A MISCREG_MC5_ADDR, 2085419SN/A MISCREG_MC6_ADDR, 2095419SN/A MISCREG_MC7_ADDR, 2106346SN/A MISCREG_MC_ADDR_END, 2115138SN/A 2126346SN/A MISCREG_MC_MISC_BASE = MISCREG_MC_ADDR_END, 2135138SN/A MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE, 2145138SN/A MISCREG_MC1_MISC, 2155138SN/A MISCREG_MC2_MISC, 2165138SN/A MISCREG_MC3_MISC, 2175138SN/A MISCREG_MC4_MISC, 2185419SN/A MISCREG_MC5_MISC, 2195419SN/A MISCREG_MC6_MISC, 2205419SN/A MISCREG_MC7_MISC, 2216346SN/A MISCREG_MC_MISC_END, 2225138SN/A 2235135SN/A // Extended feature enable register 2246346SN/A MISCREG_EFER = MISCREG_MC_MISC_END, 2255135SN/A 2265138SN/A MISCREG_STAR, 2275138SN/A MISCREG_LSTAR, 2285138SN/A MISCREG_CSTAR, 2295138SN/A 2305138SN/A MISCREG_SF_MASK, 2315138SN/A 2325138SN/A MISCREG_KERNEL_GS_BASE, 2335138SN/A 2345138SN/A MISCREG_TSC_AUX, 2355138SN/A 2365138SN/A MISCREG_PERF_EVT_SEL_BASE, 2375138SN/A MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE, 2385138SN/A MISCREG_PERF_EVT_SEL1, 2395138SN/A MISCREG_PERF_EVT_SEL2, 2405138SN/A MISCREG_PERF_EVT_SEL3, 2416346SN/A MISCREG_PERF_EVT_SEL_END, 2425138SN/A 2436346SN/A MISCREG_PERF_EVT_CTR_BASE = MISCREG_PERF_EVT_SEL_END, 2445138SN/A MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE, 2455138SN/A MISCREG_PERF_EVT_CTR1, 2465138SN/A MISCREG_PERF_EVT_CTR2, 2475138SN/A MISCREG_PERF_EVT_CTR3, 2486346SN/A MISCREG_PERF_EVT_CTR_END, 2495138SN/A 2506346SN/A MISCREG_SYSCFG = MISCREG_PERF_EVT_CTR_END, 2515138SN/A 2525138SN/A MISCREG_IORR_BASE_BASE, 2535138SN/A MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE, 2545138SN/A MISCREG_IORR_BASE1, 2556346SN/A MISCREG_IORR_BASE_END, 2565138SN/A 2576346SN/A MISCREG_IORR_MASK_BASE = MISCREG_IORR_BASE_END, 2585138SN/A MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE, 2595138SN/A MISCREG_IORR_MASK1, 2606346SN/A MISCREG_IORR_MASK_END, 2615138SN/A 2626346SN/A MISCREG_TOP_MEM = MISCREG_IORR_MASK_END, 2635138SN/A MISCREG_TOP_MEM2, 2645138SN/A 2655138SN/A MISCREG_VM_CR, 2665138SN/A MISCREG_IGNNE, 2675138SN/A MISCREG_SMM_CTL, 2685138SN/A MISCREG_VM_HSAVE_PA, 2695138SN/A 2705138SN/A /* 2715138SN/A * Segment registers 2725138SN/A */ 2734700SN/A // Segment selectors 2744862SN/A MISCREG_SEG_SEL_BASE, 2754862SN/A MISCREG_ES = MISCREG_SEG_SEL_BASE, 2764700SN/A MISCREG_CS, 2774700SN/A MISCREG_SS, 2784700SN/A MISCREG_DS, 2794700SN/A MISCREG_FS, 2804700SN/A MISCREG_GS, 2815294SN/A MISCREG_HS, 2825294SN/A MISCREG_TSL, 2835294SN/A MISCREG_TSG, 2845294SN/A MISCREG_LS, 2855294SN/A MISCREG_MS, 2865294SN/A MISCREG_TR, 2875294SN/A MISCREG_IDTR, 2884700SN/A 2894700SN/A // Hidden segment base field 2905294SN/A MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS, 2914862SN/A MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE, 2924700SN/A MISCREG_CS_BASE, 2934700SN/A MISCREG_SS_BASE, 2944700SN/A MISCREG_DS_BASE, 2954700SN/A MISCREG_FS_BASE, 2964700SN/A MISCREG_GS_BASE, 2975294SN/A MISCREG_HS_BASE, 2985294SN/A MISCREG_TSL_BASE, 2995294SN/A MISCREG_TSG_BASE, 3005294SN/A MISCREG_LS_BASE, 3015294SN/A MISCREG_MS_BASE, 3025294SN/A MISCREG_TR_BASE, 3035294SN/A MISCREG_IDTR_BASE, 3044700SN/A 3055289SN/A // The effective segment base, ie what is actually added to an 3065289SN/A // address. In 64 bit mode this can be different from the above, 3075289SN/A // namely 0. 3085294SN/A MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS, 3095289SN/A MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE, 3105289SN/A MISCREG_CS_EFF_BASE, 3115289SN/A MISCREG_SS_EFF_BASE, 3125289SN/A MISCREG_DS_EFF_BASE, 3135289SN/A MISCREG_FS_EFF_BASE, 3145289SN/A MISCREG_GS_EFF_BASE, 3155294SN/A MISCREG_HS_EFF_BASE, 3165294SN/A MISCREG_TSL_EFF_BASE, 3175294SN/A MISCREG_TSG_EFF_BASE, 3185294SN/A MISCREG_LS_EFF_BASE, 3195294SN/A MISCREG_MS_EFF_BASE, 3205294SN/A MISCREG_TR_EFF_BASE, 3215294SN/A MISCREG_IDTR_EFF_BASE, 3225289SN/A 3234700SN/A // Hidden segment limit field 3245294SN/A MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS, 3254862SN/A MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE, 3264700SN/A MISCREG_CS_LIMIT, 3274700SN/A MISCREG_SS_LIMIT, 3284700SN/A MISCREG_DS_LIMIT, 3294700SN/A MISCREG_FS_LIMIT, 3304700SN/A MISCREG_GS_LIMIT, 3315294SN/A MISCREG_HS_LIMIT, 3325294SN/A MISCREG_TSL_LIMIT, 3335294SN/A MISCREG_TSG_LIMIT, 3345294SN/A MISCREG_LS_LIMIT, 3355294SN/A MISCREG_MS_LIMIT, 3365294SN/A MISCREG_TR_LIMIT, 3375294SN/A MISCREG_IDTR_LIMIT, 3384700SN/A 3394700SN/A // Hidden segment limit attributes 3405294SN/A MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS, 3414862SN/A MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE, 3424700SN/A MISCREG_CS_ATTR, 3434700SN/A MISCREG_SS_ATTR, 3444700SN/A MISCREG_DS_ATTR, 3454700SN/A MISCREG_FS_ATTR, 3464700SN/A MISCREG_GS_ATTR, 3475294SN/A MISCREG_HS_ATTR, 3485294SN/A MISCREG_TSL_ATTR, 3495294SN/A MISCREG_TSG_ATTR, 3505294SN/A MISCREG_LS_ATTR, 3515294SN/A MISCREG_MS_ATTR, 3524700SN/A MISCREG_TR_ATTR, 3535294SN/A MISCREG_IDTR_ATTR, 3544700SN/A 3555082SN/A // Floating point control registers 3565294SN/A MISCREG_X87_TOP = 3575294SN/A MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS, 3585082SN/A 3596362SN/A MISCREG_MXCSR, 3606362SN/A MISCREG_FCW, 3616362SN/A MISCREG_FSW, 3626362SN/A MISCREG_FTW, 3636362SN/A MISCREG_FTAG, 3646362SN/A MISCREG_FISEG, 3656362SN/A MISCREG_FIOFF, 3666362SN/A MISCREG_FOSEG, 3676362SN/A MISCREG_FOOFF, 3686362SN/A MISCREG_FOP, 3696362SN/A 3704700SN/A //XXX Add "Model-Specific Registers" 3714700SN/A 3725360SN/A MISCREG_APIC_BASE, 3735360SN/A 3745360SN/A // "Fake" MSRs for internally implemented devices 3755357SN/A MISCREG_PCI_CONFIG_ADDRESS, 3765357SN/A 3775082SN/A NUM_MISCREGS 3784700SN/A }; 3794700SN/A 3805025SN/A static inline MiscRegIndex 3815025SN/A MISCREG_CR(int index) 3825025SN/A { 3836346SN/A assert(index >= 0 && index < NumCRegs); 3845025SN/A return (MiscRegIndex)(MISCREG_CR_BASE + index); 3855025SN/A } 3865025SN/A 3875025SN/A static inline MiscRegIndex 3885025SN/A MISCREG_DR(int index) 3895025SN/A { 3906346SN/A assert(index >= 0 && index < NumDRegs); 3915025SN/A return (MiscRegIndex)(MISCREG_DR_BASE + index); 3925025SN/A } 3935025SN/A 3945025SN/A static inline MiscRegIndex 3955138SN/A MISCREG_MTRR_PHYS_BASE(int index) 3965138SN/A { 3976346SN/A assert(index >= 0 && index < (MISCREG_MTRR_PHYS_BASE_END - 3986346SN/A MISCREG_MTRR_PHYS_BASE_BASE)); 3995138SN/A return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index); 4005138SN/A } 4015138SN/A 4025138SN/A static inline MiscRegIndex 4035138SN/A MISCREG_MTRR_PHYS_MASK(int index) 4045138SN/A { 4056346SN/A assert(index >= 0 && index < (MISCREG_MTRR_PHYS_MASK_END - 4066346SN/A MISCREG_MTRR_PHYS_MASK_BASE)); 4075138SN/A return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index); 4085138SN/A } 4095138SN/A 4105138SN/A static inline MiscRegIndex 4115138SN/A MISCREG_MC_CTL(int index) 4125138SN/A { 4136346SN/A assert(index >= 0 && index < (MISCREG_MC_CTL_END - 4146346SN/A MISCREG_MC_CTL_BASE)); 4155138SN/A return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index); 4165138SN/A } 4175138SN/A 4185138SN/A static inline MiscRegIndex 4195138SN/A MISCREG_MC_STATUS(int index) 4205138SN/A { 4216346SN/A assert(index >= 0 && index < (MISCREG_MC_STATUS_END - 4226346SN/A MISCREG_MC_STATUS_BASE)); 4235138SN/A return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index); 4245138SN/A } 4255138SN/A 4265138SN/A static inline MiscRegIndex 4275138SN/A MISCREG_MC_ADDR(int index) 4285138SN/A { 4296346SN/A assert(index >= 0 && index < (MISCREG_MC_ADDR_END - 4306346SN/A MISCREG_MC_ADDR_BASE)); 4315138SN/A return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index); 4325138SN/A } 4335138SN/A 4345138SN/A static inline MiscRegIndex 4355138SN/A MISCREG_MC_MISC(int index) 4365138SN/A { 4376346SN/A assert(index >= 0 && index < (MISCREG_MC_MISC_END - 4386346SN/A MISCREG_MC_MISC_BASE)); 4395138SN/A return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index); 4405138SN/A } 4415138SN/A 4425138SN/A static inline MiscRegIndex 4435138SN/A MISCREG_PERF_EVT_SEL(int index) 4445138SN/A { 4456346SN/A assert(index >= 0 && index < (MISCREG_PERF_EVT_SEL_END - 4466346SN/A MISCREG_PERF_EVT_SEL_BASE)); 4475138SN/A return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index); 4485138SN/A } 4495138SN/A 4505138SN/A static inline MiscRegIndex 4515138SN/A MISCREG_PERF_EVT_CTR(int index) 4525138SN/A { 4536346SN/A assert(index >= 0 && index < (MISCREG_PERF_EVT_CTR_END - 4546346SN/A MISCREG_PERF_EVT_CTR_BASE)); 4555138SN/A return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index); 4565138SN/A } 4575138SN/A 4585138SN/A static inline MiscRegIndex 4595138SN/A MISCREG_IORR_BASE(int index) 4605138SN/A { 4616346SN/A assert(index >= 0 && index < (MISCREG_IORR_BASE_END - 4626346SN/A MISCREG_IORR_BASE_BASE)); 4635138SN/A return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index); 4645138SN/A } 4655138SN/A 4665138SN/A static inline MiscRegIndex 4675138SN/A MISCREG_IORR_MASK(int index) 4685138SN/A { 4696346SN/A assert(index >= 0 && index < (MISCREG_IORR_MASK_END - 4706346SN/A MISCREG_IORR_MASK_BASE)); 4715138SN/A return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index); 4725138SN/A } 4735138SN/A 4745138SN/A static inline MiscRegIndex 4755025SN/A MISCREG_SEG_SEL(int index) 4765025SN/A { 4776346SN/A assert(index >= 0 && index < NUM_SEGMENTREGS); 4785025SN/A return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index); 4795025SN/A } 4805025SN/A 4815025SN/A static inline MiscRegIndex 4825025SN/A MISCREG_SEG_BASE(int index) 4835025SN/A { 4846346SN/A assert(index >= 0 && index < NUM_SEGMENTREGS); 4855025SN/A return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index); 4865025SN/A } 4875025SN/A 4885025SN/A static inline MiscRegIndex 4895289SN/A MISCREG_SEG_EFF_BASE(int index) 4905289SN/A { 4916346SN/A assert(index >= 0 && index < NUM_SEGMENTREGS); 4925289SN/A return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index); 4935289SN/A } 4945289SN/A 4955289SN/A static inline MiscRegIndex 4965025SN/A MISCREG_SEG_LIMIT(int index) 4975025SN/A { 4986346SN/A assert(index >= 0 && index < NUM_SEGMENTREGS); 4995025SN/A return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index); 5005025SN/A } 5015025SN/A 5025025SN/A static inline MiscRegIndex 5035025SN/A MISCREG_SEG_ATTR(int index) 5045025SN/A { 5056346SN/A assert(index >= 0 && index < NUM_SEGMENTREGS); 5065025SN/A return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index); 5075025SN/A } 5085025SN/A 5094700SN/A /** 5104700SN/A * A type to describe the condition code bits of the RFLAGS register, 5114700SN/A * plus two flags, EZF and ECF, which are only visible to microcode. 5124700SN/A */ 5134684SN/A BitUnion64(CCFlagBits) 5145138SN/A Bitfield<11> of; 5155138SN/A Bitfield<7> sf; 5165138SN/A Bitfield<6> zf; 5175138SN/A Bitfield<5> ezf; 5185138SN/A Bitfield<4> af; 5195138SN/A Bitfield<3> ecf; 5205138SN/A Bitfield<2> pf; 5215138SN/A Bitfield<0> cf; 5224684SN/A EndBitUnion(CCFlagBits) 5234700SN/A 5244700SN/A /** 5254700SN/A * RFLAGS 5264700SN/A */ 5274700SN/A BitUnion64(RFLAGS) 5285138SN/A Bitfield<21> id; // ID Flag 5295138SN/A Bitfield<20> vip; // Virtual Interrupt Pending 5305138SN/A Bitfield<19> vif; // Virtual Interrupt Flag 5315138SN/A Bitfield<18> ac; // Alignment Check 5325138SN/A Bitfield<17> vm; // Virtual-8086 Mode 5335138SN/A Bitfield<16> rf; // Resume Flag 5345138SN/A Bitfield<14> nt; // Nested Task 5355138SN/A Bitfield<13, 12> iopl; // I/O Privilege Level 5365138SN/A Bitfield<11> of; // Overflow Flag 5375138SN/A Bitfield<10> df; // Direction Flag 5385138SN/A Bitfield<9> intf; // Interrupt Flag 5395138SN/A Bitfield<8> tf; // Trap Flag 5405138SN/A Bitfield<7> sf; // Sign Flag 5415138SN/A Bitfield<6> zf; // Zero Flag 5425138SN/A Bitfield<4> af; // Auxiliary Flag 5435138SN/A Bitfield<2> pf; // Parity Flag 5445138SN/A Bitfield<0> cf; // Carry Flag 5454700SN/A EndBitUnion(RFLAGS) 5464700SN/A 5475429SN/A BitUnion64(HandyM5Reg) 5485429SN/A Bitfield<0> mode; 5495429SN/A Bitfield<3, 1> submode; 5505429SN/A Bitfield<5, 4> cpl; 5516141SN/A Bitfield<6> paging; 5526141SN/A Bitfield<7> prot; 5536142SN/A Bitfield<9, 8> defOp; 5546142SN/A Bitfield<11, 10> altOp; 5556142SN/A Bitfield<13, 12> defAddr; 5566142SN/A Bitfield<15, 14> altAddr; 5576142SN/A Bitfield<17, 16> stack; 5585429SN/A EndBitUnion(HandyM5Reg) 5595429SN/A 5604700SN/A /** 5614700SN/A * Control registers 5624700SN/A */ 5634700SN/A BitUnion64(CR0) 5645138SN/A Bitfield<31> pg; // Paging 5655138SN/A Bitfield<30> cd; // Cache Disable 5665138SN/A Bitfield<29> nw; // Not Writethrough 5675138SN/A Bitfield<18> am; // Alignment Mask 5685138SN/A Bitfield<16> wp; // Write Protect 5695138SN/A Bitfield<5> ne; // Numeric Error 5705138SN/A Bitfield<4> et; // Extension Type 5715138SN/A Bitfield<3> ts; // Task Switched 5725138SN/A Bitfield<2> em; // Emulation 5735138SN/A Bitfield<1> mp; // Monitor Coprocessor 5745138SN/A Bitfield<0> pe; // Protection Enabled 5754700SN/A EndBitUnion(CR0) 5764700SN/A 5774700SN/A // Page Fault Virtual Address 5784700SN/A BitUnion64(CR2) 5794700SN/A Bitfield<31, 0> legacy; 5804700SN/A EndBitUnion(CR2) 5814700SN/A 5824700SN/A BitUnion64(CR3) 5835138SN/A Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table 5844700SN/A // Base Address 5855138SN/A Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table 5864700SN/A // Base Address 5875138SN/A Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table 5884700SN/A // Base Address 5895138SN/A Bitfield<4> pcd; // Page-Level Cache Disable 5905138SN/A Bitfield<3> pwt; // Page-Level Writethrough 5914700SN/A EndBitUnion(CR3) 5924700SN/A 5934700SN/A BitUnion64(CR4) 5945138SN/A Bitfield<10> osxmmexcpt; // Operating System Unmasked 5954700SN/A // Exception Support 5965138SN/A Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support 5975138SN/A Bitfield<8> pce; // Performance-Monitoring Counter Enable 5985138SN/A Bitfield<7> pge; // Page-Global Enable 5995138SN/A Bitfield<6> mce; // Machine Check Enable 6005138SN/A Bitfield<5> pae; // Physical-Address Extension 6015138SN/A Bitfield<4> pse; // Page Size Extensions 6025138SN/A Bitfield<3> de; // Debugging Extensions 6035138SN/A Bitfield<2> tsd; // Time Stamp Disable 6045138SN/A Bitfield<1> pvi; // Protected-Mode Virtual Interrupts 6055138SN/A Bitfield<0> vme; // Virtual-8086 Mode Extensions 6064700SN/A EndBitUnion(CR4) 6074700SN/A 6084700SN/A BitUnion64(CR8) 6095138SN/A Bitfield<3, 0> tpr; // Task Priority Register 6105138SN/A EndBitUnion(CR8) 6115138SN/A 6125925SN/A BitUnion64(DR6) 6135925SN/A Bitfield<0> b0; 6145925SN/A Bitfield<1> b1; 6155925SN/A Bitfield<2> b2; 6165925SN/A Bitfield<3> b3; 6175925SN/A Bitfield<13> bd; 6185925SN/A Bitfield<14> bs; 6195925SN/A Bitfield<15> bt; 6205925SN/A EndBitUnion(DR6) 6215925SN/A 6225925SN/A BitUnion64(DR7) 6235925SN/A Bitfield<0> l0; 6245925SN/A Bitfield<1> g0; 6255925SN/A Bitfield<2> l1; 6265925SN/A Bitfield<3> g1; 6275925SN/A Bitfield<4> l2; 6285925SN/A Bitfield<5> g2; 6295925SN/A Bitfield<6> l3; 6305925SN/A Bitfield<7> g3; 6315925SN/A Bitfield<8> le; 6325925SN/A Bitfield<9> ge; 6335925SN/A Bitfield<13> gd; 6345925SN/A Bitfield<17, 16> rw0; 6355925SN/A Bitfield<19, 18> len0; 6365925SN/A Bitfield<21, 20> rw1; 6375925SN/A Bitfield<23, 22> len1; 6385925SN/A Bitfield<25, 24> rw2; 6395925SN/A Bitfield<27, 26> len2; 6405925SN/A Bitfield<29, 28> rw3; 6415925SN/A Bitfield<31, 30> len3; 6425925SN/A EndBitUnion(DR7) 6435925SN/A 6445138SN/A // MTRR capabilities 6455138SN/A BitUnion64(MTRRcap) 6465138SN/A Bitfield<7, 0> vcnt; // Variable-Range Register Count 6475138SN/A Bitfield<8> fix; // Fixed-Range Registers 6485138SN/A Bitfield<10> wc; // Write-Combining 6495138SN/A EndBitUnion(MTRRcap) 6505138SN/A 6515138SN/A /** 6525138SN/A * SYSENTER configuration registers 6535138SN/A */ 6545138SN/A BitUnion64(SysenterCS) 6555138SN/A Bitfield<15, 0> targetCS; 6565138SN/A EndBitUnion(SysenterCS) 6575138SN/A 6585138SN/A BitUnion64(SysenterESP) 6595138SN/A Bitfield<31, 0> targetESP; 6605138SN/A EndBitUnion(SysenterESP) 6615138SN/A 6625138SN/A BitUnion64(SysenterEIP) 6635138SN/A Bitfield<31, 0> targetEIP; 6645138SN/A EndBitUnion(SysenterEIP) 6655138SN/A 6665138SN/A /** 6675138SN/A * Global machine check registers 6685138SN/A */ 6695138SN/A BitUnion64(McgCap) 6705138SN/A Bitfield<7, 0> count; // Number of error reporting register banks 6715138SN/A Bitfield<8> MCGCP; // MCG_CTL register present. 6725138SN/A EndBitUnion(McgCap) 6735138SN/A 6745138SN/A BitUnion64(McgStatus) 6755138SN/A Bitfield<0> ripv; // Restart-IP valid 6765138SN/A Bitfield<1> eipv; // Error-IP valid 6775138SN/A Bitfield<2> mcip; // Machine check in-progress 6785138SN/A EndBitUnion(McgStatus) 6795138SN/A 6805138SN/A BitUnion64(DebugCtlMsr) 6815138SN/A Bitfield<0> lbr; // Last-branch record 6825138SN/A Bitfield<1> btf; // Branch single step 6835138SN/A Bitfield<2> pb0; // Performance monitoring pin control 0 6845138SN/A Bitfield<3> pb1; // Performance monitoring pin control 1 6855138SN/A Bitfield<4> pb2; // Performance monitoring pin control 2 6865138SN/A Bitfield<5> pb3; // Performance monitoring pin control 3 6875138SN/A /*uint64_t pb(int index) 6885138SN/A { 6895138SN/A return bits(__data, index + 2); 6905138SN/A }*/ 6915138SN/A EndBitUnion(DebugCtlMsr) 6925138SN/A 6935138SN/A BitUnion64(MtrrPhysBase) 6945138SN/A Bitfield<7, 0> type; // Default memory type 6955138SN/A Bitfield<51, 12> physbase; // Range physical base address 6965138SN/A EndBitUnion(MtrrPhysBase) 6975138SN/A 6985138SN/A BitUnion64(MtrrPhysMask) 6995138SN/A Bitfield<11> valid; // MTRR pair enable 7005138SN/A Bitfield<51, 12> physmask; // Range physical mask 7015138SN/A EndBitUnion(MtrrPhysMask) 7025138SN/A 7035138SN/A BitUnion64(MtrrFixed) 7045138SN/A /*uint64_t type(int index) 7055138SN/A { 7065138SN/A return bits(__data, index * 8 + 7, index * 8); 7075138SN/A }*/ 7085138SN/A EndBitUnion(MtrrFixed) 7095138SN/A 7105138SN/A BitUnion64(Pat) 7115138SN/A /*uint64_t pa(int index) 7125138SN/A { 7135138SN/A return bits(__data, index * 8 + 2, index * 8); 7145138SN/A }*/ 7155138SN/A EndBitUnion(Pat) 7165138SN/A 7175138SN/A BitUnion64(MtrrDefType) 7185138SN/A Bitfield<7, 0> type; // Default type 7195138SN/A Bitfield<10> fe; // Fixed range enable 7205138SN/A Bitfield<11> e; // MTRR enable 7215138SN/A EndBitUnion(MtrrDefType) 7225138SN/A 7235138SN/A /** 7245138SN/A * Machine check 7255138SN/A */ 7265138SN/A BitUnion64(McStatus) 7275138SN/A Bitfield<15,0> mcaErrorCode; 7285138SN/A Bitfield<31,16> modelSpecificCode; 7295138SN/A Bitfield<56,32> otherInfo; 7305138SN/A Bitfield<57> pcc; // Processor-context corrupt 7315138SN/A Bitfield<58> addrv; // Error-address register valid 7325138SN/A Bitfield<59> miscv; // Miscellaneous-error register valid 7335138SN/A Bitfield<60> en; // Error condition enabled 7345138SN/A Bitfield<61> uc; // Uncorrected error 7355138SN/A Bitfield<62> over; // Status register overflow 7365138SN/A Bitfield<63> val; // Valid 7375138SN/A EndBitUnion(McStatus) 7385138SN/A 7395138SN/A BitUnion64(McCtl) 7405138SN/A /*uint64_t en(int index) 7415138SN/A { 7425138SN/A return bits(__data, index); 7435138SN/A }*/ 7445138SN/A EndBitUnion(McCtl) 7455138SN/A 7465138SN/A // Extended feature enable register 7475138SN/A BitUnion64(Efer) 7485138SN/A Bitfield<0> sce; // System call extensions 7495138SN/A Bitfield<8> lme; // Long mode enable 7505138SN/A Bitfield<10> lma; // Long mode active 7515138SN/A Bitfield<11> nxe; // No-execute enable 7525138SN/A Bitfield<12> svme; // Secure virtual machine enable 7535138SN/A Bitfield<14> ffxsr; // Fast fxsave/fxrstor 7545138SN/A EndBitUnion(Efer) 7555138SN/A 7565138SN/A BitUnion64(Star) 7575138SN/A Bitfield<31,0> targetEip; 7585138SN/A Bitfield<47,32> syscallCsAndSs; 7595138SN/A Bitfield<63,48> sysretCsAndSs; 7605138SN/A EndBitUnion(Star) 7615138SN/A 7625138SN/A BitUnion64(SfMask) 7635138SN/A Bitfield<31,0> mask; 7645138SN/A EndBitUnion(SfMask) 7655138SN/A 7665138SN/A BitUnion64(PerfEvtSel) 7675138SN/A Bitfield<7,0> eventMask; 7685138SN/A Bitfield<15,8> unitMask; 7695138SN/A Bitfield<16> usr; // User mode 7705138SN/A Bitfield<17> os; // Operating-system mode 7715138SN/A Bitfield<18> e; // Edge detect 7725138SN/A Bitfield<19> pc; // Pin control 7735138SN/A Bitfield<20> intEn; // Interrupt enable 7745138SN/A Bitfield<22> en; // Counter enable 7755138SN/A Bitfield<23> inv; // Invert mask 7765138SN/A Bitfield<31,24> counterMask; 7775138SN/A EndBitUnion(PerfEvtSel) 7785138SN/A 7795138SN/A BitUnion32(Syscfg) 7805138SN/A Bitfield<18> mfde; // MtrrFixDramEn 7815138SN/A Bitfield<19> mfdm; // MtrrFixDramModEn 7825138SN/A Bitfield<20> mvdm; // MtrrVarDramEn 7835138SN/A Bitfield<21> tom2; // MtrrTom2En 7845138SN/A EndBitUnion(Syscfg) 7855138SN/A 7865138SN/A BitUnion64(IorrBase) 7875138SN/A Bitfield<3> wr; // WrMem Enable 7885138SN/A Bitfield<4> rd; // RdMem Enable 7895138SN/A Bitfield<51,12> physbase; // Range physical base address 7905138SN/A EndBitUnion(IorrBase) 7915138SN/A 7925138SN/A BitUnion64(IorrMask) 7935138SN/A Bitfield<11> v; // I/O register pair enable (valid) 7945138SN/A Bitfield<51,12> physmask; // Range physical mask 7955138SN/A EndBitUnion(IorrMask) 7965138SN/A 7975138SN/A BitUnion64(Tom) 7985138SN/A Bitfield<51,23> physAddr; // Top of memory physical address 7995138SN/A EndBitUnion(Tom) 8005138SN/A 8015138SN/A BitUnion64(VmCrMsr) 8025138SN/A Bitfield<0> dpd; 8035138SN/A Bitfield<1> rInit; 8045138SN/A Bitfield<2> disA20M; 8055138SN/A EndBitUnion(VmCrMsr) 8065138SN/A 8075138SN/A BitUnion64(IgnneMsr) 8085138SN/A Bitfield<0> ignne; 8095138SN/A EndBitUnion(IgnneMsr) 8105138SN/A 8115138SN/A BitUnion64(SmmCtlMsr) 8125138SN/A Bitfield<0> dismiss; 8135138SN/A Bitfield<1> enter; 8145138SN/A Bitfield<2> smiCycle; 8155138SN/A Bitfield<3> exit; 8165138SN/A Bitfield<4> rsmCycle; 8175138SN/A EndBitUnion(SmmCtlMsr) 8184700SN/A 8194700SN/A /** 8204700SN/A * Segment Selector 8214700SN/A */ 8224700SN/A BitUnion64(SegSelector) 8235294SN/A // The following bitfield is not defined in the ISA, but it's useful 8245294SN/A // when checking selectors in larger data types to make sure they 8255294SN/A // aren't too large. 8265294SN/A Bitfield<63, 3> esi; // Extended selector 8275138SN/A Bitfield<15, 3> si; // Selector Index 8285138SN/A Bitfield<2> ti; // Table Indicator 8295138SN/A Bitfield<1, 0> rpl; // Requestor Privilege Level 8304700SN/A EndBitUnion(SegSelector) 8314700SN/A 8324700SN/A /** 8334700SN/A * Segment Descriptors 8344700SN/A */ 8354700SN/A 8364700SN/A BitUnion64(SegDescriptor) 8374700SN/A Bitfield<63, 56> baseHigh; 8384700SN/A Bitfield<39, 16> baseLow; 8395138SN/A Bitfield<55> g; // Granularity 8405138SN/A Bitfield<54> d; // Default Operand Size 8415138SN/A Bitfield<54> b; // Default Operand Size 8425138SN/A Bitfield<53> l; // Long Attribute Bit 8435138SN/A Bitfield<52> avl; // Available To Software 8444700SN/A Bitfield<51, 48> limitHigh; 8454700SN/A Bitfield<15, 0> limitLow; 8465138SN/A Bitfield<47> p; // Present 8475138SN/A Bitfield<46, 45> dpl; // Descriptor Privilege-Level 8485138SN/A Bitfield<44> s; // System 8494700SN/A SubBitUnion(type, 43, 40) 8504700SN/A // Specifies whether this descriptor is for code or data. 8514700SN/A Bitfield<43> codeOrData; 8524700SN/A 8534700SN/A // These bit fields are for code segments 8545138SN/A Bitfield<42> c; // Conforming 8555138SN/A Bitfield<41> r; // Readable 8564700SN/A 8574700SN/A // These bit fields are for data segments 8585138SN/A Bitfield<42> e; // Expand-Down 8595138SN/A Bitfield<41> w; // Writable 8604700SN/A 8614700SN/A // This is used for both code and data segments. 8625138SN/A Bitfield<40> a; // Accessed 8634700SN/A EndSubBitUnion(type) 8644700SN/A EndBitUnion(SegDescriptor) 8654700SN/A 8665138SN/A BitUnion64(SegAttr) 8676222SN/A Bitfield<1, 0> dpl; 8686222SN/A Bitfield<2> unusable; 8696222SN/A Bitfield<3> defaultSize; 8706222SN/A Bitfield<4> longMode; 8716222SN/A Bitfield<5> avl; 8726222SN/A Bitfield<6> granularity; 8736222SN/A Bitfield<7> present; 8746222SN/A Bitfield<11, 8> type; 8756222SN/A Bitfield<12> writable; 8766222SN/A Bitfield<13> readable; 8776222SN/A Bitfield<14> expandDown; 8786222SN/A Bitfield<15> system; 8795138SN/A EndBitUnion(SegAttr) 8805138SN/A 8814700SN/A BitUnion64(GateDescriptor) 8824700SN/A Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset 8834700SN/A Bitfield<15, 0> offsetLow; // Target Code-Segment Offset 8844700SN/A Bitfield<31, 16> selector; // Target Code-Segment Selector 8855138SN/A Bitfield<47> p; // Present 8865138SN/A Bitfield<46, 45> dpl; // Descriptor Privilege-Level 8874700SN/A Bitfield<43, 40> type; 8884700SN/A Bitfield<36, 32> count; // Parameter Count 8894700SN/A EndBitUnion(GateDescriptor) 8904700SN/A 8914700SN/A /** 8924700SN/A * Descriptor-Table Registers 8934700SN/A */ 8944700SN/A BitUnion64(GDTR) 8954700SN/A EndBitUnion(GDTR) 8964700SN/A 8974700SN/A BitUnion64(IDTR) 8984700SN/A EndBitUnion(IDTR) 8994700SN/A 9004700SN/A BitUnion64(LDTR) 9014700SN/A EndBitUnion(LDTR) 9024700SN/A 9034700SN/A /** 9044700SN/A * Task Register 9054700SN/A */ 9064700SN/A BitUnion64(TR) 9074700SN/A EndBitUnion(TR) 9085360SN/A 9095360SN/A 9105360SN/A /** 9115360SN/A * Local APIC Base Register 9125360SN/A */ 9135360SN/A BitUnion64(LocalApicBase) 9145360SN/A Bitfield<51, 12> base; 9155360SN/A Bitfield<11> enable; 9165360SN/A Bitfield<8> bsp; 9175360SN/A EndBitUnion(LocalApicBase) 9184684SN/A}; 9194684SN/A 9204684SN/A#endif // __ARCH_X86_INTREGS_HH__ 921