misc.hh revision 6362 
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use.  Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 *     Director of Intellectual Property Licensing
21 *     Office of Strategy and Technology
22 *     Hewlett-Packard Company
23 *     1501 Page Mill Road
24 *     Palo Alto, California  94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer.  Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
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31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission.  No right of
34 * sublicense is granted herewith.  Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses.  Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_MISCREGS_HH__
59#define __ARCH_X86_MISCREGS_HH__
60
61#include "arch/x86/segmentregs.hh"
62#include "arch/x86/x86_traits.hh"
63#include "base/bitunion.hh"
64
65//These get defined in some system headers (at least termbits.h). That confuses
66//things here significantly.
67#undef CR0
68#undef CR2
69#undef CR3
70
71namespace X86ISA
72{
73    enum CondFlagBit {
74        CFBit = 1 << 0,
75        PFBit = 1 << 2,
76        ECFBit = 1 << 3,
77        AFBit = 1 << 4,
78        EZFBit = 1 << 5,
79        ZFBit = 1 << 6,
80        SFBit = 1 << 7,
81        DFBit = 1 << 10,
82        OFBit = 1 << 11
83    };
84
85    enum RFLAGBit {
86        TFBit = 1 << 8,
87        IFBit = 1 << 9,
88        NTBit = 1 << 14,
89        RFBit = 1 << 16,
90        VMBit = 1 << 17,
91        ACBit = 1 << 18,
92        VIFBit = 1 << 19,
93        VIPBit = 1 << 20,
94        IDBit = 1 << 21
95    };
96
97    enum MiscRegIndex
98    {
99        // Control registers
100        // Most of these are invalid.
101        MISCREG_CR_BASE,
102        MISCREG_CR0 = MISCREG_CR_BASE,
103        MISCREG_CR1,
104        MISCREG_CR2,
105        MISCREG_CR3,
106        MISCREG_CR4,
107        MISCREG_CR5,
108        MISCREG_CR6,
109        MISCREG_CR7,
110        MISCREG_CR8,
111        MISCREG_CR9,
112        MISCREG_CR10,
113        MISCREG_CR11,
114        MISCREG_CR12,
115        MISCREG_CR13,
116        MISCREG_CR14,
117        MISCREG_CR15,
118
119        // Debug registers
120        MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
121        MISCREG_DR0 = MISCREG_DR_BASE,
122        MISCREG_DR1,
123        MISCREG_DR2,
124        MISCREG_DR3,
125        MISCREG_DR4,
126        MISCREG_DR5,
127        MISCREG_DR6,
128        MISCREG_DR7,
129
130        // Flags register
131        MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
132
133        //Register to keep handy values like the CPU mode in.
134        MISCREG_M5_REG,
135
136        /*
137         * Model Specific Registers
138         */
139        // Time stamp counter
140        MISCREG_TSC,
141
142        MISCREG_MTRRCAP,
143
144        MISCREG_SYSENTER_CS,
145        MISCREG_SYSENTER_ESP,
146        MISCREG_SYSENTER_EIP,
147
148        MISCREG_MCG_CAP,
149        MISCREG_MCG_STATUS,
150        MISCREG_MCG_CTL,
151
152        MISCREG_DEBUG_CTL_MSR,
153
154        MISCREG_LAST_BRANCH_FROM_IP,
155        MISCREG_LAST_BRANCH_TO_IP,
156        MISCREG_LAST_EXCEPTION_FROM_IP,
157        MISCREG_LAST_EXCEPTION_TO_IP,
158
159        MISCREG_MTRR_PHYS_BASE_BASE,
160        MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
161        MISCREG_MTRR_PHYS_BASE_1,
162        MISCREG_MTRR_PHYS_BASE_2,
163        MISCREG_MTRR_PHYS_BASE_3,
164        MISCREG_MTRR_PHYS_BASE_4,
165        MISCREG_MTRR_PHYS_BASE_5,
166        MISCREG_MTRR_PHYS_BASE_6,
167        MISCREG_MTRR_PHYS_BASE_7,
168        MISCREG_MTRR_PHYS_BASE_END,
169
170        MISCREG_MTRR_PHYS_MASK_BASE = MISCREG_MTRR_PHYS_BASE_END,
171        MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
172        MISCREG_MTRR_PHYS_MASK_1,
173        MISCREG_MTRR_PHYS_MASK_2,
174        MISCREG_MTRR_PHYS_MASK_3,
175        MISCREG_MTRR_PHYS_MASK_4,
176        MISCREG_MTRR_PHYS_MASK_5,
177        MISCREG_MTRR_PHYS_MASK_6,
178        MISCREG_MTRR_PHYS_MASK_7,
179        MISCREG_MTRR_PHYS_MASK_END,
180
181        MISCREG_MTRR_FIX_64K_00000 = MISCREG_MTRR_PHYS_MASK_END,
182        MISCREG_MTRR_FIX_16K_80000,
183        MISCREG_MTRR_FIX_16K_A0000,
184        MISCREG_MTRR_FIX_4K_C0000,
185        MISCREG_MTRR_FIX_4K_C8000,
186        MISCREG_MTRR_FIX_4K_D0000,
187        MISCREG_MTRR_FIX_4K_D8000,
188        MISCREG_MTRR_FIX_4K_E0000,
189        MISCREG_MTRR_FIX_4K_E8000,
190        MISCREG_MTRR_FIX_4K_F0000,
191        MISCREG_MTRR_FIX_4K_F8000,
192
193        MISCREG_PAT,
194
195        MISCREG_DEF_TYPE,
196
197        MISCREG_MC_CTL_BASE,
198        MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
199        MISCREG_MC1_CTL,
200        MISCREG_MC2_CTL,
201        MISCREG_MC3_CTL,
202        MISCREG_MC4_CTL,
203        MISCREG_MC5_CTL,
204        MISCREG_MC6_CTL,
205        MISCREG_MC7_CTL,
206        MISCREG_MC_CTL_END,
207
208        MISCREG_MC_STATUS_BASE = MISCREG_MC_CTL_END,
209        MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
210        MISCREG_MC1_STATUS,
211        MISCREG_MC2_STATUS,
212        MISCREG_MC3_STATUS,
213        MISCREG_MC4_STATUS,
214        MISCREG_MC5_STATUS,
215        MISCREG_MC6_STATUS,
216        MISCREG_MC7_STATUS,
217        MISCREG_MC_STATUS_END,
218
219        MISCREG_MC_ADDR_BASE = MISCREG_MC_STATUS_END,
220        MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
221        MISCREG_MC1_ADDR,
222        MISCREG_MC2_ADDR,
223        MISCREG_MC3_ADDR,
224        MISCREG_MC4_ADDR,
225        MISCREG_MC5_ADDR,
226        MISCREG_MC6_ADDR,
227        MISCREG_MC7_ADDR,
228        MISCREG_MC_ADDR_END,
229
230        MISCREG_MC_MISC_BASE = MISCREG_MC_ADDR_END,
231        MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
232        MISCREG_MC1_MISC,
233        MISCREG_MC2_MISC,
234        MISCREG_MC3_MISC,
235        MISCREG_MC4_MISC,
236        MISCREG_MC5_MISC,
237        MISCREG_MC6_MISC,
238        MISCREG_MC7_MISC,
239        MISCREG_MC_MISC_END,
240
241        // Extended feature enable register
242        MISCREG_EFER = MISCREG_MC_MISC_END,
243
244        MISCREG_STAR,
245        MISCREG_LSTAR,
246        MISCREG_CSTAR,
247
248        MISCREG_SF_MASK,
249
250        MISCREG_KERNEL_GS_BASE,
251
252        MISCREG_TSC_AUX,
253
254        MISCREG_PERF_EVT_SEL_BASE,
255        MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
256        MISCREG_PERF_EVT_SEL1,
257        MISCREG_PERF_EVT_SEL2,
258        MISCREG_PERF_EVT_SEL3,
259        MISCREG_PERF_EVT_SEL_END,
260
261        MISCREG_PERF_EVT_CTR_BASE = MISCREG_PERF_EVT_SEL_END,
262        MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
263        MISCREG_PERF_EVT_CTR1,
264        MISCREG_PERF_EVT_CTR2,
265        MISCREG_PERF_EVT_CTR3,
266        MISCREG_PERF_EVT_CTR_END,
267
268        MISCREG_SYSCFG = MISCREG_PERF_EVT_CTR_END,
269
270        MISCREG_IORR_BASE_BASE,
271        MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
272        MISCREG_IORR_BASE1,
273        MISCREG_IORR_BASE_END,
274
275        MISCREG_IORR_MASK_BASE = MISCREG_IORR_BASE_END,
276        MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
277        MISCREG_IORR_MASK1,
278        MISCREG_IORR_MASK_END,
279
280        MISCREG_TOP_MEM = MISCREG_IORR_MASK_END,
281        MISCREG_TOP_MEM2,
282
283        MISCREG_VM_CR,
284        MISCREG_IGNNE,
285        MISCREG_SMM_CTL,
286        MISCREG_VM_HSAVE_PA,
287
288        /*
289         * Segment registers
290         */
291        // Segment selectors
292        MISCREG_SEG_SEL_BASE,
293        MISCREG_ES = MISCREG_SEG_SEL_BASE,
294        MISCREG_CS,
295        MISCREG_SS,
296        MISCREG_DS,
297        MISCREG_FS,
298        MISCREG_GS,
299        MISCREG_HS,
300        MISCREG_TSL,
301        MISCREG_TSG,
302        MISCREG_LS,
303        MISCREG_MS,
304        MISCREG_TR,
305        MISCREG_IDTR,
306
307        // Hidden segment base field
308        MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS,
309        MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
310        MISCREG_CS_BASE,
311        MISCREG_SS_BASE,
312        MISCREG_DS_BASE,
313        MISCREG_FS_BASE,
314        MISCREG_GS_BASE,
315        MISCREG_HS_BASE,
316        MISCREG_TSL_BASE,
317        MISCREG_TSG_BASE,
318        MISCREG_LS_BASE,
319        MISCREG_MS_BASE,
320        MISCREG_TR_BASE,
321        MISCREG_IDTR_BASE,
322
323        // The effective segment base, ie what is actually added to an
324        // address. In 64 bit mode this can be different from the above,
325        // namely 0.
326        MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS,
327        MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE,
328        MISCREG_CS_EFF_BASE,
329        MISCREG_SS_EFF_BASE,
330        MISCREG_DS_EFF_BASE,
331        MISCREG_FS_EFF_BASE,
332        MISCREG_GS_EFF_BASE,
333        MISCREG_HS_EFF_BASE,
334        MISCREG_TSL_EFF_BASE,
335        MISCREG_TSG_EFF_BASE,
336        MISCREG_LS_EFF_BASE,
337        MISCREG_MS_EFF_BASE,
338        MISCREG_TR_EFF_BASE,
339        MISCREG_IDTR_EFF_BASE,
340
341        // Hidden segment limit field
342        MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS,
343        MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
344        MISCREG_CS_LIMIT,
345        MISCREG_SS_LIMIT,
346        MISCREG_DS_LIMIT,
347        MISCREG_FS_LIMIT,
348        MISCREG_GS_LIMIT,
349        MISCREG_HS_LIMIT,
350        MISCREG_TSL_LIMIT,
351        MISCREG_TSG_LIMIT,
352        MISCREG_LS_LIMIT,
353        MISCREG_MS_LIMIT,
354        MISCREG_TR_LIMIT,
355        MISCREG_IDTR_LIMIT,
356
357        // Hidden segment limit attributes
358        MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS,
359        MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
360        MISCREG_CS_ATTR,
361        MISCREG_SS_ATTR,
362        MISCREG_DS_ATTR,
363        MISCREG_FS_ATTR,
364        MISCREG_GS_ATTR,
365        MISCREG_HS_ATTR,
366        MISCREG_TSL_ATTR,
367        MISCREG_TSG_ATTR,
368        MISCREG_LS_ATTR,
369        MISCREG_MS_ATTR,
370        MISCREG_TR_ATTR,
371        MISCREG_IDTR_ATTR,
372
373        // Floating point control registers
374        MISCREG_X87_TOP =
375            MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS,
376
377        MISCREG_MXCSR,
378        MISCREG_FCW,
379        MISCREG_FSW,
380        MISCREG_FTW,
381        MISCREG_FTAG,
382        MISCREG_FISEG,
383        MISCREG_FIOFF,
384        MISCREG_FOSEG,
385        MISCREG_FOOFF,
386        MISCREG_FOP,
387
388        //XXX Add "Model-Specific Registers"
389
390        MISCREG_APIC_BASE,
391
392        // "Fake" MSRs for internally implemented devices
393        MISCREG_PCI_CONFIG_ADDRESS,
394
395        NUM_MISCREGS
396    };
397
398    static inline MiscRegIndex
399    MISCREG_CR(int index)
400    {
401        assert(index >= 0 && index < NumCRegs);
402        return (MiscRegIndex)(MISCREG_CR_BASE + index);
403    }
404
405    static inline MiscRegIndex
406    MISCREG_DR(int index)
407    {
408        assert(index >= 0 && index < NumDRegs);
409        return (MiscRegIndex)(MISCREG_DR_BASE + index);
410    }
411
412    static inline MiscRegIndex
413    MISCREG_MTRR_PHYS_BASE(int index)
414    {
415        assert(index >= 0 && index < (MISCREG_MTRR_PHYS_BASE_END -
416                                      MISCREG_MTRR_PHYS_BASE_BASE));
417        return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
418    }
419
420    static inline MiscRegIndex
421    MISCREG_MTRR_PHYS_MASK(int index)
422    {
423        assert(index >= 0 && index < (MISCREG_MTRR_PHYS_MASK_END -
424                                      MISCREG_MTRR_PHYS_MASK_BASE));
425        return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
426    }
427
428    static inline MiscRegIndex
429    MISCREG_MC_CTL(int index)
430    {
431        assert(index >= 0 && index < (MISCREG_MC_CTL_END -
432                                      MISCREG_MC_CTL_BASE));
433        return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
434    }
435
436    static inline MiscRegIndex
437    MISCREG_MC_STATUS(int index)
438    {
439        assert(index >= 0 && index < (MISCREG_MC_STATUS_END -
440                                      MISCREG_MC_STATUS_BASE));
441        return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
442    }
443
444    static inline MiscRegIndex
445    MISCREG_MC_ADDR(int index)
446    {
447        assert(index >= 0 && index < (MISCREG_MC_ADDR_END -
448                                      MISCREG_MC_ADDR_BASE));
449        return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
450    }
451
452    static inline MiscRegIndex
453    MISCREG_MC_MISC(int index)
454    {
455        assert(index >= 0 && index < (MISCREG_MC_MISC_END -
456                                      MISCREG_MC_MISC_BASE));
457        return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
458    }
459
460    static inline MiscRegIndex
461    MISCREG_PERF_EVT_SEL(int index)
462    {
463        assert(index >= 0 && index < (MISCREG_PERF_EVT_SEL_END -
464                                      MISCREG_PERF_EVT_SEL_BASE));
465        return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
466    }
467
468    static inline MiscRegIndex
469    MISCREG_PERF_EVT_CTR(int index)
470    {
471        assert(index >= 0 && index < (MISCREG_PERF_EVT_CTR_END -
472                                      MISCREG_PERF_EVT_CTR_BASE));
473        return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
474    }
475
476    static inline MiscRegIndex
477    MISCREG_IORR_BASE(int index)
478    {
479        assert(index >= 0 && index < (MISCREG_IORR_BASE_END -
480                                      MISCREG_IORR_BASE_BASE));
481        return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
482    }
483
484    static inline MiscRegIndex
485    MISCREG_IORR_MASK(int index)
486    {
487        assert(index >= 0 && index < (MISCREG_IORR_MASK_END -
488                                      MISCREG_IORR_MASK_BASE));
489        return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
490    }
491
492    static inline MiscRegIndex
493    MISCREG_SEG_SEL(int index)
494    {
495        assert(index >= 0 && index < NUM_SEGMENTREGS);
496        return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
497    }
498
499    static inline MiscRegIndex
500    MISCREG_SEG_BASE(int index)
501    {
502        assert(index >= 0 && index < NUM_SEGMENTREGS);
503        return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
504    }
505
506    static inline MiscRegIndex
507    MISCREG_SEG_EFF_BASE(int index)
508    {
509        assert(index >= 0 && index < NUM_SEGMENTREGS);
510        return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
511    }
512
513    static inline MiscRegIndex
514    MISCREG_SEG_LIMIT(int index)
515    {
516        assert(index >= 0 && index < NUM_SEGMENTREGS);
517        return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
518    }
519
520    static inline MiscRegIndex
521    MISCREG_SEG_ATTR(int index)
522    {
523        assert(index >= 0 && index < NUM_SEGMENTREGS);
524        return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
525    }
526
527    /**
528     * A type to describe the condition code bits of the RFLAGS register,
529     * plus two flags, EZF and ECF, which are only visible to microcode.
530     */
531    BitUnion64(CCFlagBits)
532        Bitfield<11> of;
533        Bitfield<7> sf;
534        Bitfield<6> zf;
535        Bitfield<5> ezf;
536        Bitfield<4> af;
537        Bitfield<3> ecf;
538        Bitfield<2> pf;
539        Bitfield<0> cf;
540    EndBitUnion(CCFlagBits)
541
542    /**
543     * RFLAGS
544     */
545    BitUnion64(RFLAGS)
546        Bitfield<21> id; // ID Flag
547        Bitfield<20> vip; // Virtual Interrupt Pending
548        Bitfield<19> vif; // Virtual Interrupt Flag
549        Bitfield<18> ac; // Alignment Check
550        Bitfield<17> vm; // Virtual-8086 Mode
551        Bitfield<16> rf; // Resume Flag
552        Bitfield<14> nt; // Nested Task
553        Bitfield<13, 12> iopl; // I/O Privilege Level
554        Bitfield<11> of; // Overflow Flag
555        Bitfield<10> df; // Direction Flag
556        Bitfield<9> intf; // Interrupt Flag
557        Bitfield<8> tf; // Trap Flag
558        Bitfield<7> sf; // Sign Flag
559        Bitfield<6> zf; // Zero Flag
560        Bitfield<4> af; // Auxiliary Flag
561        Bitfield<2> pf; // Parity Flag
562        Bitfield<0> cf; // Carry Flag
563    EndBitUnion(RFLAGS)
564
565    BitUnion64(HandyM5Reg)
566        Bitfield<0> mode;
567        Bitfield<3, 1> submode;
568        Bitfield<5, 4> cpl;
569        Bitfield<6> paging;
570        Bitfield<7> prot;
571        Bitfield<9, 8> defOp;
572        Bitfield<11, 10> altOp;
573        Bitfield<13, 12> defAddr;
574        Bitfield<15, 14> altAddr;
575        Bitfield<17, 16> stack;
576    EndBitUnion(HandyM5Reg)
577
578    /**
579     * Control registers
580     */
581    BitUnion64(CR0)
582        Bitfield<31> pg; // Paging
583        Bitfield<30> cd; // Cache Disable
584        Bitfield<29> nw; // Not Writethrough
585        Bitfield<18> am; // Alignment Mask
586        Bitfield<16> wp; // Write Protect
587        Bitfield<5> ne; // Numeric Error
588        Bitfield<4> et; // Extension Type
589        Bitfield<3> ts; // Task Switched
590        Bitfield<2> em; // Emulation
591        Bitfield<1> mp; // Monitor Coprocessor
592        Bitfield<0> pe; // Protection Enabled
593    EndBitUnion(CR0)
594
595    // Page Fault Virtual Address
596    BitUnion64(CR2)
597        Bitfield<31, 0> legacy;
598    EndBitUnion(CR2)
599
600    BitUnion64(CR3)
601        Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
602                                   // Base Address
603        Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
604                               // Base Address
605        Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
606                                 // Base Address
607        Bitfield<4> pcd; // Page-Level Cache Disable
608        Bitfield<3> pwt; // Page-Level Writethrough
609    EndBitUnion(CR3)
610
611    BitUnion64(CR4)
612        Bitfield<10> osxmmexcpt; // Operating System Unmasked
613                                 // Exception Support
614        Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
615        Bitfield<8> pce; // Performance-Monitoring Counter Enable
616        Bitfield<7> pge; // Page-Global Enable
617        Bitfield<6> mce; // Machine Check Enable
618        Bitfield<5> pae; // Physical-Address Extension
619        Bitfield<4> pse; // Page Size Extensions
620        Bitfield<3> de; // Debugging Extensions
621        Bitfield<2> tsd; // Time Stamp Disable
622        Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
623        Bitfield<0> vme; // Virtual-8086 Mode Extensions
624    EndBitUnion(CR4)
625
626    BitUnion64(CR8)
627        Bitfield<3, 0> tpr; // Task Priority Register
628    EndBitUnion(CR8)
629
630    BitUnion64(DR6)
631        Bitfield<0> b0;
632        Bitfield<1> b1;
633        Bitfield<2> b2;
634        Bitfield<3> b3;
635        Bitfield<13> bd;
636        Bitfield<14> bs;
637        Bitfield<15> bt;
638    EndBitUnion(DR6)
639
640    BitUnion64(DR7)
641        Bitfield<0> l0;
642        Bitfield<1> g0;
643        Bitfield<2> l1;
644        Bitfield<3> g1;
645        Bitfield<4> l2;
646        Bitfield<5> g2;
647        Bitfield<6> l3;
648        Bitfield<7> g3;
649        Bitfield<8> le;
650        Bitfield<9> ge;
651        Bitfield<13> gd;
652        Bitfield<17, 16> rw0;
653        Bitfield<19, 18> len0;
654        Bitfield<21, 20> rw1;
655        Bitfield<23, 22> len1;
656        Bitfield<25, 24> rw2;
657        Bitfield<27, 26> len2;
658        Bitfield<29, 28> rw3;
659        Bitfield<31, 30> len3;
660    EndBitUnion(DR7)
661
662    // MTRR capabilities
663    BitUnion64(MTRRcap)
664        Bitfield<7, 0> vcnt; // Variable-Range Register Count
665        Bitfield<8> fix; // Fixed-Range Registers
666        Bitfield<10> wc; // Write-Combining
667    EndBitUnion(MTRRcap)
668
669    /**
670     * SYSENTER configuration registers
671     */
672    BitUnion64(SysenterCS)
673        Bitfield<15, 0> targetCS;
674    EndBitUnion(SysenterCS)
675
676    BitUnion64(SysenterESP)
677        Bitfield<31, 0> targetESP;
678    EndBitUnion(SysenterESP)
679
680    BitUnion64(SysenterEIP)
681        Bitfield<31, 0> targetEIP;
682    EndBitUnion(SysenterEIP)
683
684    /**
685     * Global machine check registers
686     */
687    BitUnion64(McgCap)
688        Bitfield<7, 0> count; // Number of error reporting register banks
689        Bitfield<8> MCGCP; // MCG_CTL register present.
690    EndBitUnion(McgCap)
691
692    BitUnion64(McgStatus)
693        Bitfield<0> ripv; // Restart-IP valid
694        Bitfield<1> eipv; // Error-IP valid
695        Bitfield<2> mcip; // Machine check in-progress
696    EndBitUnion(McgStatus)
697
698    BitUnion64(DebugCtlMsr)
699        Bitfield<0> lbr; // Last-branch record
700        Bitfield<1> btf; // Branch single step
701        Bitfield<2> pb0; // Performance monitoring pin control 0
702        Bitfield<3> pb1; // Performance monitoring pin control 1
703        Bitfield<4> pb2; // Performance monitoring pin control 2
704        Bitfield<5> pb3; // Performance monitoring pin control 3
705        /*uint64_t pb(int index)
706        {
707            return bits(__data, index + 2);
708        }*/
709    EndBitUnion(DebugCtlMsr)
710
711    BitUnion64(MtrrPhysBase)
712        Bitfield<7, 0> type; // Default memory type
713        Bitfield<51, 12> physbase; // Range physical base address
714    EndBitUnion(MtrrPhysBase)
715
716    BitUnion64(MtrrPhysMask)
717        Bitfield<11> valid; // MTRR pair enable
718        Bitfield<51, 12> physmask; // Range physical mask
719    EndBitUnion(MtrrPhysMask)
720
721    BitUnion64(MtrrFixed)
722        /*uint64_t type(int index)
723        {
724            return bits(__data, index * 8 + 7, index * 8);
725        }*/
726    EndBitUnion(MtrrFixed)
727
728    BitUnion64(Pat)
729        /*uint64_t pa(int index)
730        {
731            return bits(__data, index * 8 + 2, index * 8);
732        }*/
733    EndBitUnion(Pat)
734
735    BitUnion64(MtrrDefType)
736        Bitfield<7, 0> type; // Default type
737        Bitfield<10> fe; // Fixed range enable
738        Bitfield<11> e; // MTRR enable
739    EndBitUnion(MtrrDefType)
740
741    /**
742     * Machine check
743     */
744    BitUnion64(McStatus)
745        Bitfield<15,0> mcaErrorCode;
746        Bitfield<31,16> modelSpecificCode;
747        Bitfield<56,32> otherInfo;
748        Bitfield<57> pcc; // Processor-context corrupt
749        Bitfield<58> addrv; // Error-address register valid
750        Bitfield<59> miscv; // Miscellaneous-error register valid
751        Bitfield<60> en; // Error condition enabled
752        Bitfield<61> uc; // Uncorrected error
753        Bitfield<62> over; // Status register overflow
754        Bitfield<63> val; // Valid
755    EndBitUnion(McStatus)
756
757    BitUnion64(McCtl)
758        /*uint64_t en(int index)
759        {
760            return bits(__data, index);
761        }*/
762    EndBitUnion(McCtl)
763
764    // Extended feature enable register
765    BitUnion64(Efer)
766        Bitfield<0> sce; // System call extensions
767        Bitfield<8> lme; // Long mode enable
768        Bitfield<10> lma; // Long mode active
769        Bitfield<11> nxe; // No-execute enable
770        Bitfield<12> svme; // Secure virtual machine enable
771        Bitfield<14> ffxsr; // Fast fxsave/fxrstor
772    EndBitUnion(Efer)
773
774    BitUnion64(Star)
775        Bitfield<31,0> targetEip;
776        Bitfield<47,32> syscallCsAndSs;
777        Bitfield<63,48> sysretCsAndSs;
778    EndBitUnion(Star)
779
780    BitUnion64(SfMask)
781        Bitfield<31,0> mask;
782    EndBitUnion(SfMask)
783
784    BitUnion64(PerfEvtSel)
785        Bitfield<7,0> eventMask;
786        Bitfield<15,8> unitMask;
787        Bitfield<16> usr; // User mode
788        Bitfield<17> os; // Operating-system mode
789        Bitfield<18> e; // Edge detect
790        Bitfield<19> pc; // Pin control
791        Bitfield<20> intEn; // Interrupt enable
792        Bitfield<22> en; // Counter enable
793        Bitfield<23> inv; // Invert mask
794        Bitfield<31,24> counterMask;
795    EndBitUnion(PerfEvtSel)
796
797    BitUnion32(Syscfg)
798        Bitfield<18> mfde; // MtrrFixDramEn
799        Bitfield<19> mfdm; // MtrrFixDramModEn
800        Bitfield<20> mvdm; // MtrrVarDramEn
801        Bitfield<21> tom2; // MtrrTom2En
802    EndBitUnion(Syscfg)
803
804    BitUnion64(IorrBase)
805        Bitfield<3> wr; // WrMem Enable
806        Bitfield<4> rd; // RdMem Enable
807        Bitfield<51,12> physbase; // Range physical base address
808    EndBitUnion(IorrBase)
809
810    BitUnion64(IorrMask)
811        Bitfield<11> v; // I/O register pair enable (valid)
812        Bitfield<51,12> physmask; // Range physical mask
813    EndBitUnion(IorrMask)
814
815    BitUnion64(Tom)
816        Bitfield<51,23> physAddr; // Top of memory physical address
817    EndBitUnion(Tom)
818
819    BitUnion64(VmCrMsr)
820        Bitfield<0> dpd;
821        Bitfield<1> rInit;
822        Bitfield<2> disA20M;
823    EndBitUnion(VmCrMsr)
824
825    BitUnion64(IgnneMsr)
826        Bitfield<0> ignne;
827    EndBitUnion(IgnneMsr)
828
829    BitUnion64(SmmCtlMsr)
830        Bitfield<0> dismiss;
831        Bitfield<1> enter;
832        Bitfield<2> smiCycle;
833        Bitfield<3> exit;
834        Bitfield<4> rsmCycle;
835    EndBitUnion(SmmCtlMsr)
836
837    /**
838     * Segment Selector
839     */
840    BitUnion64(SegSelector)
841        // The following bitfield is not defined in the ISA, but it's useful
842        // when checking selectors in larger data types to make sure they
843        // aren't too large.
844        Bitfield<63, 3> esi; // Extended selector
845        Bitfield<15, 3> si; // Selector Index
846        Bitfield<2> ti; // Table Indicator
847        Bitfield<1, 0> rpl; // Requestor Privilege Level
848    EndBitUnion(SegSelector)
849
850    /**
851     * Segment Descriptors
852     */
853
854    BitUnion64(SegDescriptor)
855        Bitfield<63, 56> baseHigh;
856        Bitfield<39, 16> baseLow;
857        Bitfield<55> g; // Granularity
858        Bitfield<54> d; // Default Operand Size
859        Bitfield<54> b; // Default Operand Size
860        Bitfield<53> l; // Long Attribute Bit
861        Bitfield<52> avl; // Available To Software
862        Bitfield<51, 48> limitHigh;
863        Bitfield<15, 0> limitLow;
864        Bitfield<47> p; // Present
865        Bitfield<46, 45> dpl; // Descriptor Privilege-Level
866        Bitfield<44> s; // System
867        SubBitUnion(type, 43, 40)
868            // Specifies whether this descriptor is for code or data.
869            Bitfield<43> codeOrData;
870
871            // These bit fields are for code segments
872            Bitfield<42> c; // Conforming
873            Bitfield<41> r; // Readable
874
875            // These bit fields are for data segments
876            Bitfield<42> e; // Expand-Down
877            Bitfield<41> w; // Writable
878
879            // This is used for both code and data segments.
880            Bitfield<40> a; // Accessed
881        EndSubBitUnion(type)
882    EndBitUnion(SegDescriptor)
883
884    BitUnion64(SegAttr)
885        Bitfield<1, 0> dpl;
886        Bitfield<2> unusable;
887        Bitfield<3> defaultSize;
888        Bitfield<4> longMode;
889        Bitfield<5> avl;
890        Bitfield<6> granularity;
891        Bitfield<7> present;
892        Bitfield<11, 8> type;
893        Bitfield<12> writable;
894        Bitfield<13> readable;
895        Bitfield<14> expandDown;
896        Bitfield<15> system;
897    EndBitUnion(SegAttr)
898
899    BitUnion64(GateDescriptor)
900        Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
901        Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
902        Bitfield<31, 16> selector; // Target Code-Segment Selector
903        Bitfield<47> p; // Present
904        Bitfield<46, 45> dpl; // Descriptor Privilege-Level
905        Bitfield<43, 40> type;
906        Bitfield<36, 32> count; // Parameter Count
907    EndBitUnion(GateDescriptor)
908
909    /**
910     * Descriptor-Table Registers
911     */
912    BitUnion64(GDTR)
913    EndBitUnion(GDTR)
914
915    BitUnion64(IDTR)
916    EndBitUnion(IDTR)
917
918    BitUnion64(LDTR)
919    EndBitUnion(LDTR)
920
921    /**
922     * Task Register
923     */
924    BitUnion64(TR)
925    EndBitUnion(TR)
926
927
928    /**
929     * Local APIC Base Register
930     */
931    BitUnion64(LocalApicBase)
932        Bitfield<51, 12> base;
933        Bitfield<11> enable;
934        Bitfield<8> bsp;
935    EndBitUnion(LocalApicBase)
936};
937
938#endif // __ARCH_X86_INTREGS_HH__
939