misc.hh revision 5086 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use.  Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 *     Director of Intellectual Property Licensing
21 *     Office of Strategy and Technology
22 *     Hewlett-Packard Company
23 *     1501 Page Mill Road
24 *     Palo Alto, California  94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer.  Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution.  Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission.  No right of
34 * sublicense is granted herewith.  Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses.  Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_MISCREGS_HH__
59#define __ARCH_X86_MISCREGS_HH__
60
61#include "arch/x86/x86_traits.hh"
62#include "base/bitunion.hh"
63
64//These get defined in some system headers (at least termbits.h). That confuses
65//things here significantly.
66#undef CR0
67#undef CR2
68#undef CR3
69
70namespace X86ISA
71{
72    enum CondFlagBit {
73        CFBit = 1 << 0,
74        PFBit = 1 << 2,
75        ECFBit = 1 << 3,
76        AFBit = 1 << 4,
77        EZFBit = 1 << 5,
78        ZFBit = 1 << 6,
79        SFBit = 1 << 7,
80        DFBit = 1 << 10,
81        OFBit = 1 << 11
82    };
83
84    enum MiscRegIndex
85    {
86        // Control registers
87        // Most of these are invalid.
88        MISCREG_CR_BASE,
89        MISCREG_CR0 = MISCREG_CR_BASE,
90        MISCREG_CR1,
91        MISCREG_CR2,
92        MISCREG_CR3,
93        MISCREG_CR4,
94        MISCREG_CR5,
95        MISCREG_CR6,
96        MISCREG_CR7,
97        MISCREG_CR8,
98        MISCREG_CR9,
99        MISCREG_CR10,
100        MISCREG_CR11,
101        MISCREG_CR12,
102        MISCREG_CR13,
103        MISCREG_CR14,
104        MISCREG_CR15,
105
106        // Debug registers
107        MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
108        MISCREG_DR0 = MISCREG_DR_BASE,
109        MISCREG_DR1,
110        MISCREG_DR2,
111        MISCREG_DR3,
112        MISCREG_DR4,
113        MISCREG_DR5,
114        MISCREG_DR6,
115        MISCREG_DR7,
116
117        // Flags register
118        MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
119
120        // Segment selectors
121        MISCREG_SEG_SEL_BASE,
122        MISCREG_ES = MISCREG_SEG_SEL_BASE,
123        MISCREG_CS,
124        MISCREG_SS,
125        MISCREG_DS,
126        MISCREG_FS,
127        MISCREG_GS,
128
129        // Hidden segment base field
130        MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NumSegments,
131        MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
132        MISCREG_CS_BASE,
133        MISCREG_SS_BASE,
134        MISCREG_DS_BASE,
135        MISCREG_FS_BASE,
136        MISCREG_GS_BASE,
137
138        // Hidden segment limit field
139        MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_BASE_BASE + NumSegments,
140        MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
141        MISCREG_CS_LIMIT,
142        MISCREG_SS_LIMIT,
143        MISCREG_DS_LIMIT,
144        MISCREG_FS_LIMIT,
145        MISCREG_GS_LIMIT,
146
147        // Hidden segment limit attributes
148        MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NumSegments,
149        MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
150        MISCREG_CS_ATTR,
151        MISCREG_SS_ATTR,
152        MISCREG_DS_ATTR,
153        MISCREG_FS_ATTR,
154        MISCREG_GS_ATTR,
155
156        // System segment selectors
157        MISCREG_SYSSEG_SEL_BASE = MISCREG_SEG_ATTR_BASE + NumSegments,
158        MISCREG_LDTR = MISCREG_SYSSEG_SEL_BASE,
159        MISCREG_TR,
160
161        // Hidden system segment base field
162        MISCREG_SYSSEG_BASE_BASE = MISCREG_SYSSEG_SEL_BASE + NumSysSegments,
163        MISCREG_LDTR_BASE = MISCREG_SYSSEG_BASE_BASE,
164        MISCREG_TR_BASE,
165        MISCREG_GDTR_BASE,
166        MISCREG_IDTR_BASE,
167
168        // Hidden system segment limit field
169        MISCREG_SYSSEG_LIMIT_BASE = MISCREG_SYSSEG_BASE_BASE + NumSysSegments,
170        MISCREG_LDTR_LIMIT = MISCREG_SYSSEG_LIMIT_BASE,
171        MISCREG_TR_LIMIT,
172        MISCREG_GDTR_LIMIT,
173        MISCREG_IDTR_LIMIT,
174
175        // Hidden system segment attribute field
176        MISCREG_SYSSEG_ATTR_BASE = MISCREG_SYSSEG_LIMIT_BASE + NumSysSegments,
177        MISCREG_LDTR_ATTR = MISCREG_SYSSEG_ATTR_BASE,
178        MISCREG_TR_ATTR,
179
180        // Floating point control registers
181        MISCREG_X87_TOP = MISCREG_SYSSEG_ATTR_BASE + NumSysSegments,
182
183        //XXX Add "Model-Specific Registers"
184
185        NUM_MISCREGS
186    };
187
188    static inline MiscRegIndex
189    MISCREG_CR(int index)
190    {
191        return (MiscRegIndex)(MISCREG_CR_BASE + index);
192    }
193
194    static inline MiscRegIndex
195    MISCREG_DR(int index)
196    {
197        return (MiscRegIndex)(MISCREG_DR_BASE + index);
198    }
199
200    static inline MiscRegIndex
201    MISCREG_SEG_SEL(int index)
202    {
203        return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
204    }
205
206    static inline MiscRegIndex
207    MISCREG_SEG_BASE(int index)
208    {
209        return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
210    }
211
212    static inline MiscRegIndex
213    MISCREG_SEG_LIMIT(int index)
214    {
215        return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
216    }
217
218    static inline MiscRegIndex
219    MISCREG_SEG_ATTR(int index)
220    {
221        return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
222    }
223
224    static inline MiscRegIndex
225    MISCREG_SYSSEG_SEL(int index)
226    {
227        return (MiscRegIndex)(MISCREG_SYSSEG_SEL_BASE + index);
228    }
229
230    static inline MiscRegIndex
231    MISCREG_SYSSEG_BASE(int index)
232    {
233        return (MiscRegIndex)(MISCREG_SYSSEG_BASE_BASE + index);
234    }
235
236    static inline MiscRegIndex
237    MISCREG_SYSSEG_LIMIT(int index)
238    {
239        return (MiscRegIndex)(MISCREG_SYSSEG_LIMIT_BASE + index);
240    }
241
242    static inline MiscRegIndex
243    MISCREG_SYSSEG_ATTR(int index)
244    {
245        return (MiscRegIndex)(MISCREG_SYSSEG_ATTR_BASE + index);
246    }
247
248    /**
249     * A type to describe the condition code bits of the RFLAGS register,
250     * plus two flags, EZF and ECF, which are only visible to microcode.
251     */
252    BitUnion64(CCFlagBits)
253        Bitfield<11> OF;
254        Bitfield<7> SF;
255        Bitfield<6> ZF;
256        Bitfield<5> EZF;
257        Bitfield<4> AF;
258        Bitfield<3> ECF;
259        Bitfield<2> PF;
260        Bitfield<0> CF;
261    EndBitUnion(CCFlagBits)
262
263    /**
264     * RFLAGS
265     */
266    BitUnion64(RFLAGS)
267        Bitfield<21> ID; // ID Flag
268        Bitfield<20> VIP; // Virtual Interrupt Pending
269        Bitfield<19> VIF; // Virtual Interrupt Flag
270        Bitfield<18> AC; // Alignment Check
271        Bitfield<17> VM; // Virtual-8086 Mode
272        Bitfield<16> RF; // Resume Flag
273        Bitfield<14> NT; // Nested Task
274        Bitfield<13, 12> IOPL; // I/O Privilege Level
275        Bitfield<11> OF; // Overflow Flag
276        Bitfield<10> DF; // Direction Flag
277        Bitfield<9> IF; // Interrupt Flag
278        Bitfield<8> TF; // Trap Flag
279        Bitfield<7> SF; // Sign Flag
280        Bitfield<6> ZF; // Zero Flag
281        Bitfield<4> AF; // Auxiliary Flag
282        Bitfield<2> PF; // Parity Flag
283        Bitfield<0> CF; // Carry Flag
284    EndBitUnion(RFLAGS)
285
286    /**
287     * Control registers
288     */
289    BitUnion64(CR0)
290        Bitfield<31> PG; // Paging
291        Bitfield<30> CD; // Cache Disable
292        Bitfield<29> NW; // Not Writethrough
293        Bitfield<18> AM; // Alignment Mask
294        Bitfield<16> WP; // Write Protect
295        Bitfield<5> NE; // Numeric Error
296        Bitfield<4> ET; // Extension Type
297        Bitfield<3> TS; // Task Switched
298        Bitfield<2> EM; // Emulation
299        Bitfield<1> MP; // Monitor Coprocessor
300        Bitfield<0> PE; // Protection Enabled
301    EndBitUnion(CR0)
302
303    // Page Fault Virtual Address
304    BitUnion64(CR2)
305        Bitfield<31, 0> legacy;
306    EndBitUnion(CR2)
307
308    BitUnion64(CR3)
309        Bitfield<51, 12> longPDTB; // Long Mode Page-Directory-Table
310                                   // Base Address
311        Bitfield<31, 12> PDTB; // Non-PAE Addressing Page-Directory-Table
312                               // Base Address
313        Bitfield<31, 5> PAEPDTB; // PAE Addressing Page-Directory-Table
314                                 // Base Address
315        Bitfield<4> PCD; // Page-Level Cache Disable
316        Bitfield<3> PWT; // Page-Level Writethrough
317    EndBitUnion(CR3)
318
319    BitUnion64(CR4)
320        Bitfield<10> OSXMMEXCPT; // Operating System Unmasked
321                                 // Exception Support
322        Bitfield<9> OSFXSR; // Operating System FXSave/FSRSTOR Support
323        Bitfield<8> PCE; // Performance-Monitoring Counter Enable
324        Bitfield<7> PGE; // Page-Global Enable
325        Bitfield<6> MCE; // Machine Check Enable
326        Bitfield<5> PAE; // Physical-Address Extension
327        Bitfield<4> PSE; // Page Size Extensions
328        Bitfield<3> DE; // Debugging Extensions
329        Bitfield<2> TSD; // Time Stamp Disable
330        Bitfield<1> PVI; // Protected-Mode Virtual Interrupts
331        Bitfield<0> VME; // Virtual-8086 Mode Extensions
332    EndBitUnion(CR4)
333
334    BitUnion64(CR8)
335        Bitfield<3, 0> TPR; // Task Priority Register
336    EndBitUnion(CR4)
337
338    /**
339     * Segment Selector
340     */
341    BitUnion64(SegSelector)
342        Bitfield<15, 3> SI; // Selector Index
343        Bitfield<2> TI; // Table Indicator
344        Bitfield<1, 0> RPL; // Requestor Privilege Level
345    EndBitUnion(SegSelector)
346
347    /**
348     * Segment Descriptors
349     */
350
351    BitUnion64(SegDescriptor)
352        Bitfield<63, 56> baseHigh;
353        Bitfield<39, 16> baseLow;
354        Bitfield<55> G; // Granularity
355        Bitfield<54> D; // Default Operand Size
356        Bitfield<54> B; // Default Operand Size
357        Bitfield<53> L; // Long Attribute Bit
358        Bitfield<52> AVL; // Available To Software
359        Bitfield<51, 48> limitHigh;
360        Bitfield<15, 0> limitLow;
361        Bitfield<47> P; // Present
362        Bitfield<46, 45> DPL; // Descriptor Privilege-Level
363        Bitfield<44> S; // System
364        SubBitUnion(type, 43, 40)
365            // Specifies whether this descriptor is for code or data.
366            Bitfield<43> codeOrData;
367
368            // These bit fields are for code segments
369            Bitfield<42> C; // Conforming
370            Bitfield<41> R; // Readable
371
372            // These bit fields are for data segments
373            Bitfield<42> E; // Expand-Down
374            Bitfield<41> W; // Writable
375
376            // This is used for both code and data segments.
377            Bitfield<40> A; // Accessed
378        EndSubBitUnion(type)
379    EndBitUnion(SegDescriptor)
380
381    BitUnion64(GateDescriptor)
382        Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
383        Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
384        Bitfield<31, 16> selector; // Target Code-Segment Selector
385        Bitfield<47> P; // Present
386        Bitfield<46, 45> DPL; // Descriptor Privilege-Level
387        Bitfield<43, 40> type;
388        Bitfield<36, 32> count; // Parameter Count
389    EndBitUnion(GateDescriptor)
390
391    /**
392     * Descriptor-Table Registers
393     */
394    BitUnion64(GDTR)
395    EndBitUnion(GDTR)
396
397    BitUnion64(IDTR)
398    EndBitUnion(IDTR)
399
400    BitUnion64(LDTR)
401    EndBitUnion(LDTR)
402
403    /**
404     * Task Register
405     */
406    BitUnion64(TR)
407    EndBitUnion(TR)
408};
409
410#endif // __ARCH_X86_INTREGS_HH__
411