misc.hh revision 5082 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use.  Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 *     Director of Intellectual Property Licensing
21 *     Office of Strategy and Technology
22 *     Hewlett-Packard Company
23 *     1501 Page Mill Road
24 *     Palo Alto, California  94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer.  Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution.  Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission.  No right of
34 * sublicense is granted herewith.  Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses.  Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_MISCREGS_HH__
59#define __ARCH_X86_MISCREGS_HH__
60
61#include "arch/x86/x86_traits.hh"
62#include "base/bitunion.hh"
63
64namespace X86ISA
65{
66    enum CondFlagBit {
67        CFBit = 1 << 0,
68        PFBit = 1 << 2,
69        ECFBit = 1 << 3,
70        AFBit = 1 << 4,
71        EZFBit = 1 << 5,
72        ZFBit = 1 << 6,
73        SFBit = 1 << 7,
74        DFBit = 1 << 10,
75        OFBit = 1 << 11
76    };
77
78    enum MiscRegIndex
79    {
80        // Control registers
81        // Most of these are invalid.
82        MISCREG_CR_BASE,
83        MISCREG_CR0 = MISCREG_CR_BASE,
84        MISCREG_CR1,
85        MISCREG_CR2,
86        MISCREG_CR3,
87        MISCREG_CR4,
88        MISCREG_CR5,
89        MISCREG_CR6,
90        MISCREG_CR7,
91        MISCREG_CR8,
92        MISCREG_CR9,
93        MISCREG_CR10,
94        MISCREG_CR11,
95        MISCREG_CR12,
96        MISCREG_CR13,
97        MISCREG_CR14,
98        MISCREG_CR15,
99
100        // Debug registers
101        MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
102        MISCREG_DR0 = MISCREG_DR_BASE,
103        MISCREG_DR1,
104        MISCREG_DR2,
105        MISCREG_DR3,
106        MISCREG_DR4,
107        MISCREG_DR5,
108        MISCREG_DR6,
109        MISCREG_DR7,
110
111        // Flags register
112        MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
113
114        // Segment selectors
115        MISCREG_SEG_SEL_BASE,
116        MISCREG_ES = MISCREG_SEG_SEL_BASE,
117        MISCREG_CS,
118        MISCREG_SS,
119        MISCREG_DS,
120        MISCREG_FS,
121        MISCREG_GS,
122
123        // Hidden segment base field
124        MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NumSegments,
125        MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
126        MISCREG_CS_BASE,
127        MISCREG_SS_BASE,
128        MISCREG_DS_BASE,
129        MISCREG_FS_BASE,
130        MISCREG_GS_BASE,
131
132        // Hidden segment limit field
133        MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_BASE_BASE + NumSegments,
134        MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
135        MISCREG_CS_LIMIT,
136        MISCREG_SS_LIMIT,
137        MISCREG_DS_LIMIT,
138        MISCREG_FS_LIMIT,
139        MISCREG_GS_LIMIT,
140
141        // Hidden segment limit attributes
142        MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NumSegments,
143        MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
144        MISCREG_CS_ATTR,
145        MISCREG_SS_ATTR,
146        MISCREG_DS_ATTR,
147        MISCREG_FS_ATTR,
148        MISCREG_GS_ATTR,
149
150        // System segment selectors
151        MISCREG_SYSSEG_SEL_BASE = MISCREG_SEG_ATTR_BASE + NumSegments,
152        MISCREG_LDTR = MISCREG_SYSSEG_SEL_BASE,
153        MISCREG_TR,
154
155        // Hidden system segment base field
156        MISCREG_SYSSEG_BASE_BASE = MISCREG_SYSSEG_SEL_BASE + NumSysSegments,
157        MISCREG_LDTR_BASE = MISCREG_SYSSEG_BASE_BASE,
158        MISCREG_TR_BASE,
159        MISCREG_GDTR_BASE,
160        MISCREG_IDTR_BASE,
161
162        // Hidden system segment limit field
163        MISCREG_SYSSEG_LIMIT_BASE = MISCREG_SYSSEG_BASE_BASE + NumSysSegments,
164        MISCREG_LDTR_LIMIT = MISCREG_SYSSEG_LIMIT_BASE,
165        MISCREG_TR_LIMIT,
166        MISCREG_GDTR_LIMIT,
167        MISCREG_IDTR_LIMIT,
168
169        // Hidden system segment attribute field
170        MISCREG_SYSSEG_ATTR_BASE = MISCREG_SYSSEG_LIMIT_BASE + NumSysSegments,
171        MISCREG_LDTR_ATTR = MISCREG_SYSSEG_ATTR_BASE,
172        MISCREG_TR_ATTR,
173
174        // Floating point control registers
175        MISCREG_X87_TOP = MISCREG_SYSSEG_ATTR_BASE + NumSysSegments,
176
177        //XXX Add "Model-Specific Registers"
178
179        NUM_MISCREGS
180    };
181
182    static inline MiscRegIndex
183    MISCREG_CR(int index)
184    {
185        return (MiscRegIndex)(MISCREG_CR_BASE + index);
186    }
187
188    static inline MiscRegIndex
189    MISCREG_DR(int index)
190    {
191        return (MiscRegIndex)(MISCREG_DR_BASE + index);
192    }
193
194    static inline MiscRegIndex
195    MISCREG_SEG_SEL(int index)
196    {
197        return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
198    }
199
200    static inline MiscRegIndex
201    MISCREG_SEG_BASE(int index)
202    {
203        return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
204    }
205
206    static inline MiscRegIndex
207    MISCREG_SEG_LIMIT(int index)
208    {
209        return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
210    }
211
212    static inline MiscRegIndex
213    MISCREG_SEG_ATTR(int index)
214    {
215        return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
216    }
217
218    static inline MiscRegIndex
219    MISCREG_SYSSEG_SEL(int index)
220    {
221        return (MiscRegIndex)(MISCREG_SYSSEG_SEL_BASE + index);
222    }
223
224    static inline MiscRegIndex
225    MISCREG_SYSSEG_BASE(int index)
226    {
227        return (MiscRegIndex)(MISCREG_SYSSEG_BASE_BASE + index);
228    }
229
230    static inline MiscRegIndex
231    MISCREG_SYSSEG_LIMIT(int index)
232    {
233        return (MiscRegIndex)(MISCREG_SYSSEG_LIMIT_BASE + index);
234    }
235
236    static inline MiscRegIndex
237    MISCREG_SYSSEG_ATTR(int index)
238    {
239        return (MiscRegIndex)(MISCREG_SYSSEG_ATTR_BASE + index);
240    }
241
242    /**
243     * A type to describe the condition code bits of the RFLAGS register,
244     * plus two flags, EZF and ECF, which are only visible to microcode.
245     */
246    BitUnion64(CCFlagBits)
247        Bitfield<11> OF;
248        Bitfield<7> SF;
249        Bitfield<6> ZF;
250        Bitfield<5> EZF;
251        Bitfield<4> AF;
252        Bitfield<3> ECF;
253        Bitfield<2> PF;
254        Bitfield<0> CF;
255    EndBitUnion(CCFlagBits)
256
257    /**
258     * RFLAGS
259     */
260    BitUnion64(RFLAGS)
261        Bitfield<21> ID; // ID Flag
262        Bitfield<20> VIP; // Virtual Interrupt Pending
263        Bitfield<19> VIF; // Virtual Interrupt Flag
264        Bitfield<18> AC; // Alignment Check
265        Bitfield<17> VM; // Virtual-8086 Mode
266        Bitfield<16> RF; // Resume Flag
267        Bitfield<14> NT; // Nested Task
268        Bitfield<13, 12> IOPL; // I/O Privilege Level
269        Bitfield<11> OF; // Overflow Flag
270        Bitfield<10> DF; // Direction Flag
271        Bitfield<9> IF; // Interrupt Flag
272        Bitfield<8> TF; // Trap Flag
273        Bitfield<7> SF; // Sign Flag
274        Bitfield<6> ZF; // Zero Flag
275        Bitfield<4> AF; // Auxiliary Flag
276        Bitfield<2> PF; // Parity Flag
277        Bitfield<0> CF; // Carry Flag
278    EndBitUnion(RFLAGS)
279
280    /**
281     * Control registers
282     */
283    BitUnion64(CR0)
284        Bitfield<31> PG; // Paging
285        Bitfield<30> CD; // Cache Disable
286        Bitfield<29> NW; // Not Writethrough
287        Bitfield<18> AM; // Alignment Mask
288        Bitfield<16> WP; // Write Protect
289        Bitfield<5> NE; // Numeric Error
290        Bitfield<4> ET; // Extension Type
291        Bitfield<3> TS; // Task Switched
292        Bitfield<2> EM; // Emulation
293        Bitfield<1> MP; // Monitor Coprocessor
294        Bitfield<0> PE; // Protection Enabled
295    EndBitUnion(CR0)
296
297    // Page Fault Virtual Address
298    BitUnion64(CR2)
299        Bitfield<31, 0> legacy;
300    EndBitUnion(CR2)
301
302    BitUnion64(CR3)
303        Bitfield<51, 12> longPDTB; // Long Mode Page-Directory-Table
304                                   // Base Address
305        Bitfield<31, 12> PDTB; // Non-PAE Addressing Page-Directory-Table
306                               // Base Address
307        Bitfield<31, 5> PAEPDTB; // PAE Addressing Page-Directory-Table
308                                 // Base Address
309        Bitfield<4> PCD; // Page-Level Cache Disable
310        Bitfield<3> PWT; // Page-Level Writethrough
311    EndBitUnion(CR3)
312
313    BitUnion64(CR4)
314        Bitfield<10> OSXMMEXCPT; // Operating System Unmasked
315                                 // Exception Support
316        Bitfield<9> OSFXSR; // Operating System FXSave/FSRSTOR Support
317        Bitfield<8> PCE; // Performance-Monitoring Counter Enable
318        Bitfield<7> PGE; // Page-Global Enable
319        Bitfield<6> MCE; // Machine Check Enable
320        Bitfield<5> PAE; // Physical-Address Extension
321        Bitfield<4> PSE; // Page Size Extensions
322        Bitfield<3> DE; // Debugging Extensions
323        Bitfield<2> TSD; // Time Stamp Disable
324        Bitfield<1> PVI; // Protected-Mode Virtual Interrupts
325        Bitfield<0> VME; // Virtual-8086 Mode Extensions
326    EndBitUnion(CR4)
327
328    BitUnion64(CR8)
329        Bitfield<3, 0> TPR; // Task Priority Register
330    EndBitUnion(CR4)
331
332    /**
333     * Segment Selector
334     */
335    BitUnion64(SegSelector)
336        Bitfield<15, 3> SI; // Selector Index
337        Bitfield<2> TI; // Table Indicator
338        Bitfield<1, 0> RPL; // Requestor Privilege Level
339    EndBitUnion(SegSelector)
340
341    /**
342     * Segment Descriptors
343     */
344
345    BitUnion64(SegDescriptor)
346        Bitfield<63, 56> baseHigh;
347        Bitfield<39, 16> baseLow;
348        Bitfield<55> G; // Granularity
349        Bitfield<54> D; // Default Operand Size
350        Bitfield<54> B; // Default Operand Size
351        Bitfield<53> L; // Long Attribute Bit
352        Bitfield<52> AVL; // Available To Software
353        Bitfield<51, 48> limitHigh;
354        Bitfield<15, 0> limitLow;
355        Bitfield<47> P; // Present
356        Bitfield<46, 45> DPL; // Descriptor Privilege-Level
357        Bitfield<44> S; // System
358        SubBitUnion(type, 43, 40)
359            // Specifies whether this descriptor is for code or data.
360            Bitfield<43> codeOrData;
361
362            // These bit fields are for code segments
363            Bitfield<42> C; // Conforming
364            Bitfield<41> R; // Readable
365
366            // These bit fields are for data segments
367            Bitfield<42> E; // Expand-Down
368            Bitfield<41> W; // Writable
369
370            // This is used for both code and data segments.
371            Bitfield<40> A; // Accessed
372        EndSubBitUnion(type)
373    EndBitUnion(SegDescriptor)
374
375    BitUnion64(GateDescriptor)
376        Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
377        Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
378        Bitfield<31, 16> selector; // Target Code-Segment Selector
379        Bitfield<47> P; // Present
380        Bitfield<46, 45> DPL; // Descriptor Privilege-Level
381        Bitfield<43, 40> type;
382        Bitfield<36, 32> count; // Parameter Count
383    EndBitUnion(GateDescriptor)
384
385    /**
386     * Descriptor-Table Registers
387     */
388    BitUnion64(GDTR)
389    EndBitUnion(GDTR)
390
391    BitUnion64(IDTR)
392    EndBitUnion(IDTR)
393
394    BitUnion64(LDTR)
395    EndBitUnion(LDTR)
396
397    /**
398     * Task Register
399     */
400    BitUnion64(TR)
401    EndBitUnion(TR)
402};
403
404#endif // __ARCH_X86_INTREGS_HH__
405