registers.hh revision 6329
14120SN/A/* 24120SN/A * Copyright (c) 2007 The Hewlett-Packard Development Company 34120SN/A * All rights reserved. 44120SN/A * 54120SN/A * Redistribution and use of this software in source and binary forms, 64120SN/A * with or without modification, are permitted provided that the 74120SN/A * following conditions are met: 84120SN/A * 94120SN/A * The software must be used only for Non-Commercial Use which means any 104120SN/A * use which is NOT directed to receiving any direct monetary 114120SN/A * compensation for, or commercial advantage from such use. Illustrative 124120SN/A * examples of non-commercial use are academic research, personal study, 134120SN/A * teaching, education and corporate research & development. 144120SN/A * Illustrative examples of commercial use are distributing products for 154120SN/A * commercial advantage and providing services using the software for 164120SN/A * commercial advantage. 174120SN/A * 184120SN/A * If you wish to use this software or functionality therein that may be 194120SN/A * covered by patents for commercial use, please contact: 204120SN/A * Director of Intellectual Property Licensing 214120SN/A * Office of Strategy and Technology 224120SN/A * Hewlett-Packard Company 234120SN/A * 1501 Page Mill Road 244120SN/A * Palo Alto, California 94304 254120SN/A * 264120SN/A * Redistributions of source code must retain the above copyright notice, 274120SN/A * this list of conditions and the following disclaimer. Redistributions 284120SN/A * in binary form must reproduce the above copyright notice, this list of 294120SN/A * conditions and the following disclaimer in the documentation and/or 304120SN/A * other materials provided with the distribution. Neither the name of 314120SN/A * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 324120SN/A * contributors may be used to endorse or promote products derived from 334120SN/A * this software without specific prior written permission. No right of 344120SN/A * sublicense is granted herewith. Derivatives of the software and 354120SN/A * output created using the software may be prepared, but only for 364120SN/A * Non-Commercial Uses. Derivatives of the software may be shared with 374120SN/A * others provided: (i) the others agree to abide by the list of 384120SN/A * conditions herein which includes the Non-Commercial Use restrictions; 394120SN/A * and (ii) such Derivatives of the software include the above copyright 404120SN/A * notice to acknowledge the contribution from this software where 414120SN/A * applicable, this list of conditions and the disclaimer below. 424120SN/A * 434120SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 444120SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 454120SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 464120SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 474120SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 484120SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 494120SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 504120SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 514120SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 524120SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 534120SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 544120SN/A * 554120SN/A * Authors: Gabe Black 564120SN/A */ 574120SN/A 586329Sgblack@eecs.umich.edu#ifndef __ARCH_X86_REGISTERS_HH__ 596329Sgblack@eecs.umich.edu#define __ARCH_X86_REGISTERS_HH__ 606216SN/A 616319SN/A#include "arch/x86/intregs.hh" 626329Sgblack@eecs.umich.edu#include "arch/x86/max_inst_regs.hh" 636313SN/A#include "arch/x86/miscregs.hh" 646315SN/A#include "arch/x86/x86_traits.hh" 654137SN/A 664120SN/Anamespace X86ISA 674120SN/A{ 686329Sgblack@eecs.umich.eduusing X86ISAInst::MaxInstSrcRegs; 696329Sgblack@eecs.umich.eduusing X86ISAInst::MaxInstDestRegs; 706329Sgblack@eecs.umich.educonst int NumMiscArchRegs = NUM_MISCREGS; 716329Sgblack@eecs.umich.educonst int NumMiscRegs = NUM_MISCREGS; 726313SN/A 736329Sgblack@eecs.umich.educonst int NumIntArchRegs = NUM_INTREGS; 746329Sgblack@eecs.umich.educonst int NumIntRegs = 756329Sgblack@eecs.umich.edu NumIntArchRegs + NumMicroIntRegs + 766329Sgblack@eecs.umich.edu NumPseudoIntRegs + NumImplicitIntRegs; 776319SN/A 786329Sgblack@eecs.umich.edu//Each 128 bit xmm register is broken into two effective 64 bit registers. 796329Sgblack@eecs.umich.educonst int NumFloatRegs = 806329Sgblack@eecs.umich.edu NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs; 816329Sgblack@eecs.umich.educonst int NumFloatArchRegs = NumFloatRegs + 8; 826315SN/A 836329Sgblack@eecs.umich.edu// These enumerate all the registers for dependence tracking. 846329Sgblack@eecs.umich.eduenum DependenceTags { 856329Sgblack@eecs.umich.edu //There are 16 microcode registers at the moment. This is an 866329Sgblack@eecs.umich.edu //unusually large constant to make sure there isn't overflow. 876329Sgblack@eecs.umich.edu FP_Base_DepTag = 128, 886329Sgblack@eecs.umich.edu Ctrl_Base_DepTag = 896329Sgblack@eecs.umich.edu FP_Base_DepTag + 906329Sgblack@eecs.umich.edu //mmx/x87 registers 916329Sgblack@eecs.umich.edu 8 + 926329Sgblack@eecs.umich.edu //xmm registers 936329Sgblack@eecs.umich.edu 16 * 2 + 946329Sgblack@eecs.umich.edu //The microcode fp registers 956329Sgblack@eecs.umich.edu 8 + 966329Sgblack@eecs.umich.edu //The indices that are mapped over the fp stack 976329Sgblack@eecs.umich.edu 8 986329Sgblack@eecs.umich.edu}; 994137SN/A 1006329Sgblack@eecs.umich.edu// semantically meaningful register indices 1016329Sgblack@eecs.umich.edu//There is no such register in X86 1026329Sgblack@eecs.umich.educonst int ZeroReg = NUM_INTREGS; 1036329Sgblack@eecs.umich.educonst int StackPointerReg = INTREG_RSP; 1046329Sgblack@eecs.umich.edu//X86 doesn't seem to have a link register 1056329Sgblack@eecs.umich.educonst int ReturnAddressReg = 0; 1066329Sgblack@eecs.umich.educonst int ReturnValueReg = INTREG_RAX; 1076329Sgblack@eecs.umich.educonst int FramePointerReg = INTREG_RBP; 1084137SN/A 1096329Sgblack@eecs.umich.edu// Some OS syscalls use a second register (rdx) to return a second 1106329Sgblack@eecs.umich.edu// value 1116329Sgblack@eecs.umich.educonst int SyscallPseudoReturnReg = INTREG_RDX; 1126329Sgblack@eecs.umich.edu 1136329Sgblack@eecs.umich.edutypedef uint64_t IntReg; 1146329Sgblack@eecs.umich.edu//XXX Should this be a 128 bit structure for XMM memory ops? 1156329Sgblack@eecs.umich.edutypedef uint64_t LargestRead; 1166329Sgblack@eecs.umich.edutypedef uint64_t MiscReg; 1176329Sgblack@eecs.umich.edu 1186329Sgblack@eecs.umich.edu//These floating point types are correct for mmx, but not 1196329Sgblack@eecs.umich.edu//technically for x87 (80 bits) or at all for xmm (128 bits) 1206329Sgblack@eecs.umich.edutypedef double FloatReg; 1216329Sgblack@eecs.umich.edutypedef uint64_t FloatRegBits; 1226329Sgblack@eecs.umich.edutypedef union 1236329Sgblack@eecs.umich.edu{ 1246329Sgblack@eecs.umich.edu IntReg intReg; 1256329Sgblack@eecs.umich.edu FloatReg fpReg; 1266329Sgblack@eecs.umich.edu MiscReg ctrlReg; 1276329Sgblack@eecs.umich.edu} AnyReg; 1286329Sgblack@eecs.umich.edu 1296329Sgblack@eecs.umich.edutypedef uint16_t RegIndex; 1304137SN/A 1314137SN/A}; // namespace X86ISA 1324120SN/A 1334120SN/A#endif // __ARCH_X86_REGFILE_HH__ 134