registers.hh revision 6329
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IN NO EVENT SHALL THE COPYRIGHT 47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * 55 * Authors: Gabe Black 56 */ 57 58#ifndef __ARCH_X86_REGISTERS_HH__ 59#define __ARCH_X86_REGISTERS_HH__ 60 61#include "arch/x86/intregs.hh" 62#include "arch/x86/max_inst_regs.hh" 63#include "arch/x86/miscregs.hh" 64#include "arch/x86/x86_traits.hh" 65 66namespace X86ISA 67{ 68using X86ISAInst::MaxInstSrcRegs; 69using X86ISAInst::MaxInstDestRegs; 70const int NumMiscArchRegs = NUM_MISCREGS; 71const int NumMiscRegs = NUM_MISCREGS; 72 73const int NumIntArchRegs = NUM_INTREGS; 74const int NumIntRegs = 75 NumIntArchRegs + NumMicroIntRegs + 76 NumPseudoIntRegs + NumImplicitIntRegs; 77 78//Each 128 bit xmm register is broken into two effective 64 bit registers. 79const int NumFloatRegs = 80 NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs; 81const int NumFloatArchRegs = NumFloatRegs + 8; 82 83// These enumerate all the registers for dependence tracking. 84enum DependenceTags { 85 //There are 16 microcode registers at the moment. This is an 86 //unusually large constant to make sure there isn't overflow. 87 FP_Base_DepTag = 128, 88 Ctrl_Base_DepTag = 89 FP_Base_DepTag + 90 //mmx/x87 registers 91 8 + 92 //xmm registers 93 16 * 2 + 94 //The microcode fp registers 95 8 + 96 //The indices that are mapped over the fp stack 97 8 98}; 99 100// semantically meaningful register indices 101//There is no such register in X86 102const int ZeroReg = NUM_INTREGS; 103const int StackPointerReg = INTREG_RSP; 104//X86 doesn't seem to have a link register 105const int ReturnAddressReg = 0; 106const int ReturnValueReg = INTREG_RAX; 107const int FramePointerReg = INTREG_RBP; 108 109// Some OS syscalls use a second register (rdx) to return a second 110// value 111const int SyscallPseudoReturnReg = INTREG_RDX; 112 113typedef uint64_t IntReg; 114//XXX Should this be a 128 bit structure for XMM memory ops? 115typedef uint64_t LargestRead; 116typedef uint64_t MiscReg; 117 118//These floating point types are correct for mmx, but not 119//technically for x87 (80 bits) or at all for xmm (128 bits) 120typedef double FloatReg; 121typedef uint64_t FloatRegBits; 122typedef union 123{ 124 IntReg intReg; 125 FloatReg fpReg; 126 MiscReg ctrlReg; 127} AnyReg; 128 129typedef uint16_t RegIndex; 130 131}; // namespace X86ISA 132 133#endif // __ARCH_X86_REGFILE_HH__ 134