specialize.isa revision 8250
14348Sgblack@eecs.umich.edu// -*- mode:c++ -*- 24348Sgblack@eecs.umich.edu 34348Sgblack@eecs.umich.edu// Copyright (c) 2007 The Hewlett-Packard Development Company 44348Sgblack@eecs.umich.edu// All rights reserved. 54348Sgblack@eecs.umich.edu// 67087Snate@binkert.org// The license below extends only to copyright in the software and shall 77087Snate@binkert.org// not be construed as granting a license to any other intellectual 87087Snate@binkert.org// property including but not limited to intellectual property relating 97087Snate@binkert.org// to a hardware implementation of the functionality of the software 107087Snate@binkert.org// licensed hereunder. You may use the software subject to the license 117087Snate@binkert.org// terms below provided that you ensure that this notice is replicated 127087Snate@binkert.org// unmodified and in its entirety in all distributions of the software, 137087Snate@binkert.org// modified or unmodified, in source code or in binary form. 144348Sgblack@eecs.umich.edu// 157087Snate@binkert.org// Redistribution and use in source and binary forms, with or without 167087Snate@binkert.org// modification, are permitted provided that the following conditions are 177087Snate@binkert.org// met: redistributions of source code must retain the above copyright 187087Snate@binkert.org// notice, this list of conditions and the following disclaimer; 197087Snate@binkert.org// redistributions in binary form must reproduce the above copyright 207087Snate@binkert.org// notice, this list of conditions and the following disclaimer in the 217087Snate@binkert.org// documentation and/or other materials provided with the distribution; 227087Snate@binkert.org// neither the name of the copyright holders nor the names of its 234348Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 247087Snate@binkert.org// this software without specific prior written permission. 254348Sgblack@eecs.umich.edu// 264348Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 274348Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 284348Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 294348Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 304348Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 314348Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 324348Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 334348Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 344348Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 354348Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 364348Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 374348Sgblack@eecs.umich.edu// 384348Sgblack@eecs.umich.edu// Authors: Gabe Black 394348Sgblack@eecs.umich.edu 404348Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////// 414348Sgblack@eecs.umich.edu// 424348Sgblack@eecs.umich.edu// Code to "specialize" a microcode sequence to use a particular 434348Sgblack@eecs.umich.edu// variety of operands 444348Sgblack@eecs.umich.edu// 454348Sgblack@eecs.umich.edu 464348Sgblack@eecs.umich.edulet {{ 474348Sgblack@eecs.umich.edu # This code builds up a decode block which decodes based on switchval. 484348Sgblack@eecs.umich.edu # vals is a dict which matches case values with what should be decoded to. 494609Sgblack@eecs.umich.edu # Each element of the dict is a list containing a function and then the 504609Sgblack@eecs.umich.edu # arguments to pass to it. 514609Sgblack@eecs.umich.edu def doSplitDecode(switchVal, vals, default = None): 524542Sgblack@eecs.umich.edu blocks = OutputBlocks() 534542Sgblack@eecs.umich.edu blocks.decode_block = 'switch(%s) {\n' % switchVal 544348Sgblack@eecs.umich.edu for (val, todo) in vals.items(): 554609Sgblack@eecs.umich.edu new_blocks = todo[0](*todo[1:]) 564542Sgblack@eecs.umich.edu new_blocks.decode_block = \ 574542Sgblack@eecs.umich.edu '\tcase %s: %s\n' % (val, new_blocks.decode_block) 584542Sgblack@eecs.umich.edu blocks.append(new_blocks) 594348Sgblack@eecs.umich.edu if default: 604609Sgblack@eecs.umich.edu new_blocks = default[0](*default[1:]) 614542Sgblack@eecs.umich.edu new_blocks.decode_block = \ 624542Sgblack@eecs.umich.edu '\tdefault: %s\n' % new_blocks.decode_block 634542Sgblack@eecs.umich.edu blocks.append(new_blocks) 644542Sgblack@eecs.umich.edu blocks.decode_block += '}\n' 654542Sgblack@eecs.umich.edu return blocks 664348Sgblack@eecs.umich.edu}}; 674348Sgblack@eecs.umich.edu 684348Sgblack@eecs.umich.edulet {{ 694609Sgblack@eecs.umich.edu def doRipRelativeDecode(Name, opTypes, env): 704609Sgblack@eecs.umich.edu # print "RIPing %s with opTypes %s" % (Name, opTypes) 715788Sgblack@eecs.umich.edu env.memoryInst = True 725788Sgblack@eecs.umich.edu normEnv = copy.copy(env) 735788Sgblack@eecs.umich.edu normEnv.addToDisassembly( 745788Sgblack@eecs.umich.edu '''printMem(out, env.seg, env.scale, env.index, env.base, 755788Sgblack@eecs.umich.edu machInst.displacement, env.addressSize, false);''') 765788Sgblack@eecs.umich.edu normBlocks = specializeInst(Name + "_M", copy.copy(opTypes), normEnv) 775788Sgblack@eecs.umich.edu ripEnv = copy.copy(env) 785788Sgblack@eecs.umich.edu ripEnv.addToDisassembly( 795788Sgblack@eecs.umich.edu '''printMem(out, env.seg, 1, 0, 0, 805788Sgblack@eecs.umich.edu machInst.displacement, env.addressSize, true);''') 815788Sgblack@eecs.umich.edu ripBlocks = specializeInst(Name + "_P", copy.copy(opTypes), ripEnv) 824609Sgblack@eecs.umich.edu 834609Sgblack@eecs.umich.edu blocks = OutputBlocks() 844609Sgblack@eecs.umich.edu blocks.append(normBlocks) 854609Sgblack@eecs.umich.edu blocks.append(ripBlocks) 864609Sgblack@eecs.umich.edu 874609Sgblack@eecs.umich.edu blocks.decode_block = ''' 884609Sgblack@eecs.umich.edu if(machInst.modRM.mod == 0 && 894609Sgblack@eecs.umich.edu machInst.modRM.rm == 5 && 904609Sgblack@eecs.umich.edu machInst.mode.submode == SixtyFourBitMode) 914609Sgblack@eecs.umich.edu { %s } 924609Sgblack@eecs.umich.edu else 934609Sgblack@eecs.umich.edu { %s }''' % \ 944609Sgblack@eecs.umich.edu (ripBlocks.decode_block, normBlocks.decode_block) 954609Sgblack@eecs.umich.edu return blocks 964609Sgblack@eecs.umich.edu}}; 974609Sgblack@eecs.umich.edu 984609Sgblack@eecs.umich.edulet {{ 998250Sgblack@eecs.umich.edu def doBadInstDecode(): 1008250Sgblack@eecs.umich.edu blocks = OutputBlocks() 1018250Sgblack@eecs.umich.edu blocks.decode_block = ''' 1028250Sgblack@eecs.umich.edu return new Unknown(machInst); 1038250Sgblack@eecs.umich.edu ''' 1048250Sgblack@eecs.umich.edu return blocks 1058250Sgblack@eecs.umich.edu}}; 1068250Sgblack@eecs.umich.edu 1078250Sgblack@eecs.umich.edulet {{ 1084348Sgblack@eecs.umich.edu class OpType(object): 1094601Sgblack@eecs.umich.edu parser = re.compile(r"(?P<tag>[A-Z]+)(?P<size>[a-z]*)|(r(?P<reg>[A-Z0-9]+)(?P<rsize>[a-z]*))") 1104348Sgblack@eecs.umich.edu def __init__(self, opTypeString): 1114348Sgblack@eecs.umich.edu match = OpType.parser.search(opTypeString) 1124348Sgblack@eecs.umich.edu if match == None: 1134348Sgblack@eecs.umich.edu raise Exception, "Problem parsing operand type %s" % opTypeString 1144348Sgblack@eecs.umich.edu self.reg = match.group("reg") 1154348Sgblack@eecs.umich.edu self.tag = match.group("tag") 1164348Sgblack@eecs.umich.edu self.size = match.group("size") 1174746Sgblack@eecs.umich.edu if not self.size: 1184746Sgblack@eecs.umich.edu self.size = match.group("rsize") 1194348Sgblack@eecs.umich.edu 1204548Sgblack@eecs.umich.edu ModRMRegIndex = "(MODRM_REG | (REX_R << 3))" 1214548Sgblack@eecs.umich.edu ModRMRMIndex = "(MODRM_RM | (REX_B << 3))" 1224716Sgblack@eecs.umich.edu InstRegIndex = "(OPCODE_OP_BOTTOM3 | (REX_B << 3))" 1234548Sgblack@eecs.umich.edu 1244348Sgblack@eecs.umich.edu # This function specializes the given piece of code to use a particular 1254528Sgblack@eecs.umich.edu # set of argument types described by "opTypes". 1264528Sgblack@eecs.umich.edu def specializeInst(Name, opTypes, env): 1274568Sgblack@eecs.umich.edu # print "Specializing %s with opTypes %s" % (Name, opTypes) 1284348Sgblack@eecs.umich.edu while len(opTypes): 1294528Sgblack@eecs.umich.edu # Parse the operand type string we're working with 1304542Sgblack@eecs.umich.edu opType = OpType(opTypes[0]) 1314601Sgblack@eecs.umich.edu opTypes.pop(0) 1324348Sgblack@eecs.umich.edu 1336519Sgblack@eecs.umich.edu if opType.tag not in ("I", "J", "P", "PR", "Q", "V", "VR", "W"): 1344746Sgblack@eecs.umich.edu if opType.size: 1354746Sgblack@eecs.umich.edu env.setSize(opType.size) 1364746Sgblack@eecs.umich.edu 1374348Sgblack@eecs.umich.edu if opType.reg: 1384348Sgblack@eecs.umich.edu #Figure out what to do with fixed register operands 1394528Sgblack@eecs.umich.edu #This is the index to use, so we should stick it some place. 1404542Sgblack@eecs.umich.edu if opType.reg in ("A", "B", "C", "D"): 1415788Sgblack@eecs.umich.edu regString = "INTREG_R%sX" % opType.reg 1424542Sgblack@eecs.umich.edu else: 1435788Sgblack@eecs.umich.edu regString = "INTREG_R%s" % opType.reg 1445788Sgblack@eecs.umich.edu env.addReg(regString) 1455788Sgblack@eecs.umich.edu env.addToDisassembly( 1465788Sgblack@eecs.umich.edu "printReg(out, %s, regSize);\n" % regString) 1474575Sgblack@eecs.umich.edu Name += "_R" 1484716Sgblack@eecs.umich.edu elif opType.tag == "B": 1494716Sgblack@eecs.umich.edu # This refers to registers whose index is encoded as part of the opcode 1505788Sgblack@eecs.umich.edu env.addToDisassembly( 1515788Sgblack@eecs.umich.edu "printReg(out, %s, regSize);\n" % InstRegIndex) 1524716Sgblack@eecs.umich.edu Name += "_R" 1534716Sgblack@eecs.umich.edu env.addReg(InstRegIndex) 1544601Sgblack@eecs.umich.edu elif opType.tag == "M": 1554601Sgblack@eecs.umich.edu # This refers to memory. The macroop constructor sets up modrm 1564601Sgblack@eecs.umich.edu # addressing. Non memory modrm settings should cause an error. 1574601Sgblack@eecs.umich.edu env.doModRM = True 1588250Sgblack@eecs.umich.edu return doSplitDecode("MODRM_MOD", 1598250Sgblack@eecs.umich.edu {"3" : (doBadInstDecode,) }, 1608250Sgblack@eecs.umich.edu (doRipRelativeDecode, Name, opTypes, env)) 1614348Sgblack@eecs.umich.edu elif opType.tag == None or opType.size == None: 1624348Sgblack@eecs.umich.edu raise Exception, "Problem parsing operand tag: %s" % opType.tag 1635241Sgblack@eecs.umich.edu elif opType.tag == "C": 1645294Sgblack@eecs.umich.edu # A control register indexed by the "reg" field 1655241Sgblack@eecs.umich.edu env.addReg(ModRMRegIndex) 1665788Sgblack@eecs.umich.edu env.addToDisassembly( 1675788Sgblack@eecs.umich.edu "ccprintf(out, \"CR%%d\", %s);\n" % ModRMRegIndex) 1685241Sgblack@eecs.umich.edu Name += "_C" 1695241Sgblack@eecs.umich.edu elif opType.tag == "D": 1705294Sgblack@eecs.umich.edu # A debug register indexed by the "reg" field 1715241Sgblack@eecs.umich.edu env.addReg(ModRMRegIndex) 1725788Sgblack@eecs.umich.edu env.addToDisassembly( 1735788Sgblack@eecs.umich.edu "ccprintf(out, \"DR%%d\", %s);\n" % ModRMRegIndex) 1745241Sgblack@eecs.umich.edu Name += "_D" 1755294Sgblack@eecs.umich.edu elif opType.tag == "S": 1765294Sgblack@eecs.umich.edu # A segment selector register indexed by the "reg" field 1775294Sgblack@eecs.umich.edu env.addReg(ModRMRegIndex) 1785788Sgblack@eecs.umich.edu env.addToDisassembly( 1795788Sgblack@eecs.umich.edu "printSegment(out, %s);\n" % ModRMRegIndex) 1805294Sgblack@eecs.umich.edu Name += "_S" 1815294Sgblack@eecs.umich.edu elif opType.tag in ("G", "P", "T", "V"): 1824348Sgblack@eecs.umich.edu # Use the "reg" field of the ModRM byte to select the register 1834548Sgblack@eecs.umich.edu env.addReg(ModRMRegIndex) 1845788Sgblack@eecs.umich.edu env.addToDisassembly( 1855788Sgblack@eecs.umich.edu "printReg(out, %s, regSize);\n" % ModRMRegIndex) 1866518Sgblack@eecs.umich.edu if opType.tag == "P": 1876518Sgblack@eecs.umich.edu Name += "_MMX" 1886518Sgblack@eecs.umich.edu elif opType.tag == "V": 1896518Sgblack@eecs.umich.edu Name += "_XMM" 1906518Sgblack@eecs.umich.edu else: 1916518Sgblack@eecs.umich.edu Name += "_R" 1924348Sgblack@eecs.umich.edu elif opType.tag in ("E", "Q", "W"): 1934348Sgblack@eecs.umich.edu # This might refer to memory or to a register. We need to 1944348Sgblack@eecs.umich.edu # divide it up farther. 1954528Sgblack@eecs.umich.edu regEnv = copy.copy(env) 1964548Sgblack@eecs.umich.edu regEnv.addReg(ModRMRMIndex) 1975788Sgblack@eecs.umich.edu regEnv.addToDisassembly( 1985788Sgblack@eecs.umich.edu "printReg(out, %s, regSize);\n" % ModRMRMIndex) 1994601Sgblack@eecs.umich.edu # This refers to memory. The macroop constructor should set up 2004601Sgblack@eecs.umich.edu # modrm addressing. 2014528Sgblack@eecs.umich.edu memEnv = copy.copy(env) 2024601Sgblack@eecs.umich.edu memEnv.doModRM = True 2036518Sgblack@eecs.umich.edu regSuffix = "_R" 2046518Sgblack@eecs.umich.edu if opType.tag == "Q": 2056518Sgblack@eecs.umich.edu regSuffix = "_MMX" 2066518Sgblack@eecs.umich.edu elif opType.tag == "W": 2076518Sgblack@eecs.umich.edu regSuffix = "_XMM" 2084609Sgblack@eecs.umich.edu return doSplitDecode("MODRM_MOD", 2096518Sgblack@eecs.umich.edu {"3" : (specializeInst, Name + regSuffix, 2106518Sgblack@eecs.umich.edu copy.copy(opTypes), regEnv)}, 2116518Sgblack@eecs.umich.edu (doRipRelativeDecode, Name, 2126518Sgblack@eecs.umich.edu copy.copy(opTypes), memEnv)) 2134348Sgblack@eecs.umich.edu elif opType.tag in ("I", "J"): 2144532Sgblack@eecs.umich.edu # Immediates 2155788Sgblack@eecs.umich.edu env.addToDisassembly( 2165788Sgblack@eecs.umich.edu "ccprintf(out, \"%#x\", machInst.immediate);\n") 2174575Sgblack@eecs.umich.edu Name += "_I" 2185151Sgblack@eecs.umich.edu elif opType.tag == "O": 2195151Sgblack@eecs.umich.edu # Immediate containing a memory offset 2205151Sgblack@eecs.umich.edu Name += "_MI" 2214348Sgblack@eecs.umich.edu elif opType.tag in ("PR", "R", "VR"): 2224601Sgblack@eecs.umich.edu # Non register modrm settings should cause an error 2234548Sgblack@eecs.umich.edu env.addReg(ModRMRMIndex) 2245788Sgblack@eecs.umich.edu env.addToDisassembly( 2255788Sgblack@eecs.umich.edu "printReg(out, %s, regSize);\n" % ModRMRMIndex) 2266518Sgblack@eecs.umich.edu if opType.tag == "PR": 2276518Sgblack@eecs.umich.edu Name += "_MMX" 2286518Sgblack@eecs.umich.edu elif opType.tag == "VR": 2296518Sgblack@eecs.umich.edu Name += "_XMM" 2306518Sgblack@eecs.umich.edu else: 2316518Sgblack@eecs.umich.edu Name += "_R" 2324868Sgblack@eecs.umich.edu elif opType.tag in ("X", "Y"): 2334868Sgblack@eecs.umich.edu # This type of memory addressing is for string instructions. 2344868Sgblack@eecs.umich.edu # They'll use the right index and segment internally. 2355788Sgblack@eecs.umich.edu if opType.tag == "X": 2365788Sgblack@eecs.umich.edu env.addToDisassembly( 2375788Sgblack@eecs.umich.edu '''printMem(out, env.seg, 2385788Sgblack@eecs.umich.edu 1, X86ISA::ZeroReg, X86ISA::INTREG_RSI, 0, 2395788Sgblack@eecs.umich.edu env.addressSize, false);''') 2405788Sgblack@eecs.umich.edu else: 2415788Sgblack@eecs.umich.edu env.addToDisassembly( 2425788Sgblack@eecs.umich.edu '''printMem(out, SEGMENT_REG_ES, 2435788Sgblack@eecs.umich.edu 1, X86ISA::ZeroReg, X86ISA::INTREG_RDI, 0, 2445788Sgblack@eecs.umich.edu env.addressSize, false);''') 2454868Sgblack@eecs.umich.edu Name += "_M" 2464348Sgblack@eecs.umich.edu else: 2474348Sgblack@eecs.umich.edu raise Exception, "Unrecognized tag %s." % opType.tag 2484348Sgblack@eecs.umich.edu 2494532Sgblack@eecs.umich.edu # Generate code to return a macroop of the given name which will 2504559Sgblack@eecs.umich.edu # operate in the "emulation environment" env 2514528Sgblack@eecs.umich.edu return genMacroop(Name, env) 2524348Sgblack@eecs.umich.edu}}; 253