specialize.isa revision 8250 
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007 The Hewlett-Packard Development Company
4// All rights reserved.
5//
6// The license below extends only to copyright in the software and shall
7// not be construed as granting a license to any other intellectual
8// property including but not limited to intellectual property relating
9// to a hardware implementation of the functionality of the software
10// licensed hereunder.  You may use the software subject to the license
11// terms below provided that you ensure that this notice is replicated
12// unmodified and in its entirety in all distributions of the software,
13// modified or unmodified, in source code or in binary form.
14//
15// Redistribution and use in source and binary forms, with or without
16// modification, are permitted provided that the following conditions are
17// met: redistributions of source code must retain the above copyright
18// notice, this list of conditions and the following disclaimer;
19// redistributions in binary form must reproduce the above copyright
20// notice, this list of conditions and the following disclaimer in the
21// documentation and/or other materials provided with the distribution;
22// neither the name of the copyright holders nor the names of its
23// contributors may be used to endorse or promote products derived from
24// this software without specific prior written permission.
25//
26// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37//
38// Authors: Gabe Black
39
40////////////////////////////////////////////////////////////////////
41//
42//  Code to "specialize" a microcode sequence to use a particular
43//  variety of operands
44//
45
46let {{
47    # This code builds up a decode block which decodes based on switchval.
48    # vals is a dict which matches case values with what should be decoded to.
49    # Each element of the dict is a list containing a function and then the
50    # arguments to pass to it.
51    def doSplitDecode(switchVal, vals, default = None):
52        blocks = OutputBlocks()
53        blocks.decode_block = 'switch(%s) {\n' % switchVal
54        for (val, todo) in vals.items():
55            new_blocks = todo[0](*todo[1:])
56            new_blocks.decode_block = \
57                '\tcase %s: %s\n' % (val, new_blocks.decode_block)
58            blocks.append(new_blocks)
59        if default:
60            new_blocks = default[0](*default[1:])
61            new_blocks.decode_block = \
62                '\tdefault: %s\n' % new_blocks.decode_block
63            blocks.append(new_blocks)
64        blocks.decode_block += '}\n'
65        return blocks
66}};
67
68let {{
69    def doRipRelativeDecode(Name, opTypes, env):
70        # print "RIPing %s with opTypes %s" % (Name, opTypes)
71        env.memoryInst = True
72        normEnv = copy.copy(env)
73        normEnv.addToDisassembly(
74                '''printMem(out, env.seg, env.scale, env.index, env.base,
75                    machInst.displacement, env.addressSize, false);''')
76        normBlocks = specializeInst(Name + "_M", copy.copy(opTypes), normEnv)
77        ripEnv = copy.copy(env)
78        ripEnv.addToDisassembly(
79                '''printMem(out, env.seg, 1, 0, 0,
80                    machInst.displacement, env.addressSize, true);''')
81        ripBlocks = specializeInst(Name + "_P", copy.copy(opTypes), ripEnv)
82
83        blocks = OutputBlocks()
84        blocks.append(normBlocks)
85        blocks.append(ripBlocks)
86
87        blocks.decode_block = '''
88        if(machInst.modRM.mod == 0 &&
89          machInst.modRM.rm == 5 &&
90          machInst.mode.submode == SixtyFourBitMode)
91        { %s }
92        else
93        { %s }''' % \
94         (ripBlocks.decode_block, normBlocks.decode_block)
95        return blocks
96}};
97
98let {{
99    def doBadInstDecode():
100        blocks = OutputBlocks()
101        blocks.decode_block = '''
102        return new Unknown(machInst);
103        '''
104        return blocks
105}};
106
107let {{
108    class OpType(object):
109        parser = re.compile(r"(?P<tag>[A-Z]+)(?P<size>[a-z]*)|(r(?P<reg>[A-Z0-9]+)(?P<rsize>[a-z]*))")
110        def __init__(self, opTypeString):
111            match = OpType.parser.search(opTypeString)
112            if match == None:
113                raise Exception, "Problem parsing operand type %s" % opTypeString
114            self.reg = match.group("reg")
115            self.tag = match.group("tag")
116            self.size = match.group("size")
117            if not self.size:
118                self.size = match.group("rsize")
119
120    ModRMRegIndex = "(MODRM_REG | (REX_R << 3))"
121    ModRMRMIndex = "(MODRM_RM | (REX_B << 3))"
122    InstRegIndex = "(OPCODE_OP_BOTTOM3 | (REX_B << 3))"
123
124    # This function specializes the given piece of code to use a particular
125    # set of argument types described by "opTypes".
126    def specializeInst(Name, opTypes, env):
127        # print "Specializing %s with opTypes %s" % (Name, opTypes)
128        while len(opTypes):
129            # Parse the operand type string we're working with
130            opType = OpType(opTypes[0])
131            opTypes.pop(0)
132
133            if opType.tag not in ("I", "J", "P", "PR", "Q", "V", "VR", "W"):
134                if opType.size:
135                    env.setSize(opType.size)
136
137            if opType.reg:
138                #Figure out what to do with fixed register operands
139                #This is the index to use, so we should stick it some place.
140                if opType.reg in ("A", "B", "C", "D"):
141                    regString = "INTREG_R%sX" % opType.reg
142                else:
143                    regString = "INTREG_R%s" % opType.reg
144                env.addReg(regString)
145                env.addToDisassembly(
146                        "printReg(out, %s, regSize);\n" % regString)
147                Name += "_R"
148            elif opType.tag == "B":
149                # This refers to registers whose index is encoded as part of the opcode
150                env.addToDisassembly(
151                        "printReg(out, %s, regSize);\n" % InstRegIndex)
152                Name += "_R"
153                env.addReg(InstRegIndex)
154            elif opType.tag == "M":
155                # This refers to memory. The macroop constructor sets up modrm
156                # addressing. Non memory modrm settings should cause an error.
157                env.doModRM = True
158                return doSplitDecode("MODRM_MOD",
159                        {"3" : (doBadInstDecode,) },
160                        (doRipRelativeDecode, Name, opTypes, env))
161            elif opType.tag == None or opType.size == None:
162                raise Exception, "Problem parsing operand tag: %s" % opType.tag
163            elif opType.tag == "C":
164                # A control register indexed by the "reg" field
165                env.addReg(ModRMRegIndex)
166                env.addToDisassembly(
167                        "ccprintf(out, \"CR%%d\", %s);\n" % ModRMRegIndex)
168                Name += "_C"
169            elif opType.tag == "D":
170                # A debug register indexed by the "reg" field
171                env.addReg(ModRMRegIndex)
172                env.addToDisassembly(
173                        "ccprintf(out, \"DR%%d\", %s);\n" % ModRMRegIndex)
174                Name += "_D"
175            elif opType.tag == "S":
176                # A segment selector register indexed by the "reg" field
177                env.addReg(ModRMRegIndex)
178                env.addToDisassembly(
179                        "printSegment(out, %s);\n" % ModRMRegIndex)
180                Name += "_S"
181            elif opType.tag in ("G", "P", "T", "V"):
182                # Use the "reg" field of the ModRM byte to select the register
183                env.addReg(ModRMRegIndex)
184                env.addToDisassembly(
185                        "printReg(out, %s, regSize);\n" % ModRMRegIndex)
186                if opType.tag == "P":
187                    Name += "_MMX"
188                elif opType.tag == "V":
189                    Name += "_XMM"
190                else:
191                    Name += "_R"
192            elif opType.tag in ("E", "Q", "W"):
193                # This might refer to memory or to a register. We need to
194                # divide it up farther.
195                regEnv = copy.copy(env)
196                regEnv.addReg(ModRMRMIndex)
197                regEnv.addToDisassembly(
198                        "printReg(out, %s, regSize);\n" % ModRMRMIndex)
199                # This refers to memory. The macroop constructor should set up
200                # modrm addressing.
201                memEnv = copy.copy(env)
202                memEnv.doModRM = True
203                regSuffix = "_R"
204                if opType.tag == "Q":
205                    regSuffix = "_MMX"
206                elif opType.tag == "W":
207                    regSuffix = "_XMM"
208                return doSplitDecode("MODRM_MOD",
209                    {"3" : (specializeInst, Name + regSuffix,
210                            copy.copy(opTypes), regEnv)},
211                           (doRipRelativeDecode, Name,
212                            copy.copy(opTypes), memEnv))
213            elif opType.tag in ("I", "J"):
214                # Immediates
215                env.addToDisassembly(
216                        "ccprintf(out, \"%#x\", machInst.immediate);\n")
217                Name += "_I"
218            elif opType.tag == "O":
219                # Immediate containing a memory offset
220                Name += "_MI"
221            elif opType.tag in ("PR", "R", "VR"):
222                # Non register modrm settings should cause an error
223                env.addReg(ModRMRMIndex)
224                env.addToDisassembly(
225                        "printReg(out, %s, regSize);\n" % ModRMRMIndex)
226                if opType.tag == "PR":
227                    Name += "_MMX"
228                elif opType.tag == "VR":
229                    Name += "_XMM"
230                else:
231                    Name += "_R"
232            elif opType.tag in ("X", "Y"):
233                # This type of memory addressing is for string instructions.
234                # They'll use the right index and segment internally.
235                if opType.tag == "X":
236                    env.addToDisassembly(
237                            '''printMem(out, env.seg,
238                                1, X86ISA::ZeroReg, X86ISA::INTREG_RSI, 0,
239                                env.addressSize, false);''')
240                else:
241                    env.addToDisassembly(
242                            '''printMem(out, SEGMENT_REG_ES,
243                                1, X86ISA::ZeroReg, X86ISA::INTREG_RDI, 0,
244                                env.addressSize, false);''')
245                Name += "_M"
246            else:
247                raise Exception, "Unrecognized tag %s." % opType.tag
248
249        # Generate code to return a macroop of the given name which will
250        # operate in the "emulation environment" env
251        return genMacroop(Name, env)
252}};
253