operands.isa revision 9211:46c3a74952ec
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license 9// terms below provided that you ensure that this notice is replicated 10// unmodified and in its entirety in all distributions of the software, 11// modified or unmodified, in source code or in binary form. 12// 13// Copyright (c) 2007 The Regents of The University of Michigan 14// All rights reserved. 15// 16// Redistribution and use in source and binary forms, with or without 17// modification, are permitted provided that the following conditions are 18// met: redistributions of source code must retain the above copyright 19// notice, this list of conditions and the following disclaimer; 20// redistributions in binary form must reproduce the above copyright 21// notice, this list of conditions and the following disclaimer in the 22// documentation and/or other materials provided with the distribution; 23// neither the name of the copyright holders nor the names of its 24// contributors may be used to endorse or promote products derived from 25// this software without specific prior written permission. 26// 27// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38// 39// Authors: Gabe Black 40 41def operand_types {{ 42 'sb' : 'int8_t', 43 'ub' : 'uint8_t', 44 'sw' : 'int16_t', 45 'uw' : 'uint16_t', 46 'sdw' : 'int32_t', 47 'udw' : 'uint32_t', 48 'sqw' : 'int64_t', 49 'uqw' : 'uint64_t', 50 'sf' : 'float', 51 'df' : 'double', 52}}; 53 54let {{ 55 def foldInt(idx, foldBit, id): 56 return ('IntReg', 'uqw', 'INTREG_FOLDED(%s, %s)' % (idx, foldBit), 57 'IsInteger', id) 58 def intReg(idx, id): 59 return ('IntReg', 'uqw', idx, 'IsInteger', id) 60 def impIntReg(idx, id): 61 return ('IntReg', 'uqw', 'INTREG_IMPLICIT(%s)' % idx, 'IsInteger', id) 62 def floatReg(idx, id): 63 return ('FloatReg', 'df', idx, 'IsFloating', id) 64 def controlReg(idx, id, ctype = 'uqw'): 65 return ('ControlReg', ctype, idx, 66 (None, None, ['IsSerializeAfter', 67 'IsSerializing', 68 'IsNonSpeculative']), 69 id) 70 def squashCheckReg(idx, id, check, ctype = 'uqw'): 71 return ('ControlReg', ctype, idx, 72 (None, None, ['((%s) ? ' % check+ \ 73 'IsSquashAfter : IsSerializeAfter)', 74 'IsSerializing', 75 'IsNonSpeculative']), 76 id) 77 def squashCReg(idx, id, ctype = 'uqw'): 78 return squashCheckReg(idx, id, 'true', ctype) 79 def squashCSReg(idx, id, ctype = 'uqw'): 80 return squashCheckReg(idx, id, 'dest == SEGMENT_REG_CS', ctype) 81 def squashCR0Reg(idx, id, ctype = 'uqw'): 82 return squashCheckReg(idx, id, 'dest == 0', ctype) 83}}; 84 85def operands {{ 86 'SrcReg1': foldInt('src1', 'foldOBit', 1), 87 'SSrcReg1': intReg('src1', 1), 88 'SrcReg2': foldInt('src2', 'foldOBit', 2), 89 'SSrcReg2': intReg('src2', 1), 90 'Index': foldInt('index', 'foldABit', 3), 91 'Base': foldInt('base', 'foldABit', 4), 92 'DestReg': foldInt('dest', 'foldOBit', 5), 93 'SDestReg': intReg('dest', 5), 94 'Data': foldInt('data', 'foldOBit', 6), 95 'ProdLow': impIntReg(0, 7), 96 'ProdHi': impIntReg(1, 8), 97 'Quotient': impIntReg(2, 9), 98 'Remainder': impIntReg(3, 10), 99 'Divisor': impIntReg(4, 11), 100 'DoubleBits': impIntReg(5, 11), 101 'Rax': intReg('(INTREG_RAX)', 12), 102 'Rbx': intReg('(INTREG_RBX)', 13), 103 'Rcx': intReg('(INTREG_RCX)', 14), 104 'Rdx': intReg('(INTREG_RDX)', 15), 105 'Rsp': intReg('(INTREG_RSP)', 16), 106 'Rbp': intReg('(INTREG_RBP)', 17), 107 'Rsi': intReg('(INTREG_RSI)', 18), 108 'Rdi': intReg('(INTREG_RDI)', 19), 109 'FpSrcReg1': floatReg('src1', 20), 110 'FpSrcReg2': floatReg('src2', 21), 111 'FpDestReg': floatReg('dest', 22), 112 'FpData': floatReg('data', 23), 113 'RIP': ('PCState', 'uqw', 'pc', 114 (None, None, 'IsControl'), 50), 115 'NRIP': ('PCState', 'uqw', 'npc', 116 (None, None, 'IsControl'), 50), 117 'nuIP': ('PCState', 'uqw', 'nupc', 118 (None, None, 'IsControl'), 50), 119 # This holds the condition code portion of the flag register. The 120 # nccFlagBits version holds the rest. 121 'ccFlagBits': intReg('INTREG_PSEUDO(0)', 60), 122 'cfofBits': intReg('INTREG_PSEUDO(1)', 61), 123 'dfBit': intReg('INTREG_PSEUDO(2)', 62), 124 'ecfBit': intReg('INTREG_PSEUDO(3)', 63), 125 'ezfBit': intReg('INTREG_PSEUDO(4)', 64), 126 # These register should needs to be more protected so that later 127 # instructions don't map their indexes with an old value. 128 'nccFlagBits': controlReg('MISCREG_RFLAGS', 65), 129 'TOP': controlReg('MISCREG_X87_TOP', 66, ctype='ub'), 130 # The segment base as used by memory instructions. 131 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70), 132 133 # Operands to get and set registers indexed by the operands of the 134 # original instruction. 135 'ControlDest': squashCR0Reg('MISCREG_CR(dest)', 100), 136 'ControlSrc1': controlReg('MISCREG_CR(src1)', 101), 137 'DebugDest': controlReg('MISCREG_DR(dest)', 102), 138 'DebugSrc1': controlReg('MISCREG_DR(src1)', 103), 139 'SegBaseDest': squashCSReg('MISCREG_SEG_BASE(dest)', 104), 140 'SegBaseSrc1': controlReg('MISCREG_SEG_BASE(src1)', 105), 141 'SegLimitDest': squashCSReg('MISCREG_SEG_LIMIT(dest)', 106), 142 'SegLimitSrc1': controlReg('MISCREG_SEG_LIMIT(src1)', 107), 143 'SegSelDest': controlReg('MISCREG_SEG_SEL(dest)', 108), 144 'SegSelSrc1': controlReg('MISCREG_SEG_SEL(src1)', 109), 145 'SegAttrDest': squashCSReg('MISCREG_SEG_ATTR(dest)', 110), 146 'SegAttrSrc1': controlReg('MISCREG_SEG_ATTR(src1)', 111), 147 148 # Operands to access specific control registers directly. 149 'EferOp': squashCReg('MISCREG_EFER', 200), 150 'CR4Op': controlReg('MISCREG_CR4', 201), 151 'DR7Op': controlReg('MISCREG_DR7', 202), 152 'LDTRBase': controlReg('MISCREG_TSL_BASE', 203), 153 'LDTRLimit': controlReg('MISCREG_TSL_LIMIT', 204), 154 'LDTRSel': controlReg('MISCREG_TSL', 205), 155 'GDTRBase': controlReg('MISCREG_TSG_BASE', 206), 156 'GDTRLimit': controlReg('MISCREG_TSG_LIMIT', 207), 157 'CSBase': squashCReg('MISCREG_CS_EFF_BASE', 208), 158 'CSAttr': squashCReg('MISCREG_CS_ATTR', 209), 159 'MiscRegDest': controlReg('dest', 210), 160 'MiscRegSrc1': controlReg('src1', 211), 161 'TscOp': controlReg('MISCREG_TSC', 212), 162 'M5Reg': squashCReg('MISCREG_M5_REG', 213), 163 'Mem': ('Mem', 'uqw', None, \ 164 ('IsMemRef', 'IsLoad', 'IsStore'), 300) 165}}; 166