operands.isa revision 7720:65d338a8dba4
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder.  You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Copyright (c) 2007 The Regents of The University of Michigan
14// All rights reserved.
15//
16// Redistribution and use in source and binary forms, with or without
17// modification, are permitted provided that the following conditions are
18// met: redistributions of source code must retain the above copyright
19// notice, this list of conditions and the following disclaimer;
20// redistributions in binary form must reproduce the above copyright
21// notice, this list of conditions and the following disclaimer in the
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23// neither the name of the copyright holders nor the names of its
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25// this software without specific prior written permission.
26//
27// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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38//
39// Authors: Gabe Black
40
41def operand_types {{
42    'sb' : ('signed int', 8),
43    'ub' : ('unsigned int', 8),
44    'sw' : ('signed int', 16),
45    'uw' : ('unsigned int', 16),
46    'sdw' : ('signed int', 32),
47    'udw' : ('unsigned int', 32),
48    'sqw' : ('signed int', 64),
49    'uqw' : ('unsigned int', 64),
50    'sf' : ('float', 32),
51    'df' : ('float', 64),
52}};
53
54let {{
55    def foldInt(idx, foldBit, id):
56        return ('IntReg', 'uqw', 'INTREG_FOLDED(%s, %s)' % (idx, foldBit),
57                'IsInteger', id)
58    def intReg(idx, id):
59        return ('IntReg', 'uqw', idx, 'IsInteger', id)
60    def impIntReg(idx, id):
61        return ('IntReg', 'uqw', 'INTREG_IMPLICIT(%s)' % idx, 'IsInteger', id)
62    def floatReg(idx, id):
63        return ('FloatReg', 'df', idx, 'IsFloating', id)
64    def controlReg(idx, id, ctype = 'uqw'):
65        return ('ControlReg', ctype, idx,
66                (None, None, ['IsSerializeAfter',
67                              'IsSerializing',
68                              'IsNonSpeculative']),
69                id)
70}};
71
72def operands {{
73        'SrcReg1':       foldInt('src1', 'foldOBit', 1),
74        'SSrcReg1':      intReg('src1', 1),
75        'SrcReg2':       foldInt('src2', 'foldOBit', 2),
76        'SSrcReg2':      intReg('src2', 1),
77        'Index':         foldInt('index', 'foldABit', 3),
78        'Base':          foldInt('base', 'foldABit', 4),
79        'DestReg':       foldInt('dest', 'foldOBit', 5),
80        'SDestReg':      intReg('dest', 5),
81        'Data':          foldInt('data', 'foldOBit', 6),
82        'ProdLow':       impIntReg(0, 7),
83        'ProdHi':        impIntReg(1, 8),
84        'Quotient':      impIntReg(2, 9),
85        'Remainder':     impIntReg(3, 10),
86        'Divisor':       impIntReg(4, 11),
87        'DoubleBits':    impIntReg(5, 11),
88        'Rax':           intReg('(INTREG_RAX)', 12),
89        'Rbx':           intReg('(INTREG_RBX)', 13),
90        'Rcx':           intReg('(INTREG_RCX)', 14),
91        'Rdx':           intReg('(INTREG_RDX)', 15),
92        'Rsp':           intReg('(INTREG_RSP)', 16),
93        'Rbp':           intReg('(INTREG_RBP)', 17),
94        'Rsi':           intReg('(INTREG_RSI)', 18),
95        'Rdi':           intReg('(INTREG_RDI)', 19),
96        'FpSrcReg1':     floatReg('src1', 20),
97        'FpSrcReg2':     floatReg('src2', 21),
98        'FpDestReg':     floatReg('dest', 22),
99        'FpData':        floatReg('data', 23),
100        'PCS':           ('PCState', 'udw', None,
101                          (None, None, 'IsControl'), 50),
102        # This holds the condition code portion of the flag register. The
103        # nccFlagBits version holds the rest.
104        'ccFlagBits':    intReg('INTREG_PSEUDO(0)', 60),
105        # These register should needs to be more protected so that later
106        # instructions don't map their indexes with an old value.
107        'nccFlagBits':   controlReg('MISCREG_RFLAGS', 61),
108        'TOP':           controlReg('MISCREG_X87_TOP', 62, ctype='ub'),
109        # The segment base as used by memory instructions.
110        'SegBase':       controlReg('MISCREG_SEG_EFF_BASE(segment)', 70),
111
112        # Operands to get and set registers indexed by the operands of the
113        # original instruction.
114        'ControlDest':   controlReg('MISCREG_CR(dest)', 100),
115        'ControlSrc1':   controlReg('MISCREG_CR(src1)', 101),
116        'DebugDest':     controlReg('MISCREG_DR(dest)', 102),
117        'DebugSrc1':     controlReg('MISCREG_DR(src1)', 103),
118        'SegBaseDest':   controlReg('MISCREG_SEG_BASE(dest)', 104),
119        'SegBaseSrc1':   controlReg('MISCREG_SEG_BASE(src1)', 105),
120        'SegLimitDest':  controlReg('MISCREG_SEG_LIMIT(dest)', 106),
121        'SegLimitSrc1':  controlReg('MISCREG_SEG_LIMIT(src1)', 107),
122        'SegSelDest':    controlReg('MISCREG_SEG_SEL(dest)', 108),
123        'SegSelSrc1':    controlReg('MISCREG_SEG_SEL(src1)', 109),
124        'SegAttrDest':   controlReg('MISCREG_SEG_ATTR(dest)', 110),
125        'SegAttrSrc1':   controlReg('MISCREG_SEG_ATTR(src1)', 111),
126
127        # Operands to access specific control registers directly.
128        'EferOp':        controlReg('MISCREG_EFER', 200),
129        'CR4Op':         controlReg('MISCREG_CR4', 201),
130        'DR7Op':         controlReg('MISCREG_DR7', 202),
131        'LDTRBase':      controlReg('MISCREG_TSL_BASE', 203),
132        'LDTRLimit':     controlReg('MISCREG_TSL_LIMIT', 204),
133        'LDTRSel':       controlReg('MISCREG_TSL', 205),
134        'GDTRBase':      controlReg('MISCREG_TSG_BASE', 206),
135        'GDTRLimit':     controlReg('MISCREG_TSG_LIMIT', 207),
136        'CSBase':        controlReg('MISCREG_CS_EFF_BASE', 208),
137        'CSAttr':        controlReg('MISCREG_CS_ATTR', 209),
138        'MiscRegDest':   controlReg('dest', 210),
139        'MiscRegSrc1':   controlReg('src1', 211),
140        'TscOp':         controlReg('MISCREG_TSC', 212),
141        'M5Reg':         controlReg('MISCREG_M5_REG', 213),
142        'Mem':           ('Mem', 'uqw', None, \
143                          ('IsMemRef', 'IsLoad', 'IsStore'), 300)
144}};
145