seqop.isa revision 7720:65d338a8dba4 
1// Copyright (c) 2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder.  You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Redistribution and use in source and binary forms, with or without
14// modification, are permitted provided that the following conditions are
15// met: redistributions of source code must retain the above copyright
16// notice, this list of conditions and the following disclaimer;
17// redistributions in binary form must reproduce the above copyright
18// notice, this list of conditions and the following disclaimer in the
19// documentation and/or other materials provided with the distribution;
20// neither the name of the copyright holders nor the names of its
21// contributors may be used to endorse or promote products derived from
22// this software without specific prior written permission.
23//
24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35//
36// Authors: Gabe Black
37
38output header {{
39    class SeqOpBase : public X86ISA::X86MicroopBase
40    {
41      protected:
42        uint16_t target;
43        uint8_t cc;
44
45      public:
46        SeqOpBase(ExtMachInst _machInst, const char * instMnem,
47                const char * mnemonic, uint64_t setFlags,
48                uint16_t _target, uint8_t _cc);
49
50        SeqOpBase(ExtMachInst _machInst, const char * instMnem,
51                const char * mnemonic,
52                uint16_t _target, uint8_t _cc);
53
54        std::string generateDisassembly(Addr pc,
55                const SymbolTable *symtab) const;
56    };
57}};
58
59def template SeqOpDeclare {{
60    class %(class_name)s : public %(base_class)s
61    {
62      public:
63        %(class_name)s(ExtMachInst _machInst, const char * instMnem,
64                uint64_t setFlags, uint16_t _target, uint8_t _cc);
65
66        %(BasicExecDeclare)s
67    };
68}};
69
70def template SeqOpExecute {{
71        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
72                Trace::InstRecord *traceData) const
73        {
74            %(op_decl)s;
75            %(op_rd)s;
76            if (%(cond_test)s) {
77                %(code)s;
78            } else {
79                %(else_code)s;
80            }
81            %(op_wb)s;
82            return NoFault;
83        }
84}};
85
86output decoder {{
87    inline SeqOpBase::SeqOpBase(
88            ExtMachInst machInst, const char * mnemonic, const char * instMnem,
89            uint64_t setFlags, uint16_t _target, uint8_t _cc) :
90        X86MicroopBase(machInst, mnemonic, instMnem, setFlags, No_OpClass),
91                target(_target), cc(_cc)
92    {
93    }
94}};
95
96def template SeqOpConstructor {{
97    inline %(class_name)s::%(class_name)s(
98            ExtMachInst machInst, const char * instMnem,
99            uint64_t setFlags, uint16_t _target, uint8_t _cc) :
100        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
101                setFlags, _target, _cc)
102    {
103        %(constructor)s;
104    }
105}};
106
107output decoder {{
108    std::string SeqOpBase::generateDisassembly(Addr pc,
109            const SymbolTable *symtab) const
110    {
111        std::stringstream response;
112
113        printMnemonic(response, instMnem, mnemonic);
114        ccprintf(response, "%#x", target);
115
116        return response.str();
117    }
118}};
119
120let {{
121    class SeqOp(X86Microop):
122        def __init__(self, target, flags=None):
123            self.target = target
124            if flags:
125                if not isinstance(flags, (list, tuple)):
126                    raise Exception, "flags must be a list or tuple of flags"
127                self.cond = " | ".join(flags)
128                self.className += "Flags"
129            else:
130                self.cond = "0"
131
132        def getAllocator(self, microFlags):
133            allocator = '''new %(class_name)s(machInst, macrocodeBlock,
134                    %(flags)s, %(target)s, %(cc)s)''' % {
135                "class_name" : self.className,
136                "flags" : self.microFlagsText(microFlags),
137                "target" : self.target,
138                "cc" : self.cond}
139            return allocator
140
141    class Br(SeqOp):
142        className = "MicroBranch"
143
144        def getAllocator(self, microFlags):
145            if "IsLastMicroop" in microFlags:
146                microFlags.remove("IsLastMicroop")
147            if not "IsDelayedCommit" in microFlags:
148                microFlags.append("IsDelayedCommit")
149            return super(Br, self).getAllocator(microFlags)
150
151    class Eret(SeqOp):
152        target = "normalMicroPC(0)"
153        className = "Eret"
154
155        def __init__(self, flags=None):
156            if flags:
157                if not isinstance(flags, (list, tuple)):
158                    raise Exception, "flags must be a list or tuple of flags"
159                self.cond = " | ".join(flags)
160                self.className += "Flags"
161            else:
162                self.cond = "0"
163
164        def getAllocator(self, microFlags):
165            if not "IsLastMicroop" in microFlags:
166                microFlags.append("IsLastMicroop")
167            if "IsDelayedCommit" in microFlags:
168                microFlags.remove("IsDelayedCommit")
169            return super(Eret, self).getAllocator(microFlags)
170
171    iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase",
172            {"code": '''
173             X86ISA::PCState pc = PCS;
174             pc.nupc(target);
175             PCS = pc;
176             ''',
177             "else_code": "PCS = PCS",
178             "cond_test": "checkCondition(ccFlagBits, cc)"})
179    exec_output += SeqOpExecute.subst(iop)
180    header_output += SeqOpDeclare.subst(iop)
181    decoder_output += SeqOpConstructor.subst(iop)
182    iop = InstObjParams("br", "MicroBranch", "SeqOpBase",
183            {"code": '''
184             X86ISA::PCState pc = PCS;
185             pc.nupc(target);
186             PCS = pc;
187             ''',
188             "else_code": "PCS = PCS",
189             "cond_test": "true"})
190    exec_output += SeqOpExecute.subst(iop)
191    header_output += SeqOpDeclare.subst(iop)
192    decoder_output += SeqOpConstructor.subst(iop)
193    microopClasses["br"] = Br
194
195    iop = InstObjParams("eret", "EretFlags", "SeqOpBase",
196            {"code": "", "else_code": "",
197             "cond_test": "checkCondition(ccFlagBits, cc)"})
198    exec_output += SeqOpExecute.subst(iop)
199    header_output += SeqOpDeclare.subst(iop)
200    decoder_output += SeqOpConstructor.subst(iop)
201    iop = InstObjParams("eret", "Eret", "SeqOpBase",
202            {"code": "", "else_code": "",
203             "cond_test": "true"})
204    exec_output += SeqOpExecute.subst(iop)
205    header_output += SeqOpDeclare.subst(iop)
206    decoder_output += SeqOpConstructor.subst(iop)
207    microopClasses["eret"] = Eret
208}};
209