seqop.isa revision 10184:bbfa3152bdea 
1// Copyright (c) 2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder.  You may use the software subject to the license
9// terms below provided that you ensure that this notice is replicated
10// unmodified and in its entirety in all distributions of the software,
11// modified or unmodified, in source code or in binary form.
12//
13// Redistribution and use in source and binary forms, with or without
14// modification, are permitted provided that the following conditions are
15// met: redistributions of source code must retain the above copyright
16// notice, this list of conditions and the following disclaimer;
17// redistributions in binary form must reproduce the above copyright
18// notice, this list of conditions and the following disclaimer in the
19// documentation and/or other materials provided with the distribution;
20// neither the name of the copyright holders nor the names of its
21// contributors may be used to endorse or promote products derived from
22// this software without specific prior written permission.
23//
24// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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33// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35//
36// Authors: Gabe Black
37
38output header {{
39    class SeqOpBase : public X86ISA::X86MicroopBase
40    {
41      protected:
42        uint16_t target;
43        uint8_t cc;
44
45      public:
46        SeqOpBase(ExtMachInst _machInst, const char * instMnem,
47                const char * mnemonic, uint64_t setFlags,
48                uint16_t _target, uint8_t _cc);
49
50        SeqOpBase(ExtMachInst _machInst, const char * instMnem,
51                const char * mnemonic,
52                uint16_t _target, uint8_t _cc);
53
54        std::string generateDisassembly(Addr pc,
55                const SymbolTable *symtab) const;
56    };
57}};
58
59def template SeqOpDeclare {{
60    class %(class_name)s : public %(base_class)s
61    {
62      public:
63        %(class_name)s(ExtMachInst _machInst, const char * instMnem,
64                uint64_t setFlags, uint16_t _target, uint8_t _cc);
65
66        %(BasicExecDeclare)s
67    };
68}};
69
70def template SeqOpExecute {{
71        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
72                Trace::InstRecord *traceData) const
73        {
74            %(op_decl)s;
75            %(op_rd)s;
76            if (%(cond_test)s) {
77                %(code)s;
78            } else {
79                %(else_code)s;
80            }
81            %(op_wb)s;
82            return NoFault;
83        }
84}};
85
86output decoder {{
87    SeqOpBase::SeqOpBase(
88            ExtMachInst machInst, const char * mnemonic, const char * instMnem,
89            uint64_t setFlags, uint16_t _target, uint8_t _cc) :
90        X86MicroopBase(machInst, mnemonic, instMnem, setFlags, No_OpClass),
91                target(_target), cc(_cc)
92    {
93    }
94}};
95
96def template SeqOpConstructor {{
97    %(class_name)s::%(class_name)s(
98            ExtMachInst machInst, const char * instMnem,
99            uint64_t setFlags, uint16_t _target, uint8_t _cc) :
100        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
101                setFlags, _target, _cc)
102    {
103        %(constructor)s;
104        %(cond_control_flag_init)s;
105    }
106}};
107
108output decoder {{
109    std::string SeqOpBase::generateDisassembly(Addr pc,
110            const SymbolTable *symtab) const
111    {
112        std::stringstream response;
113
114        printMnemonic(response, instMnem, mnemonic);
115        ccprintf(response, "%#x", target);
116
117        return response.str();
118    }
119}};
120
121let {{
122    class SeqOp(X86Microop):
123        def __init__(self, target, flags=None):
124            self.target = target
125            if flags:
126                if not isinstance(flags, (list, tuple)):
127                    raise Exception, "flags must be a list or tuple of flags"
128                self.cond = " | ".join(flags)
129                self.className += "Flags"
130            else:
131                self.cond = "0"
132
133        def getAllocator(self, microFlags):
134            allocator = '''new %(class_name)s(machInst, macrocodeBlock,
135                    %(flags)s, %(target)s, %(cc)s)''' % {
136                "class_name" : self.className,
137                "flags" : self.microFlagsText(microFlags),
138                "target" : self.target,
139                "cc" : self.cond}
140            return allocator
141
142    class Br(SeqOp):
143        className = "MicroBranch"
144
145        def getAllocator(self, microFlags):
146            if "IsLastMicroop" in microFlags:
147                microFlags.remove("IsLastMicroop")
148            if not "IsDelayedCommit" in microFlags:
149                microFlags.append("IsDelayedCommit")
150            return super(Br, self).getAllocator(microFlags)
151
152    class Eret(SeqOp):
153        target = "normalMicroPC(0)"
154        className = "Eret"
155
156        def __init__(self, flags=None):
157            if flags:
158                if not isinstance(flags, (list, tuple)):
159                    raise Exception, "flags must be a list or tuple of flags"
160                self.cond = " | ".join(flags)
161                self.className += "Flags"
162            else:
163                self.cond = "0"
164
165        def getAllocator(self, microFlags):
166            if not "IsLastMicroop" in microFlags:
167                microFlags.append("IsLastMicroop")
168            if "IsDelayedCommit" in microFlags:
169                microFlags.remove("IsDelayedCommit")
170            return super(Eret, self).getAllocator(microFlags)
171
172    iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase",
173            {"code": "nuIP = target;",
174             "else_code": "nuIP = nuIP;",
175             "cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
176                                          ecfBit | ezfBit, cc)",
177             "cond_control_flag_init": "flags[IsCondControl] = true"})
178    exec_output += SeqOpExecute.subst(iop)
179    header_output += SeqOpDeclare.subst(iop)
180    decoder_output += SeqOpConstructor.subst(iop)
181    iop = InstObjParams("br", "MicroBranch", "SeqOpBase",
182            {"code": "nuIP = target;",
183             "else_code": "nuIP = nuIP;",
184             "cond_test": "true",
185             "cond_control_flag_init": ""})
186    exec_output += SeqOpExecute.subst(iop)
187    header_output += SeqOpDeclare.subst(iop)
188    decoder_output += SeqOpConstructor.subst(iop)
189    microopClasses["br"] = Br
190
191    iop = InstObjParams("eret", "EretFlags", "SeqOpBase",
192            {"code": "", "else_code": "",
193             "cond_test": "checkCondition(ccFlagBits | cfofBits | dfBit | \
194                                          ecfBit | ezfBit, cc)",
195             "cond_control_flag_init": ""})
196    exec_output += SeqOpExecute.subst(iop)
197    header_output += SeqOpDeclare.subst(iop)
198    decoder_output += SeqOpConstructor.subst(iop)
199    iop = InstObjParams("eret", "Eret", "SeqOpBase",
200            {"code": "", "else_code": "",
201             "cond_test": "true",
202             "cond_control_flag_init": ""})
203    exec_output += SeqOpExecute.subst(iop)
204    header_output += SeqOpDeclare.subst(iop)
205    decoder_output += SeqOpConstructor.subst(iop)
206    microopClasses["eret"] = Eret
207}};
208