regop.isa revision 6456
19793Sakash.bagdia@arm.com// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 29518SAndreas.Sandberg@ARM.com// All rights reserved. 311320Ssteve.reinhardt@amd.com// 49518SAndreas.Sandberg@ARM.com// Redistribution and use of this software in source and binary forms, 59518SAndreas.Sandberg@ARM.com// with or without modification, are permitted provided that the 69518SAndreas.Sandberg@ARM.com// following conditions are met: 79518SAndreas.Sandberg@ARM.com// 89518SAndreas.Sandberg@ARM.com// The software must be used only for Non-Commercial Use which means any 99518SAndreas.Sandberg@ARM.com// use which is NOT directed to receiving any direct monetary 109518SAndreas.Sandberg@ARM.com// compensation for, or commercial advantage from such use. Illustrative 119518SAndreas.Sandberg@ARM.com// examples of non-commercial use are academic research, personal study, 129518SAndreas.Sandberg@ARM.com// teaching, education and corporate research & development. 135347Ssaidi@eecs.umich.edu// Illustrative examples of commercial use are distributing products for 147534Ssteve.reinhardt@amd.com// commercial advantage and providing services using the software for 153395Shsul@eecs.umich.edu// commercial advantage. 163395Shsul@eecs.umich.edu// 173395Shsul@eecs.umich.edu// If you wish to use this software or functionality therein that may be 183395Shsul@eecs.umich.edu// covered by patents for commercial use, please contact: 193395Shsul@eecs.umich.edu// Director of Intellectual Property Licensing 203395Shsul@eecs.umich.edu// Office of Strategy and Technology 213395Shsul@eecs.umich.edu// Hewlett-Packard Company 223395Shsul@eecs.umich.edu// 1501 Page Mill Road 233395Shsul@eecs.umich.edu// Palo Alto, California 94304 243395Shsul@eecs.umich.edu// 253395Shsul@eecs.umich.edu// Redistributions of source code must retain the above copyright notice, 263395Shsul@eecs.umich.edu// this list of conditions and the following disclaimer. Redistributions 273395Shsul@eecs.umich.edu// in binary form must reproduce the above copyright notice, this list of 283395Shsul@eecs.umich.edu// conditions and the following disclaimer in the documentation and/or 293395Shsul@eecs.umich.edu// other materials provided with the distribution. Neither the name of 303395Shsul@eecs.umich.edu// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 313395Shsul@eecs.umich.edu// contributors may be used to endorse or promote products derived from 323395Shsul@eecs.umich.edu// this software without specific prior written permission. No right of 333395Shsul@eecs.umich.edu// sublicense is granted herewith. Derivatives of the software and 343395Shsul@eecs.umich.edu// output created using the software may be prepared, but only for 353395Shsul@eecs.umich.edu// Non-Commercial Uses. Derivatives of the software may be shared with 363395Shsul@eecs.umich.edu// others provided: (i) the others agree to abide by the list of 373395Shsul@eecs.umich.edu// conditions herein which includes the Non-Commercial Use restrictions; 383395Shsul@eecs.umich.edu// and (ii) such Derivatives of the software include the above copyright 393395Shsul@eecs.umich.edu// notice to acknowledge the contribution from this software where 403395Shsul@eecs.umich.edu// applicable, this list of conditions and the disclaimer below. 413395Shsul@eecs.umich.edu// 429457Svilanova@ac.upc.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 433395Shsul@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 443509Shsul@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 456654Snate@binkert.org// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 4611688Sandreas.hansson@arm.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 4711688Sandreas.hansson@arm.com// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 489520SAndreas.Sandberg@ARM.com// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 493395Shsul@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 506654Snate@binkert.org// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 513395Shsul@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 526654Snate@binkert.org// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 536654Snate@binkert.org// 546654Snate@binkert.org// Authors: Gabe Black 553395Shsul@eecs.umich.edu 569139Snilay@cs.wisc.edu////////////////////////////////////////////////////////////////////////// 579520SAndreas.Sandberg@ARM.com// 589520SAndreas.Sandberg@ARM.com// RegOp Microop templates 599520SAndreas.Sandberg@ARM.com// 609139Snilay@cs.wisc.edu////////////////////////////////////////////////////////////////////////// 613481Shsul@eecs.umich.edu 629139Snilay@cs.wisc.edudef template MicroRegOpExecute {{ 633481Shsul@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 649139Snilay@cs.wisc.edu Trace::InstRecord *traceData) const 659139Snilay@cs.wisc.edu { 669139Snilay@cs.wisc.edu Fault fault = NoFault; 679139Snilay@cs.wisc.edu 689139Snilay@cs.wisc.edu DPRINTF(X86, "The data size is %d\n", dataSize); 699139Snilay@cs.wisc.edu %(op_decl)s; 709139Snilay@cs.wisc.edu %(op_rd)s; 719139Snilay@cs.wisc.edu 723481Shsul@eecs.umich.edu if(%(cond_check)s) 739518SAndreas.Sandberg@ARM.com { 749518SAndreas.Sandberg@ARM.com %(code)s; 759518SAndreas.Sandberg@ARM.com %(flag_code)s; 763481Shsul@eecs.umich.edu } 779139Snilay@cs.wisc.edu else 789139Snilay@cs.wisc.edu { 793481Shsul@eecs.umich.edu %(else_code)s; 809139Snilay@cs.wisc.edu } 819139Snilay@cs.wisc.edu 829139Snilay@cs.wisc.edu //Write the resulting state to the execution context 839139Snilay@cs.wisc.edu if(fault == NoFault) 849139Snilay@cs.wisc.edu { 853481Shsul@eecs.umich.edu %(op_wb)s; 863481Shsul@eecs.umich.edu } 873481Shsul@eecs.umich.edu return fault; 889665Sandreas.hansson@arm.com } 899665Sandreas.hansson@arm.com}}; 909665Sandreas.hansson@arm.com 919665Sandreas.hansson@arm.comdef template MicroRegOpImmExecute {{ 929665Sandreas.hansson@arm.com Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 938919Snilay@cs.wisc.edu Trace::InstRecord *traceData) const 948919Snilay@cs.wisc.edu { 958919Snilay@cs.wisc.edu Fault fault = NoFault; 9610159Sgedare@rtems.org 9710159Sgedare@rtems.org %(op_decl)s; 988919Snilay@cs.wisc.edu %(op_rd)s; 998919Snilay@cs.wisc.edu 1008919Snilay@cs.wisc.edu if(%(cond_check)s) 1018919Snilay@cs.wisc.edu { 1028919Snilay@cs.wisc.edu %(code)s; 1038919Snilay@cs.wisc.edu %(flag_code)s; 1048919Snilay@cs.wisc.edu } 1058919Snilay@cs.wisc.edu else 1068919Snilay@cs.wisc.edu { 1078919Snilay@cs.wisc.edu %(else_code)s; 1088919Snilay@cs.wisc.edu } 1098919Snilay@cs.wisc.edu 1103481Shsul@eecs.umich.edu //Write the resulting state to the execution context 1119816Sjthestness@gmail.com if(fault == NoFault) 1129140Snilay@cs.wisc.edu { 1139140Snilay@cs.wisc.edu %(op_wb)s; 1149140Snilay@cs.wisc.edu } 1159140Snilay@cs.wisc.edu return fault; 1169140Snilay@cs.wisc.edu } 1179140Snilay@cs.wisc.edu}}; 1189140Snilay@cs.wisc.edu 1199140Snilay@cs.wisc.edudef template MicroRegOpDeclare {{ 1209140Snilay@cs.wisc.edu class %(class_name)s : public %(base_class)s 1219140Snilay@cs.wisc.edu { 1229140Snilay@cs.wisc.edu protected: 1239140Snilay@cs.wisc.edu void buildMe(); 1249140Snilay@cs.wisc.edu 1259140Snilay@cs.wisc.edu public: 1269140Snilay@cs.wisc.edu %(class_name)s(ExtMachInst _machInst, 1279140Snilay@cs.wisc.edu const char * instMnem, 1289140Snilay@cs.wisc.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1299140Snilay@cs.wisc.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1309140Snilay@cs.wisc.edu uint8_t _dataSize, uint16_t _ext); 1319867Sjthestness@gmail.com 1329140Snilay@cs.wisc.edu %(class_name)s(ExtMachInst _machInst, 1339140Snilay@cs.wisc.edu const char * instMnem, 1349140Snilay@cs.wisc.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1359140Snilay@cs.wisc.edu uint8_t _dataSize, uint16_t _ext); 1369140Snilay@cs.wisc.edu 1379140Snilay@cs.wisc.edu %(BasicExecDeclare)s 1389140Snilay@cs.wisc.edu }; 1399140Snilay@cs.wisc.edu}}; 1409140Snilay@cs.wisc.edu 1419140Snilay@cs.wisc.edudef template MicroRegOpImmDeclare {{ 1429140Snilay@cs.wisc.edu 14310608Sdam.sunwoo@arm.com class %(class_name)s : public %(base_class)s 14410608Sdam.sunwoo@arm.com { 14510608Sdam.sunwoo@arm.com protected: 14610608Sdam.sunwoo@arm.com void buildMe(); 14710608Sdam.sunwoo@arm.com 14810608Sdam.sunwoo@arm.com public: 14910608Sdam.sunwoo@arm.com %(class_name)s(ExtMachInst _machInst, 15010608Sdam.sunwoo@arm.com const char * instMnem, 15110608Sdam.sunwoo@arm.com bool isMicro, bool isDelayed, bool isFirst, bool isLast, 15210608Sdam.sunwoo@arm.com InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 15310608Sdam.sunwoo@arm.com uint8_t _dataSize, uint16_t _ext); 15410608Sdam.sunwoo@arm.com 15510608Sdam.sunwoo@arm.com %(class_name)s(ExtMachInst _machInst, 15610608Sdam.sunwoo@arm.com const char * instMnem, 15710608Sdam.sunwoo@arm.com InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 15810608Sdam.sunwoo@arm.com uint8_t _dataSize, uint16_t _ext); 15910608Sdam.sunwoo@arm.com 16010608Sdam.sunwoo@arm.com %(BasicExecDeclare)s 16110608Sdam.sunwoo@arm.com }; 16210608Sdam.sunwoo@arm.com}}; 16310608Sdam.sunwoo@arm.com 16410608Sdam.sunwoo@arm.comdef template MicroRegOpConstructor {{ 16510608Sdam.sunwoo@arm.com 16610608Sdam.sunwoo@arm.com inline void %(class_name)s::buildMe() 16710608Sdam.sunwoo@arm.com { 16810608Sdam.sunwoo@arm.com %(constructor)s; 16910608Sdam.sunwoo@arm.com } 17010608Sdam.sunwoo@arm.com 17110608Sdam.sunwoo@arm.com inline %(class_name)s::%(class_name)s( 17210608Sdam.sunwoo@arm.com ExtMachInst machInst, const char * instMnem, 17310608Sdam.sunwoo@arm.com InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 17410608Sdam.sunwoo@arm.com uint8_t _dataSize, uint16_t _ext) : 17510608Sdam.sunwoo@arm.com %(base_class)s(machInst, "%(mnemonic)s", instMnem, 17610608Sdam.sunwoo@arm.com false, false, false, false, 17710608Sdam.sunwoo@arm.com _src1, _src2, _dest, _dataSize, _ext, 17810608Sdam.sunwoo@arm.com %(op_class)s) 17910608Sdam.sunwoo@arm.com { 1809140Snilay@cs.wisc.edu buildMe(); 1819140Snilay@cs.wisc.edu } 18210608Sdam.sunwoo@arm.com 1839140Snilay@cs.wisc.edu inline %(class_name)s::%(class_name)s( 1849140Snilay@cs.wisc.edu ExtMachInst machInst, const char * instMnem, 1859140Snilay@cs.wisc.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1869140Snilay@cs.wisc.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1879140Snilay@cs.wisc.edu uint8_t _dataSize, uint16_t _ext) : 1889140Snilay@cs.wisc.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1899140Snilay@cs.wisc.edu isMicro, isDelayed, isFirst, isLast, 1909140Snilay@cs.wisc.edu _src1, _src2, _dest, _dataSize, _ext, 1919140Snilay@cs.wisc.edu %(op_class)s) 1929140Snilay@cs.wisc.edu { 1939140Snilay@cs.wisc.edu buildMe(); 1949140Snilay@cs.wisc.edu } 1959816Sjthestness@gmail.com}}; 1969140Snilay@cs.wisc.edu 1979140Snilay@cs.wisc.edudef template MicroRegOpImmConstructor {{ 1989816Sjthestness@gmail.com 1999140Snilay@cs.wisc.edu inline void %(class_name)s::buildMe() 2009215Sandreas.hansson@arm.com { 2019140Snilay@cs.wisc.edu %(constructor)s; 2029140Snilay@cs.wisc.edu } 2039140Snilay@cs.wisc.edu 2049140Snilay@cs.wisc.edu inline %(class_name)s::%(class_name)s( 2059140Snilay@cs.wisc.edu ExtMachInst machInst, const char * instMnem, 2069140Snilay@cs.wisc.edu InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 2079140Snilay@cs.wisc.edu uint8_t _dataSize, uint16_t _ext) : 2089140Snilay@cs.wisc.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2099140Snilay@cs.wisc.edu false, false, false, false, 2109140Snilay@cs.wisc.edu _src1, _imm8, _dest, _dataSize, _ext, 2119140Snilay@cs.wisc.edu %(op_class)s) 2129140Snilay@cs.wisc.edu { 2139140Snilay@cs.wisc.edu buildMe(); 2149140Snilay@cs.wisc.edu } 2159140Snilay@cs.wisc.edu 2169140Snilay@cs.wisc.edu inline %(class_name)s::%(class_name)s( 2179140Snilay@cs.wisc.edu ExtMachInst machInst, const char * instMnem, 2189140Snilay@cs.wisc.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 2199140Snilay@cs.wisc.edu InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 2209140Snilay@cs.wisc.edu uint8_t _dataSize, uint16_t _ext) : 2219140Snilay@cs.wisc.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2229140Snilay@cs.wisc.edu isMicro, isDelayed, isFirst, isLast, 2239140Snilay@cs.wisc.edu _src1, _imm8, _dest, _dataSize, _ext, 2249140Snilay@cs.wisc.edu %(op_class)s) 2259140Snilay@cs.wisc.edu { 2269140Snilay@cs.wisc.edu buildMe(); 2279156Sandreas.hansson@arm.com } 2289140Snilay@cs.wisc.edu}}; 2299634Sjthestness@gmail.com 2309140Snilay@cs.wisc.eduoutput header {{ 2319140Snilay@cs.wisc.edu void 2329140Snilay@cs.wisc.edu divide(uint64_t dividend, uint64_t divisor, 2339140Snilay@cs.wisc.edu uint64_t "ient, uint64_t &remainder); 2349140Snilay@cs.wisc.edu 2359140Snilay@cs.wisc.edu enum SegmentSelectorCheck { 2369140Snilay@cs.wisc.edu SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck, 2379140Snilay@cs.wisc.edu SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck, 2389140Snilay@cs.wisc.edu SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck 2399140Snilay@cs.wisc.edu }; 2409140Snilay@cs.wisc.edu 2419140Snilay@cs.wisc.edu enum LongModeDescriptorType { 2429140Snilay@cs.wisc.edu LDT64 = 2, 2439140Snilay@cs.wisc.edu AvailableTSS64 = 9, 2449140Snilay@cs.wisc.edu BusyTSS64 = 0xb, 2459140Snilay@cs.wisc.edu CallGate64 = 0xc, 2469140Snilay@cs.wisc.edu IntGate64 = 0xe, 2479140Snilay@cs.wisc.edu TrapGate64 = 0xf 2489140Snilay@cs.wisc.edu }; 2499140Snilay@cs.wisc.edu}}; 2509140Snilay@cs.wisc.edu 2519140Snilay@cs.wisc.eduoutput decoder {{ 2529140Snilay@cs.wisc.edu void 2539140Snilay@cs.wisc.edu divide(uint64_t dividend, uint64_t divisor, 2549140Snilay@cs.wisc.edu uint64_t "ient, uint64_t &remainder) 2559140Snilay@cs.wisc.edu { 2569140Snilay@cs.wisc.edu //Check for divide by zero. 2579140Snilay@cs.wisc.edu if (divisor == 0) 2589606Snilay@cs.wisc.edu panic("Divide by zero!\\n"); 2599140Snilay@cs.wisc.edu //If the divisor is bigger than the dividend, don't do anything. 2609140Snilay@cs.wisc.edu if (divisor <= dividend) { 2619634Sjthestness@gmail.com //Shift the divisor so it's msb lines up with the dividend. 2629140Snilay@cs.wisc.edu int dividendMsb = findMsbSet(dividend); 2639140Snilay@cs.wisc.edu int divisorMsb = findMsbSet(divisor); 2649140Snilay@cs.wisc.edu int shift = dividendMsb - divisorMsb; 2659140Snilay@cs.wisc.edu divisor <<= shift; 2669140Snilay@cs.wisc.edu //Compute what we'll add to the quotient if the divisor isn't 2679140Snilay@cs.wisc.edu //now larger than the dividend. 2689140Snilay@cs.wisc.edu uint64_t quotientBit = 1; 2699140Snilay@cs.wisc.edu quotientBit <<= shift; 2709140Snilay@cs.wisc.edu //If we need to step back a bit (no pun intended) because the 2719140Snilay@cs.wisc.edu //divisor got too to large, do that here. This is the "or two" 2729140Snilay@cs.wisc.edu //part of one or two bit division. 2739140Snilay@cs.wisc.edu if (divisor > dividend) { 2749140Snilay@cs.wisc.edu quotientBit >>= 1; 2759140Snilay@cs.wisc.edu divisor >>= 1; 2769140Snilay@cs.wisc.edu } 2779460Ssaidi@eecs.umich.edu //Decrement the remainder and increment the quotient. 2789140Snilay@cs.wisc.edu quotient += quotientBit; 27910608Sdam.sunwoo@arm.com remainder -= divisor; 28010608Sdam.sunwoo@arm.com } 28110608Sdam.sunwoo@arm.com } 28210608Sdam.sunwoo@arm.com}}; 28310608Sdam.sunwoo@arm.com 28410608Sdam.sunwoo@arm.comlet {{ 28510608Sdam.sunwoo@arm.com # Make these empty strings so that concatenating onto 28610608Sdam.sunwoo@arm.com # them will always work. 28710608Sdam.sunwoo@arm.com header_output = "" 28810608Sdam.sunwoo@arm.com decoder_output = "" 28910608Sdam.sunwoo@arm.com exec_output = "" 29010608Sdam.sunwoo@arm.com 29110608Sdam.sunwoo@arm.com immTemplates = ( 29210608Sdam.sunwoo@arm.com MicroRegOpImmDeclare, 29310608Sdam.sunwoo@arm.com MicroRegOpImmConstructor, 29410608Sdam.sunwoo@arm.com MicroRegOpImmExecute) 29510608Sdam.sunwoo@arm.com 29610608Sdam.sunwoo@arm.com regTemplates = ( 29710608Sdam.sunwoo@arm.com MicroRegOpDeclare, 29810608Sdam.sunwoo@arm.com MicroRegOpConstructor, 29910608Sdam.sunwoo@arm.com MicroRegOpExecute) 30010608Sdam.sunwoo@arm.com 30110608Sdam.sunwoo@arm.com class RegOpMeta(type): 30210608Sdam.sunwoo@arm.com def buildCppClasses(self, name, Name, suffix, \ 30310608Sdam.sunwoo@arm.com code, flag_code, cond_check, else_code): 30410608Sdam.sunwoo@arm.com 30510608Sdam.sunwoo@arm.com # Globals to stick the output in 30610608Sdam.sunwoo@arm.com global header_output 30710608Sdam.sunwoo@arm.com global decoder_output 30810608Sdam.sunwoo@arm.com global exec_output 30910608Sdam.sunwoo@arm.com 31010608Sdam.sunwoo@arm.com # Stick all the code together so it can be searched at once 31110608Sdam.sunwoo@arm.com allCode = "|".join((code, flag_code, cond_check, else_code)) 31210608Sdam.sunwoo@arm.com 31310608Sdam.sunwoo@arm.com # If op2 is used anywhere, make register and immediate versions 31410608Sdam.sunwoo@arm.com # of this code. 31510608Sdam.sunwoo@arm.com matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?") 31610608Sdam.sunwoo@arm.com match = matcher.search(allCode) 31710608Sdam.sunwoo@arm.com if match: 31810608Sdam.sunwoo@arm.com typeQual = "" 31910608Sdam.sunwoo@arm.com if match.group("typeQual"): 32010608Sdam.sunwoo@arm.com typeQual = match.group("typeQual") 32110608Sdam.sunwoo@arm.com src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 32210608Sdam.sunwoo@arm.com self.buildCppClasses(name, Name, suffix, 32310608Sdam.sunwoo@arm.com matcher.sub(src2_name, code), 32410608Sdam.sunwoo@arm.com matcher.sub(src2_name, flag_code), 32510608Sdam.sunwoo@arm.com matcher.sub(src2_name, cond_check), 32610608Sdam.sunwoo@arm.com matcher.sub(src2_name, else_code)) 32710608Sdam.sunwoo@arm.com self.buildCppClasses(name + "i", Name, suffix + "Imm", 32810608Sdam.sunwoo@arm.com matcher.sub("imm8", code), 32910608Sdam.sunwoo@arm.com matcher.sub("imm8", flag_code), 33010608Sdam.sunwoo@arm.com matcher.sub("imm8", cond_check), 33110608Sdam.sunwoo@arm.com matcher.sub("imm8", else_code)) 33210608Sdam.sunwoo@arm.com return 33310608Sdam.sunwoo@arm.com 33410608Sdam.sunwoo@arm.com # If there's something optional to do with flags, generate 33510608Sdam.sunwoo@arm.com # a version without it and fix up this version to use it. 33610608Sdam.sunwoo@arm.com if flag_code != "" or cond_check != "true": 33710608Sdam.sunwoo@arm.com self.buildCppClasses(name, Name, suffix, 33810608Sdam.sunwoo@arm.com code, "", "true", else_code) 33910608Sdam.sunwoo@arm.com suffix = "Flags" + suffix 34010608Sdam.sunwoo@arm.com 34110608Sdam.sunwoo@arm.com # If psrc1 or psrc2 is used, we need to actually insert code to 34210608Sdam.sunwoo@arm.com # compute it. 34310608Sdam.sunwoo@arm.com matcher = re.compile("(?<!\w)psrc1(?!\w)") 34410608Sdam.sunwoo@arm.com if matcher.search(allCode): 34510608Sdam.sunwoo@arm.com code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code 34610608Sdam.sunwoo@arm.com matcher = re.compile("(?<!\w)psrc2(?!\w)") 34710608Sdam.sunwoo@arm.com if matcher.search(allCode): 34810608Sdam.sunwoo@arm.com code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code 34910608Sdam.sunwoo@arm.com # Also make available versions which do sign extension 35010608Sdam.sunwoo@arm.com matcher = re.compile("(?<!\w)spsrc1(?!\w)") 35110608Sdam.sunwoo@arm.com if matcher.search(allCode): 35210608Sdam.sunwoo@arm.com code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code 35310608Sdam.sunwoo@arm.com matcher = re.compile("(?<!\w)spsrc2(?!\w)") 35410608Sdam.sunwoo@arm.com if matcher.search(allCode): 35510608Sdam.sunwoo@arm.com code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code 35610608Sdam.sunwoo@arm.com 35710608Sdam.sunwoo@arm.com base = "X86ISA::RegOp" 35810608Sdam.sunwoo@arm.com 35910608Sdam.sunwoo@arm.com # If imm8 shows up in the code, use the immediate templates, if 36010608Sdam.sunwoo@arm.com # not, hopefully the register ones will be correct. 36110608Sdam.sunwoo@arm.com templates = regTemplates 36210608Sdam.sunwoo@arm.com matcher = re.compile("(?<!\w)imm8(?!\w)") 36310608Sdam.sunwoo@arm.com if matcher.search(allCode): 36410608Sdam.sunwoo@arm.com base += "Imm" 36510608Sdam.sunwoo@arm.com templates = immTemplates 36610608Sdam.sunwoo@arm.com 36710608Sdam.sunwoo@arm.com # Get everything ready for the substitution 36810608Sdam.sunwoo@arm.com iop = InstObjParams(name, Name + suffix, base, 36910608Sdam.sunwoo@arm.com {"code" : code, 37010608Sdam.sunwoo@arm.com "flag_code" : flag_code, 37110608Sdam.sunwoo@arm.com "cond_check" : cond_check, 37210608Sdam.sunwoo@arm.com "else_code" : else_code}) 37310608Sdam.sunwoo@arm.com 37410608Sdam.sunwoo@arm.com # Generate the actual code (finally!) 37510608Sdam.sunwoo@arm.com header_output += templates[0].subst(iop) 37610608Sdam.sunwoo@arm.com decoder_output += templates[1].subst(iop) 37710608Sdam.sunwoo@arm.com exec_output += templates[2].subst(iop) 37810608Sdam.sunwoo@arm.com 37910608Sdam.sunwoo@arm.com 38010608Sdam.sunwoo@arm.com def __new__(mcls, Name, bases, dict): 38110608Sdam.sunwoo@arm.com abstract = False 38210608Sdam.sunwoo@arm.com name = Name.lower() 38310608Sdam.sunwoo@arm.com if "abstract" in dict: 38410608Sdam.sunwoo@arm.com abstract = dict['abstract'] 38510608Sdam.sunwoo@arm.com del dict['abstract'] 38610608Sdam.sunwoo@arm.com 38710608Sdam.sunwoo@arm.com cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 38810608Sdam.sunwoo@arm.com if not abstract: 38910608Sdam.sunwoo@arm.com cls.className = Name 39010608Sdam.sunwoo@arm.com cls.base_mnemonic = name 39110608Sdam.sunwoo@arm.com code = cls.code 39210608Sdam.sunwoo@arm.com flag_code = cls.flag_code 39310608Sdam.sunwoo@arm.com cond_check = cls.cond_check 39410608Sdam.sunwoo@arm.com else_code = cls.else_code 39510608Sdam.sunwoo@arm.com 39610608Sdam.sunwoo@arm.com # Set up the C++ classes 39710608Sdam.sunwoo@arm.com mcls.buildCppClasses(cls, name, Name, "", 39810608Sdam.sunwoo@arm.com code, flag_code, cond_check, else_code) 39910608Sdam.sunwoo@arm.com 40010608Sdam.sunwoo@arm.com # Hook into the microassembler dict 40110608Sdam.sunwoo@arm.com global microopClasses 40210608Sdam.sunwoo@arm.com microopClasses[name] = cls 40310608Sdam.sunwoo@arm.com 4049151Satgutier@umich.edu allCode = "|".join((code, flag_code, cond_check, else_code)) 4059151Satgutier@umich.edu 4069151Satgutier@umich.edu # If op2 is used anywhere, make register and immediate versions 4079151Satgutier@umich.edu # of this code. 4089151Satgutier@umich.edu matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 4099151Satgutier@umich.edu if matcher.search(allCode): 4109151Satgutier@umich.edu microopClasses[name + 'i'] = cls 4119460Ssaidi@eecs.umich.edu return cls 4129151Satgutier@umich.edu 4139521SAndreas.Sandberg@ARM.com 4149151Satgutier@umich.edu class RegOp(X86Microop): 4159151Satgutier@umich.edu __metaclass__ = RegOpMeta 4169151Satgutier@umich.edu # This class itself doesn't act as a microop 4179151Satgutier@umich.edu abstract = True 4189151Satgutier@umich.edu 4199151Satgutier@umich.edu # Default template parameter values 4209151Satgutier@umich.edu flag_code = "" 4219151Satgutier@umich.edu cond_check = "true" 4229460Ssaidi@eecs.umich.edu else_code = ";" 4239151Satgutier@umich.edu 4243481Shsul@eecs.umich.edu def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 4253395Shsul@eecs.umich.edu self.dest = dest 4263395Shsul@eecs.umich.edu self.src1 = src1 4275211Ssaidi@eecs.umich.edu self.op2 = op2 4285211Ssaidi@eecs.umich.edu self.flags = flags 4293395Shsul@eecs.umich.edu self.dataSize = dataSize 4303395Shsul@eecs.umich.edu if flags is None: 4313395Shsul@eecs.umich.edu self.ext = 0 4325370Ssaidi@eecs.umich.edu else: 4336654Snate@binkert.org if not isinstance(flags, (list, tuple)): 4345370Ssaidi@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 4355371Shsul@eecs.umich.edu self.ext = " | ".join(flags) 4366654Snate@binkert.org self.className += "Flags" 4375370Ssaidi@eecs.umich.edu 4389151Satgutier@umich.edu def getAllocator(self, *microFlags): 4399151Satgutier@umich.edu className = self.className 4409151Satgutier@umich.edu if self.mnemonic == self.base_mnemonic + 'i': 4419151Satgutier@umich.edu className += "Imm" 4429151Satgutier@umich.edu allocator = '''new %(class_name)s(machInst, macrocodeBlock 4439151Satgutier@umich.edu %(flags)s, %(src1)s, %(op2)s, %(dest)s, 4443395Shsul@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 4453481Shsul@eecs.umich.edu "class_name" : className, 4463481Shsul@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 4478318Sksewell@umich.edu "src1" : self.src1, "op2" : self.op2, 4486144Sksewell@umich.edu "dest" : self.dest, 4498311Sksewell@umich.edu "dataSize" : self.dataSize, 4506144Sksewell@umich.edu "ext" : self.ext} 4516641Sksewell@umich.edu return allocator 4526641Sksewell@umich.edu 4536641Sksewell@umich.edu class LogicRegOp(RegOp): 4546641Sksewell@umich.edu abstract = True 4553481Shsul@eecs.umich.edu flag_code = ''' 4569433SAndreas.Sandberg@ARM.com //Don't have genFlags handle the OF or CF bits 4573481Shsul@eecs.umich.edu uint64_t mask = CFBit | ECFBit | OFBit; 4583481Shsul@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); 4593481Shsul@eecs.umich.edu //If a logic microop wants to set these, it wants to set them to 0. 4605361Srstrong@cs.ucsd.edu ccFlagBits &= ~(CFBit & ext); 4615369Ssaidi@eecs.umich.edu ccFlagBits &= ~(ECFBit & ext); 46211251Sradhika.jagtap@ARM.com ccFlagBits &= ~(OFBit & ext); 4638803Sgblack@eecs.umich.edu ''' 4649793Sakash.bagdia@arm.com 46511251Sradhika.jagtap@ARM.com class FlagRegOp(RegOp): 46611251Sradhika.jagtap@ARM.com abstract = True 46712374Saustinharris@utexas.edu flag_code = \ 4685369Ssaidi@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" 4698311Sksewell@umich.edu 4708311Sksewell@umich.edu class SubRegOp(RegOp): 4718887Sgeoffrey.blake@arm.com abstract = True 4728887Sgeoffrey.blake@arm.com flag_code = \ 4738887Sgeoffrey.blake@arm.com "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 4743481Shsul@eecs.umich.edu 47511251Sradhika.jagtap@ARM.com class CondRegOp(RegOp): 47611251Sradhika.jagtap@ARM.com abstract = True 47711251Sradhika.jagtap@ARM.com cond_check = "checkCondition(ccFlagBits, ext)" 47811251Sradhika.jagtap@ARM.com 47911251Sradhika.jagtap@ARM.com class RdRegOp(RegOp): 4805311Ssaidi@eecs.umich.edu abstract = True 4813481Shsul@eecs.umich.edu def __init__(self, dest, src1=None, dataSize="env.dataSize"): 4823395Shsul@eecs.umich.edu if not src1: 4839151Satgutier@umich.edu src1 = dest 4849518SAndreas.Sandberg@ARM.com super(RdRegOp, self).__init__(dest, src1, \ 4859518SAndreas.Sandberg@ARM.com "InstRegIndex(NUM_INTREGS)", None, dataSize) 4869518SAndreas.Sandberg@ARM.com 4879518SAndreas.Sandberg@ARM.com class WrRegOp(RegOp): 4889518SAndreas.Sandberg@ARM.com abstract = True 4899518SAndreas.Sandberg@ARM.com def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 4909518SAndreas.Sandberg@ARM.com super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ 4919518SAndreas.Sandberg@ARM.com src1, src2, flags, dataSize) 4929151Satgutier@umich.edu 4939518SAndreas.Sandberg@ARM.com class Add(FlagRegOp): 4949518SAndreas.Sandberg@ARM.com code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' 4959151Satgutier@umich.edu 4969151Satgutier@umich.edu class Or(LogicRegOp): 4979151Satgutier@umich.edu code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' 4989151Satgutier@umich.edu 4999793Sakash.bagdia@arm.com class Adc(FlagRegOp): 50012374Saustinharris@utexas.edu code = ''' 5019151Satgutier@umich.edu CCFlagBits flags = ccFlagBits; 5029151Satgutier@umich.edu DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize); 5039151Satgutier@umich.edu ''' 5049151Satgutier@umich.edu 5059151Satgutier@umich.edu class Sbb(SubRegOp): 5069151Satgutier@umich.edu code = ''' 5079151Satgutier@umich.edu CCFlagBits flags = ccFlagBits; 5089151Satgutier@umich.edu DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize); 5099151Satgutier@umich.edu ''' 5109151Satgutier@umich.edu 5119151Satgutier@umich.edu class And(LogicRegOp): 5129151Satgutier@umich.edu code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)' 5139151Satgutier@umich.edu 5149151Satgutier@umich.edu class Sub(SubRegOp): 5159151Satgutier@umich.edu code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)' 5169151Satgutier@umich.edu 5173395Shsul@eecs.umich.edu class Xor(LogicRegOp): 5189433SAndreas.Sandberg@ARM.com code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)' 5193395Shsul@eecs.umich.edu 5209433SAndreas.Sandberg@ARM.com class Mul1s(WrRegOp): 5213395Shsul@eecs.umich.edu code = ''' 5223478Shsul@eecs.umich.edu ProdLow = psrc1 * op2; 5233395Shsul@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5243395Shsul@eecs.umich.edu uint64_t shifter = (1ULL << halfSize); 5253478Shsul@eecs.umich.edu uint64_t hiResult; 5268803Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 / shifter; 5278803Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5289793Sakash.bagdia@arm.com uint64_t psrc2_h = op2 / shifter; 5299793Sakash.bagdia@arm.com uint64_t psrc2_l = op2 & mask(halfSize); 53012374Saustinharris@utexas.edu hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 53112374Saustinharris@utexas.edu ((psrc1_l * psrc2_l) / shifter)) /shifter) + 5323480Shsul@eecs.umich.edu psrc1_h * psrc2_h; 5335361Srstrong@cs.ucsd.edu if (spsrc1 < 0) 5345369Ssaidi@eecs.umich.edu hiResult -= op2; 5355361Srstrong@cs.ucsd.edu int64_t bigSop2 = sop2; 5365361Srstrong@cs.ucsd.edu if (bigSop2 < 0) 5375361Srstrong@cs.ucsd.edu hiResult -= psrc1; 5385369Ssaidi@eecs.umich.edu ProdHi = hiResult; 5395361Srstrong@cs.ucsd.edu ''' 5405361Srstrong@cs.ucsd.edu 5415378Ssaidi@eecs.umich.edu class Mul1u(WrRegOp): 5426654Snate@binkert.org code = ''' 5435361Srstrong@cs.ucsd.edu ProdLow = psrc1 * op2; 5445361Srstrong@cs.ucsd.edu int halfSize = (dataSize * 8) / 2; 5455361Srstrong@cs.ucsd.edu uint64_t shifter = (1ULL << halfSize); 5465361Srstrong@cs.ucsd.edu uint64_t psrc1_h = psrc1 / shifter; 5475361Srstrong@cs.ucsd.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5485361Srstrong@cs.ucsd.edu uint64_t psrc2_h = op2 / shifter; 5495361Srstrong@cs.ucsd.edu uint64_t psrc2_l = op2 & mask(halfSize); 5505361Srstrong@cs.ucsd.edu ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 5515361Srstrong@cs.ucsd.edu ((psrc1_l * psrc2_l) / shifter)) / shifter) + 5525361Srstrong@cs.ucsd.edu psrc1_h * psrc2_h; 5535361Srstrong@cs.ucsd.edu ''' 5548311Sksewell@umich.edu 5558311Sksewell@umich.edu class Mulel(RdRegOp): 5565353Svilas.sridharan@gmail.com code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 5578887Sgeoffrey.blake@arm.com 5588887Sgeoffrey.blake@arm.com class Muleh(RdRegOp): 5598887Sgeoffrey.blake@arm.com def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 5608887Sgeoffrey.blake@arm.com if not src1: 5618887Sgeoffrey.blake@arm.com src1 = dest 5628211Satgutier@umich.edu super(RdRegOp, self).__init__(dest, src1, \ 5638211Satgutier@umich.edu "InstRegIndex(NUM_INTREGS)", flags, dataSize) 5648211Satgutier@umich.edu code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 5658211Satgutier@umich.edu flag_code = ''' 5663395Shsul@eecs.umich.edu if (ProdHi) 5675361Srstrong@cs.ucsd.edu ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 5685369Ssaidi@eecs.umich.edu else 5695361Srstrong@cs.ucsd.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 5705361Srstrong@cs.ucsd.edu ''' 5715361Srstrong@cs.ucsd.edu 5725361Srstrong@cs.ucsd.edu # One or two bit divide 5735361Srstrong@cs.ucsd.edu class Div1(WrRegOp): 5745378Ssaidi@eecs.umich.edu code = ''' 5756654Snate@binkert.org //These are temporaries so that modifying them later won't make 5765369Ssaidi@eecs.umich.edu //the ISA parser think they're also sources. 5775361Srstrong@cs.ucsd.edu uint64_t quotient = 0; 5785361Srstrong@cs.ucsd.edu uint64_t remainder = psrc1; 5795361Srstrong@cs.ucsd.edu //Similarly, this is a temporary so changing it doesn't make it 5805361Srstrong@cs.ucsd.edu //a source. 5815361Srstrong@cs.ucsd.edu uint64_t divisor = op2; 5825361Srstrong@cs.ucsd.edu //This is a temporary just for consistency and clarity. 5835361Srstrong@cs.ucsd.edu uint64_t dividend = remainder; 5845361Srstrong@cs.ucsd.edu //Do the division. 5855361Srstrong@cs.ucsd.edu divide(dividend, divisor, quotient, remainder); 5865361Srstrong@cs.ucsd.edu //Record the final results. 58710608Sdam.sunwoo@arm.com Remainder = remainder; 58810608Sdam.sunwoo@arm.com Quotient = quotient; 58910608Sdam.sunwoo@arm.com Divisor = divisor; 5907531Ssteve.reinhardt@amd.com ''' 5919816Sjthestness@gmail.com 5929816Sjthestness@gmail.com # Step divide 5937531Ssteve.reinhardt@amd.com class Div2(RegOp): 5943395Shsul@eecs.umich.edu code = ''' 59510757SCurtis.Dunham@arm.com uint64_t dividend = Remainder; 59610757SCurtis.Dunham@arm.com uint64_t divisor = Divisor; 59710757SCurtis.Dunham@arm.com uint64_t quotient = Quotient; 59810757SCurtis.Dunham@arm.com uint64_t remainder = dividend; 59910757SCurtis.Dunham@arm.com int remaining = op2; 60010757SCurtis.Dunham@arm.com //If we overshot, do nothing. This lets us unrool division loops a 60110757SCurtis.Dunham@arm.com //little. 6029816Sjthestness@gmail.com if (remaining) { 6039816Sjthestness@gmail.com //Shift in bits from the low order portion of the dividend 6049816Sjthestness@gmail.com while(dividend < divisor && remaining) { 6059816Sjthestness@gmail.com dividend = (dividend << 1) | bits(SrcReg1, remaining - 1); 6069816Sjthestness@gmail.com quotient <<= 1; 6079816Sjthestness@gmail.com remaining--; 6089816Sjthestness@gmail.com } 6099816Sjthestness@gmail.com remainder = dividend; 6109816Sjthestness@gmail.com //Do the division. 6119816Sjthestness@gmail.com divide(dividend, divisor, quotient, remainder); 6129816Sjthestness@gmail.com } 6139816Sjthestness@gmail.com //Keep track of how many bits there are still to pull in. 6149816Sjthestness@gmail.com DestReg = merge(DestReg, remaining, dataSize); 6159816Sjthestness@gmail.com //Record the final results 6169816Sjthestness@gmail.com Remainder = remainder; 6179816Sjthestness@gmail.com Quotient = quotient; 6189816Sjthestness@gmail.com ''' 6199867Sjthestness@gmail.com flag_code = ''' 6209867Sjthestness@gmail.com if (DestReg == 0) 6219867Sjthestness@gmail.com ccFlagBits = ccFlagBits | (ext & EZFBit); 6229867Sjthestness@gmail.com else 6239867Sjthestness@gmail.com ccFlagBits = ccFlagBits & ~(ext & EZFBit); 6249816Sjthestness@gmail.com ''' 6259816Sjthestness@gmail.com 6269816Sjthestness@gmail.com class Divq(RdRegOp): 6279816Sjthestness@gmail.com code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 6289816Sjthestness@gmail.com 6299816Sjthestness@gmail.com class Divr(RdRegOp): 6309816Sjthestness@gmail.com code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 6319816Sjthestness@gmail.com 6329816Sjthestness@gmail.com class Mov(CondRegOp): 6339816Sjthestness@gmail.com code = 'DestReg = merge(SrcReg1, op2, dataSize)' 6349816Sjthestness@gmail.com else_code = 'DestReg=DestReg;' 6359816Sjthestness@gmail.com 6369816Sjthestness@gmail.com # Shift instructions 6373481Shsul@eecs.umich.edu 6385361Srstrong@cs.ucsd.edu class Sll(RegOp): 6395361Srstrong@cs.ucsd.edu code = ''' 6405361Srstrong@cs.ucsd.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6415361Srstrong@cs.ucsd.edu DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 6425361Srstrong@cs.ucsd.edu ''' 6435361Srstrong@cs.ucsd.edu flag_code = ''' 6445361Srstrong@cs.ucsd.edu // If the shift amount is zero, no flags should be modified. 6455361Srstrong@cs.ucsd.edu if (shiftAmt) { 6465361Srstrong@cs.ucsd.edu //Zero out any flags we might modify. This way we only have to 6475361Srstrong@cs.ucsd.edu //worry about setting them. 6485361Srstrong@cs.ucsd.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 6497766Sgblack@eecs.umich.edu int CFBits = 0; 6503395Shsul@eecs.umich.edu //Figure out if we -would- set the CF bits if requested. 6519521SAndreas.Sandberg@ARM.com if (shiftAmt <= dataSize * 8 && 6523395Shsul@eecs.umich.edu bits(SrcReg1, dataSize * 8 - shiftAmt)) { 6533481Shsul@eecs.umich.edu CFBits = 1; 6545361Srstrong@cs.ucsd.edu } 6555361Srstrong@cs.ucsd.edu //If some combination of the CF bits need to be set, set them. 6565361Srstrong@cs.ucsd.edu if ((ext & (CFBit | ECFBit)) && CFBits) 6575361Srstrong@cs.ucsd.edu ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 6585361Srstrong@cs.ucsd.edu //Figure out what the OF bit should be. 6595361Srstrong@cs.ucsd.edu if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) 6605361Srstrong@cs.ucsd.edu ccFlagBits = ccFlagBits | OFBit; 6619151Satgutier@umich.edu //Use the regular mechanisms to calculate the other flags. 6627766Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 6635361Srstrong@cs.ucsd.edu DestReg, psrc1, op2); 6645361Srstrong@cs.ucsd.edu } 6659521SAndreas.Sandberg@ARM.com ''' 6663395Shsul@eecs.umich.edu 6677489Ssteve.reinhardt@amd.com class Srl(RegOp): 6687489Ssteve.reinhardt@amd.com code = ''' 6697489Ssteve.reinhardt@amd.com uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6707489Ssteve.reinhardt@amd.com // Because what happens to the bits shift -in- on a right shift 67110608Sdam.sunwoo@arm.com // is not defined in the C/C++ standard, we have to mask them out 67210608Sdam.sunwoo@arm.com // to be sure they're zero. 67310608Sdam.sunwoo@arm.com uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 6747489Ssteve.reinhardt@amd.com DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 6757489Ssteve.reinhardt@amd.com ''' 6767489Ssteve.reinhardt@amd.com flag_code = ''' 6777489Ssteve.reinhardt@amd.com // If the shift amount is zero, no flags should be modified. 6787489Ssteve.reinhardt@amd.com if (shiftAmt) { 6795369Ssaidi@eecs.umich.edu //Zero out any flags we might modify. This way we only have to 6809140Snilay@cs.wisc.edu //worry about setting them. 6819140Snilay@cs.wisc.edu ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 6829140Snilay@cs.wisc.edu //If some combination of the CF bits need to be set, set them. 6839140Snilay@cs.wisc.edu if ((ext & (CFBit | ECFBit)) && 6849606Snilay@cs.wisc.edu shiftAmt <= dataSize * 8 && 68510608Sdam.sunwoo@arm.com bits(SrcReg1, shiftAmt - 1)) { 68610608Sdam.sunwoo@arm.com ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 68710608Sdam.sunwoo@arm.com } 68810608Sdam.sunwoo@arm.com //Figure out what the OF bit should be. 68910608Sdam.sunwoo@arm.com if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) 69010608Sdam.sunwoo@arm.com ccFlagBits = ccFlagBits | OFBit; 69110608Sdam.sunwoo@arm.com //Use the regular mechanisms to calculate the other flags. 69210608Sdam.sunwoo@arm.com ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 69310608Sdam.sunwoo@arm.com DestReg, psrc1, op2); 6949140Snilay@cs.wisc.edu } 6959151Satgutier@umich.edu ''' 6969151Satgutier@umich.edu 6979151Satgutier@umich.edu class Sra(RegOp): 6989151Satgutier@umich.edu code = ''' 6999140Snilay@cs.wisc.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 7009140Snilay@cs.wisc.edu // Because what happens to the bits shift -in- on a right shift 7019151Satgutier@umich.edu // is not defined in the C/C++ standard, we have to sign extend 7029460Ssaidi@eecs.umich.edu // them manually to be sure. 7039151Satgutier@umich.edu uint64_t arithMask = (shiftAmt == 0) ? 0 : 7049151Satgutier@umich.edu -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 7059460Ssaidi@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 7063395Shsul@eecs.umich.edu ''' 7079460Ssaidi@eecs.umich.edu flag_code = ''' 7086776SBrad.Beckmann@amd.com // If the shift amount is zero, no flags should be modified. 7097525Ssteve.reinhardt@amd.com if (shiftAmt) { 7109457Svilanova@ac.upc.edu //Zero out any flags we might modify. This way we only have to 7119494Sandreas@sandberg.pp.se //worry about setting them. 7129494Sandreas@sandberg.pp.se ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 713 //If some combination of the CF bits need to be set, set them. 714 uint8_t effectiveShift = 715 (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8); 716 if ((ext & (CFBit | ECFBit)) && 717 bits(SrcReg1, effectiveShift - 1)) { 718 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 719 } 720 //Use the regular mechanisms to calculate the other flags. 721 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 722 DestReg, psrc1, op2); 723 } 724 ''' 725 726 class Ror(RegOp): 727 code = ''' 728 uint8_t shiftAmt = 729 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 730 uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 731 if(realShiftAmt) 732 { 733 uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt); 734 uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt); 735 DestReg = merge(DestReg, top | bottom, dataSize); 736 } 737 else 738 DestReg = merge(DestReg, DestReg, dataSize); 739 ''' 740 flag_code = ''' 741 // If the shift amount is zero, no flags should be modified. 742 if (shiftAmt) { 743 //Zero out any flags we might modify. This way we only have to 744 //worry about setting them. 745 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 746 //Find the most and second most significant bits of the result. 747 int msb = bits(DestReg, dataSize * 8 - 1); 748 int smsb = bits(DestReg, dataSize * 8 - 2); 749 //If some combination of the CF bits need to be set, set them. 750 if ((ext & (CFBit | ECFBit)) && msb) 751 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 752 //Figure out what the OF bit should be. 753 if ((ext & OFBit) && (msb ^ smsb)) 754 ccFlagBits = ccFlagBits | OFBit; 755 //Use the regular mechanisms to calculate the other flags. 756 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 757 DestReg, psrc1, op2); 758 } 759 ''' 760 761 class Rcr(RegOp): 762 code = ''' 763 uint8_t shiftAmt = 764 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 765 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 766 if(realShiftAmt) 767 { 768 CCFlagBits flags = ccFlagBits; 769 uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt); 770 if (realShiftAmt > 1) 771 top |= psrc1 << (dataSize * 8 - realShiftAmt + 1); 772 uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt); 773 DestReg = merge(DestReg, top | bottom, dataSize); 774 } 775 else 776 DestReg = merge(DestReg, DestReg, dataSize); 777 ''' 778 flag_code = ''' 779 // If the shift amount is zero, no flags should be modified. 780 if (shiftAmt) { 781 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 782 //Zero out any flags we might modify. This way we only have to 783 //worry about setting them. 784 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 785 //Figure out what the OF bit should be. 786 if ((ext & OFBit) && (origCFBit ^ 787 bits(SrcReg1, dataSize * 8 - 1))) { 788 ccFlagBits = ccFlagBits | OFBit; 789 } 790 //If some combination of the CF bits need to be set, set them. 791 if ((ext & (CFBit | ECFBit)) && 792 (realShiftAmt == 0) ? origCFBit : 793 bits(SrcReg1, realShiftAmt - 1)) { 794 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 795 } 796 //Use the regular mechanisms to calculate the other flags. 797 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 798 DestReg, psrc1, op2); 799 } 800 ''' 801 802 class Rol(RegOp): 803 code = ''' 804 uint8_t shiftAmt = 805 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 806 uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 807 if(realShiftAmt) 808 { 809 uint64_t top = psrc1 << realShiftAmt; 810 uint64_t bottom = 811 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt); 812 DestReg = merge(DestReg, top | bottom, dataSize); 813 } 814 else 815 DestReg = merge(DestReg, DestReg, dataSize); 816 ''' 817 flag_code = ''' 818 // If the shift amount is zero, no flags should be modified. 819 if (shiftAmt) { 820 //Zero out any flags we might modify. This way we only have to 821 //worry about setting them. 822 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 823 //The CF bits, if set, would be set to the lsb of the result. 824 int lsb = DestReg & 0x1; 825 int msb = bits(DestReg, dataSize * 8 - 1); 826 //If some combination of the CF bits need to be set, set them. 827 if ((ext & (CFBit | ECFBit)) && lsb) 828 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 829 //Figure out what the OF bit should be. 830 if ((ext & OFBit) && (msb ^ lsb)) 831 ccFlagBits = ccFlagBits | OFBit; 832 //Use the regular mechanisms to calculate the other flags. 833 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 834 DestReg, psrc1, op2); 835 } 836 ''' 837 838 class Rcl(RegOp): 839 code = ''' 840 uint8_t shiftAmt = 841 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 842 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 843 if(realShiftAmt) 844 { 845 CCFlagBits flags = ccFlagBits; 846 uint64_t top = psrc1 << realShiftAmt; 847 uint64_t bottom = flags.cf << (realShiftAmt - 1); 848 if(shiftAmt > 1) 849 bottom |= 850 bits(psrc1, dataSize * 8 - 1, 851 dataSize * 8 - realShiftAmt + 1); 852 DestReg = merge(DestReg, top | bottom, dataSize); 853 } 854 else 855 DestReg = merge(DestReg, DestReg, dataSize); 856 ''' 857 flag_code = ''' 858 // If the shift amount is zero, no flags should be modified. 859 if (shiftAmt) { 860 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 861 //Zero out any flags we might modify. This way we only have to 862 //worry about setting them. 863 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 864 int msb = bits(DestReg, dataSize * 8 - 1); 865 int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt); 866 //If some combination of the CF bits need to be set, set them. 867 if ((ext & (CFBit | ECFBit)) && 868 (realShiftAmt == 0) ? origCFBit : CFBits) 869 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 870 //Figure out what the OF bit should be. 871 if ((ext & OFBit) && (msb ^ CFBits)) 872 ccFlagBits = ccFlagBits | OFBit; 873 //Use the regular mechanisms to calculate the other flags. 874 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 875 DestReg, psrc1, op2); 876 } 877 ''' 878 879 class Wrip(WrRegOp, CondRegOp): 880 code = 'RIP = psrc1 + sop2 + CSBase' 881 else_code="RIP = RIP;" 882 883 class Wruflags(WrRegOp): 884 code = 'ccFlagBits = psrc1 ^ op2' 885 886 class Wrflags(WrRegOp): 887 code = ''' 888 MiscReg newFlags = psrc1 ^ op2; 889 MiscReg userFlagMask = 0xDD5; 890 // Get only the user flags 891 ccFlagBits = newFlags & userFlagMask; 892 // Get everything else 893 nccFlagBits = newFlags & ~userFlagMask; 894 ''' 895 896 class Rdip(RdRegOp): 897 code = 'DestReg = RIP - CSBase' 898 899 class Ruflags(RdRegOp): 900 code = 'DestReg = ccFlagBits' 901 902 class Rflags(RdRegOp): 903 code = 'DestReg = ccFlagBits | nccFlagBits' 904 905 class Ruflag(RegOp): 906 code = ''' 907 int flag = bits(ccFlagBits, imm8); 908 DestReg = merge(DestReg, flag, dataSize); 909 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 910 (ccFlagBits & ~EZFBit); 911 ''' 912 def __init__(self, dest, imm, flags=None, \ 913 dataSize="env.dataSize"): 914 super(Ruflag, self).__init__(dest, \ 915 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 916 917 class Rflag(RegOp): 918 code = ''' 919 MiscReg flagMask = 0x3F7FDD5; 920 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 921 int flag = bits(flags, imm8); 922 DestReg = merge(DestReg, flag, dataSize); 923 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 924 (ccFlagBits & ~EZFBit); 925 ''' 926 def __init__(self, dest, imm, flags=None, \ 927 dataSize="env.dataSize"): 928 super(Rflag, self).__init__(dest, \ 929 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 930 931 class Sext(RegOp): 932 code = ''' 933 IntReg val = psrc1; 934 // Mask the bit position so that it wraps. 935 int bitPos = op2 & (dataSize * 8 - 1); 936 int sign_bit = bits(val, bitPos, bitPos); 937 uint64_t maskVal = mask(bitPos+1); 938 val = sign_bit ? (val | ~maskVal) : (val & maskVal); 939 DestReg = merge(DestReg, val, dataSize); 940 ''' 941 flag_code = ''' 942 if (!sign_bit) 943 ccFlagBits = ccFlagBits & 944 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit)); 945 else 946 ccFlagBits = ccFlagBits | 947 (ext & (CFBit | ECFBit | ZFBit | EZFBit)); 948 ''' 949 950 class Zext(RegOp): 951 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' 952 953 class Rddr(RegOp): 954 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 955 super(Rddr, self).__init__(dest, \ 956 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 957 code = ''' 958 CR4 cr4 = CR4Op; 959 DR7 dr7 = DR7Op; 960 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 961 fault = new InvalidOpcode(); 962 } else if (dr7.gd) { 963 fault = new DebugException(); 964 } else { 965 DestReg = merge(DestReg, DebugSrc1, dataSize); 966 } 967 ''' 968 969 class Wrdr(RegOp): 970 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 971 super(Wrdr, self).__init__(dest, \ 972 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 973 code = ''' 974 CR4 cr4 = CR4Op; 975 DR7 dr7 = DR7Op; 976 if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { 977 fault = new InvalidOpcode(); 978 } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) && 979 machInst.mode.mode == LongMode) { 980 fault = new GeneralProtection(0); 981 } else if (dr7.gd) { 982 fault = new DebugException(); 983 } else { 984 DebugDest = psrc1; 985 } 986 ''' 987 988 class Rdcr(RegOp): 989 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 990 super(Rdcr, self).__init__(dest, \ 991 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 992 code = ''' 993 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 994 fault = new InvalidOpcode(); 995 } else { 996 DestReg = merge(DestReg, ControlSrc1, dataSize); 997 } 998 ''' 999 1000 class Wrcr(RegOp): 1001 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1002 super(Wrcr, self).__init__(dest, \ 1003 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1004 code = ''' 1005 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 1006 fault = new InvalidOpcode(); 1007 } else { 1008 // There are *s in the line below so it doesn't confuse the 1009 // parser. They may be unnecessary. 1010 //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 1011 MiscReg newVal = psrc1; 1012 1013 // Check for any modifications that would cause a fault. 1014 switch(dest) { 1015 case 0: 1016 { 1017 Efer efer = EferOp; 1018 CR0 cr0 = newVal; 1019 CR4 oldCr4 = CR4Op; 1020 if (bits(newVal, 63, 32) || 1021 (!cr0.pe && cr0.pg) || 1022 (!cr0.cd && cr0.nw) || 1023 (cr0.pg && efer.lme && !oldCr4.pae)) 1024 fault = new GeneralProtection(0); 1025 } 1026 break; 1027 case 2: 1028 break; 1029 case 3: 1030 break; 1031 case 4: 1032 { 1033 CR4 cr4 = newVal; 1034 // PAE can't be disabled in long mode. 1035 if (bits(newVal, 63, 11) || 1036 (machInst.mode.mode == LongMode && !cr4.pae)) 1037 fault = new GeneralProtection(0); 1038 } 1039 break; 1040 case 8: 1041 { 1042 if (bits(newVal, 63, 4)) 1043 fault = new GeneralProtection(0); 1044 } 1045 default: 1046 panic("Unrecognized control register %d.\\n", dest); 1047 } 1048 ControlDest = newVal; 1049 } 1050 ''' 1051 1052 # Microops for manipulating segmentation registers 1053 class SegOp(CondRegOp): 1054 abstract = True 1055 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1056 super(SegOp, self).__init__(dest, \ 1057 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1058 1059 class Wrbase(SegOp): 1060 code = ''' 1061 SegBaseDest = psrc1; 1062 ''' 1063 1064 class Wrlimit(SegOp): 1065 code = ''' 1066 SegLimitDest = psrc1; 1067 ''' 1068 1069 class Wrsel(SegOp): 1070 code = ''' 1071 SegSelDest = psrc1; 1072 ''' 1073 1074 class WrAttr(SegOp): 1075 code = ''' 1076 SegAttrDest = psrc1; 1077 ''' 1078 1079 class Rdbase(SegOp): 1080 code = ''' 1081 DestReg = merge(DestReg, SegBaseSrc1, dataSize); 1082 ''' 1083 1084 class Rdlimit(SegOp): 1085 code = ''' 1086 DestReg = merge(DestReg, SegLimitSrc1, dataSize); 1087 ''' 1088 1089 class RdAttr(SegOp): 1090 code = ''' 1091 DestReg = merge(DestReg, SegAttrSrc1, dataSize); 1092 ''' 1093 1094 class Rdsel(SegOp): 1095 code = ''' 1096 DestReg = merge(DestReg, SegSelSrc1, dataSize); 1097 ''' 1098 1099 class Rdval(RegOp): 1100 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1101 super(Rdval, self).__init__(dest, src1, \ 1102 "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1103 code = ''' 1104 DestReg = MiscRegSrc1; 1105 ''' 1106 1107 class Wrval(RegOp): 1108 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1109 super(Wrval, self).__init__(dest, src1, \ 1110 "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1111 code = ''' 1112 MiscRegDest = SrcReg1; 1113 ''' 1114 1115 class Chks(RegOp): 1116 def __init__(self, dest, src1, src2=0, 1117 flags=None, dataSize="env.dataSize"): 1118 super(Chks, self).__init__(dest, 1119 src1, src2, flags, dataSize) 1120 code = ''' 1121 // The selector is in source 1 and can be at most 16 bits. 1122 SegSelector selector = DestReg; 1123 SegDescriptor desc = SrcReg1; 1124 HandyM5Reg m5reg = M5Reg; 1125 1126 switch (imm8) 1127 { 1128 case SegNoCheck: 1129 break; 1130 case SegCSCheck: 1131 // Make sure it's the right type 1132 if (desc.s == 0 || desc.type.codeOrData != 1) { 1133 fault = new GeneralProtection(0); 1134 } else if (m5reg.cpl != desc.dpl) { 1135 fault = new GeneralProtection(0); 1136 } 1137 break; 1138 case SegCallGateCheck: 1139 panic("CS checks for far calls/jumps through call gates" 1140 "not implemented.\\n"); 1141 break; 1142 case SegSoftIntGateCheck: 1143 // Check permissions. 1144 if (desc.dpl < m5reg.cpl) { 1145 fault = new GeneralProtection(selector); 1146 break; 1147 } 1148 // Fall through on purpose 1149 case SegIntGateCheck: 1150 // Make sure the gate's the right type. 1151 if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) || 1152 ((desc.type & 0x6) != 0x6)) { 1153 fault = new GeneralProtection(0); 1154 } 1155 break; 1156 case SegSSCheck: 1157 if (selector.si || selector.ti) { 1158 if (!desc.p) { 1159 fault = new StackFault(selector); 1160 } 1161 } else { 1162 if ((m5reg.submode != SixtyFourBitMode || 1163 m5reg.cpl == 3) || 1164 !(desc.s == 1 && 1165 desc.type.codeOrData == 0 && desc.type.w) || 1166 (desc.dpl != m5reg.cpl) || 1167 (selector.rpl != m5reg.cpl)) { 1168 fault = new GeneralProtection(selector); 1169 } 1170 } 1171 break; 1172 case SegIretCheck: 1173 { 1174 if ((!selector.si && !selector.ti) || 1175 (selector.rpl < m5reg.cpl) || 1176 !(desc.s == 1 && desc.type.codeOrData == 1) || 1177 (!desc.type.c && desc.dpl != selector.rpl) || 1178 (desc.type.c && desc.dpl > selector.rpl)) { 1179 fault = new GeneralProtection(selector); 1180 } else if (!desc.p) { 1181 fault = new SegmentNotPresent(selector); 1182 } 1183 break; 1184 } 1185 case SegIntCSCheck: 1186 if (m5reg.mode == LongMode) { 1187 if (desc.l != 1 || desc.d != 0) { 1188 fault = new GeneralProtection(selector); 1189 } 1190 } else { 1191 panic("Interrupt CS checks not implemented " 1192 "in legacy mode.\\n"); 1193 } 1194 break; 1195 case SegTRCheck: 1196 if (!selector.si || selector.ti) { 1197 fault = new GeneralProtection(selector); 1198 } 1199 break; 1200 case SegTSSCheck: 1201 if (!desc.p) { 1202 fault = new SegmentNotPresent(selector); 1203 } else if (!(desc.type == 0x9 || 1204 (desc.type == 1 && 1205 m5reg.mode != LongMode))) { 1206 fault = new GeneralProtection(selector); 1207 } 1208 break; 1209 case SegInGDTCheck: 1210 if (selector.ti) { 1211 fault = new GeneralProtection(selector); 1212 } 1213 break; 1214 case SegLDTCheck: 1215 if (!desc.p) { 1216 fault = new SegmentNotPresent(selector); 1217 } else if (desc.type != 0x2) { 1218 fault = new GeneralProtection(selector); 1219 } 1220 break; 1221 default: 1222 panic("Undefined segment check type.\\n"); 1223 } 1224 ''' 1225 flag_code = ''' 1226 // Check for a NULL selector and set ZF,EZF appropriately. 1227 ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit)); 1228 if (!selector.si && !selector.ti) 1229 ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit)); 1230 ''' 1231 1232 class Wrdh(RegOp): 1233 code = ''' 1234 SegDescriptor desc = SrcReg1; 1235 1236 uint64_t target = bits(SrcReg2, 31, 0) << 32; 1237 switch(desc.type) { 1238 case LDT64: 1239 case AvailableTSS64: 1240 case BusyTSS64: 1241 replaceBits(target, 23, 0, desc.baseLow); 1242 replaceBits(target, 31, 24, desc.baseHigh); 1243 break; 1244 case CallGate64: 1245 case IntGate64: 1246 case TrapGate64: 1247 replaceBits(target, 15, 0, bits(desc, 15, 0)); 1248 replaceBits(target, 31, 16, bits(desc, 63, 48)); 1249 break; 1250 default: 1251 panic("Wrdh used with wrong descriptor type!\\n"); 1252 } 1253 DestReg = target; 1254 ''' 1255 1256 class Wrtsc(WrRegOp): 1257 code = ''' 1258 TscOp = psrc1; 1259 ''' 1260 1261 class Rdtsc(RdRegOp): 1262 code = ''' 1263 DestReg = TscOp; 1264 ''' 1265 1266 class Rdm5reg(RdRegOp): 1267 code = ''' 1268 DestReg = M5Reg; 1269 ''' 1270 1271 class Wrdl(RegOp): 1272 code = ''' 1273 SegDescriptor desc = SrcReg1; 1274 SegSelector selector = SrcReg2; 1275 if (selector.si || selector.ti) { 1276 if (!desc.p) 1277 panic("Segment not present.\\n"); 1278 SegAttr attr = 0; 1279 attr.dpl = desc.dpl; 1280 attr.unusable = 0; 1281 attr.defaultSize = desc.d; 1282 attr.longMode = desc.l; 1283 attr.avl = desc.avl; 1284 attr.granularity = desc.g; 1285 attr.present = desc.p; 1286 attr.system = desc.s; 1287 attr.type = desc.type; 1288 if (!desc.s) { 1289 // The expand down bit happens to be set for gates. 1290 if (desc.type.e) { 1291 panic("Gate descriptor encountered.\\n"); 1292 } 1293 attr.readable = 1; 1294 attr.writable = 1; 1295 attr.expandDown = 0; 1296 } else { 1297 if (desc.type.codeOrData) { 1298 attr.expandDown = 0; 1299 attr.readable = desc.type.r; 1300 attr.writable = 0; 1301 } else { 1302 attr.expandDown = desc.type.e; 1303 attr.readable = 1; 1304 attr.writable = desc.type.w; 1305 } 1306 } 1307 Addr base = desc.baseLow | (desc.baseHigh << 24); 1308 Addr limit = desc.limitLow | (desc.limitHigh << 16); 1309 if (desc.g) 1310 limit = (limit << 12) | mask(12); 1311 SegBaseDest = base; 1312 SegLimitDest = limit; 1313 SegAttrDest = attr; 1314 } else { 1315 SegBaseDest = SegBaseDest; 1316 SegLimitDest = SegLimitDest; 1317 SegAttrDest = SegAttrDest; 1318 } 1319 ''' 1320}}; 1321