regop.isa revision 6456
12847Sksewell@umich.edu// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 25596Sgblack@eecs.umich.edu// All rights reserved. 32847Sksewell@umich.edu// 42847Sksewell@umich.edu// Redistribution and use of this software in source and binary forms, 52847Sksewell@umich.edu// with or without modification, are permitted provided that the 62847Sksewell@umich.edu// following conditions are met: 72847Sksewell@umich.edu// 82847Sksewell@umich.edu// The software must be used only for Non-Commercial Use which means any 92847Sksewell@umich.edu// use which is NOT directed to receiving any direct monetary 102847Sksewell@umich.edu// compensation for, or commercial advantage from such use. Illustrative 112847Sksewell@umich.edu// examples of non-commercial use are academic research, personal study, 122847Sksewell@umich.edu// teaching, education and corporate research & development. 132847Sksewell@umich.edu// Illustrative examples of commercial use are distributing products for 142847Sksewell@umich.edu// commercial advantage and providing services using the software for 152847Sksewell@umich.edu// commercial advantage. 162847Sksewell@umich.edu// 172847Sksewell@umich.edu// If you wish to use this software or functionality therein that may be 182847Sksewell@umich.edu// covered by patents for commercial use, please contact: 192847Sksewell@umich.edu// Director of Intellectual Property Licensing 202847Sksewell@umich.edu// Office of Strategy and Technology 212847Sksewell@umich.edu// Hewlett-Packard Company 222847Sksewell@umich.edu// 1501 Page Mill Road 232847Sksewell@umich.edu// Palo Alto, California 94304 242847Sksewell@umich.edu// 252847Sksewell@umich.edu// Redistributions of source code must retain the above copyright notice, 262847Sksewell@umich.edu// this list of conditions and the following disclaimer. Redistributions 272847Sksewell@umich.edu// in binary form must reproduce the above copyright notice, this list of 285596Sgblack@eecs.umich.edu// conditions and the following disclaimer in the documentation and/or 292847Sksewell@umich.edu// other materials provided with the distribution. Neither the name of 302847Sksewell@umich.edu// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 312847Sksewell@umich.edu// contributors may be used to endorse or promote products derived from 322847Sksewell@umich.edu// this software without specific prior written permission. No right of 332847Sksewell@umich.edu// sublicense is granted herewith. Derivatives of the software and 345596Sgblack@eecs.umich.edu// output created using the software may be prepared, but only for 356658Snate@binkert.org// Non-Commercial Uses. Derivatives of the software may be shared with 365596Sgblack@eecs.umich.edu// others provided: (i) the others agree to abide by the list of 375596Sgblack@eecs.umich.edu// conditions herein which includes the Non-Commercial Use restrictions; 385596Sgblack@eecs.umich.edu// and (ii) such Derivatives of the software include the above copyright 395596Sgblack@eecs.umich.edu// notice to acknowledge the contribution from this software where 402847Sksewell@umich.edu// applicable, this list of conditions and the disclaimer below. 415596Sgblack@eecs.umich.edu// 425596Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 435596Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 445596Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 455596Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 465596Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 475596Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 485596Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 495596Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 505596Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 515596Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 525596Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 535596Sgblack@eecs.umich.edu// 545596Sgblack@eecs.umich.edu// Authors: Gabe Black 555596Sgblack@eecs.umich.edu 565596Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 575596Sgblack@eecs.umich.edu// 585596Sgblack@eecs.umich.edu// RegOp Microop templates 595596Sgblack@eecs.umich.edu// 605596Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 615596Sgblack@eecs.umich.edu 625596Sgblack@eecs.umich.edudef template MicroRegOpExecute {{ 635596Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 645596Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 655596Sgblack@eecs.umich.edu { 665596Sgblack@eecs.umich.edu Fault fault = NoFault; 675596Sgblack@eecs.umich.edu 685596Sgblack@eecs.umich.edu DPRINTF(X86, "The data size is %d\n", dataSize); 695596Sgblack@eecs.umich.edu %(op_decl)s; 705596Sgblack@eecs.umich.edu %(op_rd)s; 715596Sgblack@eecs.umich.edu 725596Sgblack@eecs.umich.edu if(%(cond_check)s) 735596Sgblack@eecs.umich.edu { 745596Sgblack@eecs.umich.edu %(code)s; 755596Sgblack@eecs.umich.edu %(flag_code)s; 765596Sgblack@eecs.umich.edu } 777720Sgblack@eecs.umich.edu else 787720Sgblack@eecs.umich.edu { 797720Sgblack@eecs.umich.edu %(else_code)s; 805596Sgblack@eecs.umich.edu } 815596Sgblack@eecs.umich.edu 827720Sgblack@eecs.umich.edu //Write the resulting state to the execution context 837720Sgblack@eecs.umich.edu if(fault == NoFault) 847720Sgblack@eecs.umich.edu { 855596Sgblack@eecs.umich.edu %(op_wb)s; 865596Sgblack@eecs.umich.edu } 875596Sgblack@eecs.umich.edu return fault; 885596Sgblack@eecs.umich.edu } 895596Sgblack@eecs.umich.edu}}; 905596Sgblack@eecs.umich.edu 915596Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{ 925596Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 935596Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 945596Sgblack@eecs.umich.edu { 955596Sgblack@eecs.umich.edu Fault fault = NoFault; 965596Sgblack@eecs.umich.edu 975596Sgblack@eecs.umich.edu %(op_decl)s; 985596Sgblack@eecs.umich.edu %(op_rd)s; 995596Sgblack@eecs.umich.edu 1005596Sgblack@eecs.umich.edu if(%(cond_check)s) 1015596Sgblack@eecs.umich.edu { 1025596Sgblack@eecs.umich.edu %(code)s; 1035596Sgblack@eecs.umich.edu %(flag_code)s; 1045596Sgblack@eecs.umich.edu } 1055596Sgblack@eecs.umich.edu else 1065596Sgblack@eecs.umich.edu { 1075596Sgblack@eecs.umich.edu %(else_code)s; 1085596Sgblack@eecs.umich.edu } 1095596Sgblack@eecs.umich.edu 1105596Sgblack@eecs.umich.edu //Write the resulting state to the execution context 1115596Sgblack@eecs.umich.edu if(fault == NoFault) 1125596Sgblack@eecs.umich.edu { 1135596Sgblack@eecs.umich.edu %(op_wb)s; 1145596Sgblack@eecs.umich.edu } 1155596Sgblack@eecs.umich.edu return fault; 1165596Sgblack@eecs.umich.edu } 1175596Sgblack@eecs.umich.edu}}; 1185596Sgblack@eecs.umich.edu 1195596Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{ 1205596Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1215596Sgblack@eecs.umich.edu { 1225596Sgblack@eecs.umich.edu protected: 1235596Sgblack@eecs.umich.edu void buildMe(); 1245596Sgblack@eecs.umich.edu 1255596Sgblack@eecs.umich.edu public: 1265596Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1275596Sgblack@eecs.umich.edu const char * instMnem, 1285596Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1295596Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1305596Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1315596Sgblack@eecs.umich.edu 1325596Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1335596Sgblack@eecs.umich.edu const char * instMnem, 1345596Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1355596Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1365596Sgblack@eecs.umich.edu 1375596Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1385596Sgblack@eecs.umich.edu }; 1395596Sgblack@eecs.umich.edu}}; 1405596Sgblack@eecs.umich.edu 1415596Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{ 1425596Sgblack@eecs.umich.edu 1435596Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1445596Sgblack@eecs.umich.edu { 1455596Sgblack@eecs.umich.edu protected: 1465596Sgblack@eecs.umich.edu void buildMe(); 1475596Sgblack@eecs.umich.edu 1485596Sgblack@eecs.umich.edu public: 1495596Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1505596Sgblack@eecs.umich.edu const char * instMnem, 1515596Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1525596Sgblack@eecs.umich.edu InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 1535596Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1545596Sgblack@eecs.umich.edu 1555596Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1565596Sgblack@eecs.umich.edu const char * instMnem, 1575596Sgblack@eecs.umich.edu InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 1585596Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1595596Sgblack@eecs.umich.edu 1605596Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1615596Sgblack@eecs.umich.edu }; 1625596Sgblack@eecs.umich.edu}}; 1635596Sgblack@eecs.umich.edu 1645596Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{ 1655596Sgblack@eecs.umich.edu 1665596Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 1675596Sgblack@eecs.umich.edu { 1685596Sgblack@eecs.umich.edu %(constructor)s; 1695596Sgblack@eecs.umich.edu } 1705596Sgblack@eecs.umich.edu 1715596Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1725702Ssaidi@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1735702Ssaidi@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1745596Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1755596Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1765702Ssaidi@eecs.umich.edu false, false, false, false, 1772935Sksewell@umich.edu _src1, _src2, _dest, _dataSize, _ext, 1785596Sgblack@eecs.umich.edu %(op_class)s) 1795596Sgblack@eecs.umich.edu { 1802848Sksewell@umich.edu buildMe(); 1812847Sksewell@umich.edu } 1825596Sgblack@eecs.umich.edu 1835596Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1845596Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1855596Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1865596Sgblack@eecs.umich.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1875596Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1885596Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1895596Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 1905596Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1915596Sgblack@eecs.umich.edu %(op_class)s) 1925596Sgblack@eecs.umich.edu { 1935596Sgblack@eecs.umich.edu buildMe(); 1945596Sgblack@eecs.umich.edu } 1955596Sgblack@eecs.umich.edu}}; 1965596Sgblack@eecs.umich.edu 1975596Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{ 1985596Sgblack@eecs.umich.edu 1995596Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 2005596Sgblack@eecs.umich.edu { 2015596Sgblack@eecs.umich.edu %(constructor)s; 2025596Sgblack@eecs.umich.edu } 2035596Sgblack@eecs.umich.edu 2045596Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 2055596Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2065596Sgblack@eecs.umich.edu InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 2075596Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2085596Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2095596Sgblack@eecs.umich.edu false, false, false, false, 2105596Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2115596Sgblack@eecs.umich.edu %(op_class)s) 2125596Sgblack@eecs.umich.edu { 2135596Sgblack@eecs.umich.edu buildMe(); 2145596Sgblack@eecs.umich.edu } 2155596Sgblack@eecs.umich.edu 2165596Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 2175596Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2185596Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 2195596Sgblack@eecs.umich.edu InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 2205596Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2215596Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2225596Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 2235596Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2245596Sgblack@eecs.umich.edu %(op_class)s) 2255596Sgblack@eecs.umich.edu { 2265596Sgblack@eecs.umich.edu buildMe(); 2275596Sgblack@eecs.umich.edu } 2285596Sgblack@eecs.umich.edu}}; 2295596Sgblack@eecs.umich.edu 2305596Sgblack@eecs.umich.eduoutput header {{ 2315596Sgblack@eecs.umich.edu void 2325596Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 2335596Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder); 2345596Sgblack@eecs.umich.edu 2355596Sgblack@eecs.umich.edu enum SegmentSelectorCheck { 2365596Sgblack@eecs.umich.edu SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck, 2375596Sgblack@eecs.umich.edu SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck, 2385596Sgblack@eecs.umich.edu SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck 2395596Sgblack@eecs.umich.edu }; 2405596Sgblack@eecs.umich.edu 2415596Sgblack@eecs.umich.edu enum LongModeDescriptorType { 2425596Sgblack@eecs.umich.edu LDT64 = 2, 2435596Sgblack@eecs.umich.edu AvailableTSS64 = 9, 2445596Sgblack@eecs.umich.edu BusyTSS64 = 0xb, 2455596Sgblack@eecs.umich.edu CallGate64 = 0xc, 2465596Sgblack@eecs.umich.edu IntGate64 = 0xe, 2475596Sgblack@eecs.umich.edu TrapGate64 = 0xf 2485596Sgblack@eecs.umich.edu }; 2495596Sgblack@eecs.umich.edu}}; 2505596Sgblack@eecs.umich.edu 2515596Sgblack@eecs.umich.eduoutput decoder {{ 2525596Sgblack@eecs.umich.edu void 2535596Sgblack@eecs.umich.edu divide(uint64_t dividend, uint64_t divisor, 2545596Sgblack@eecs.umich.edu uint64_t "ient, uint64_t &remainder) 2555596Sgblack@eecs.umich.edu { 2565596Sgblack@eecs.umich.edu //Check for divide by zero. 2575596Sgblack@eecs.umich.edu if (divisor == 0) 2585596Sgblack@eecs.umich.edu panic("Divide by zero!\\n"); 2595596Sgblack@eecs.umich.edu //If the divisor is bigger than the dividend, don't do anything. 2605596Sgblack@eecs.umich.edu if (divisor <= dividend) { 2615596Sgblack@eecs.umich.edu //Shift the divisor so it's msb lines up with the dividend. 2625596Sgblack@eecs.umich.edu int dividendMsb = findMsbSet(dividend); 2635596Sgblack@eecs.umich.edu int divisorMsb = findMsbSet(divisor); 2645596Sgblack@eecs.umich.edu int shift = dividendMsb - divisorMsb; 2655596Sgblack@eecs.umich.edu divisor <<= shift; 2665596Sgblack@eecs.umich.edu //Compute what we'll add to the quotient if the divisor isn't 267 //now larger than the dividend. 268 uint64_t quotientBit = 1; 269 quotientBit <<= shift; 270 //If we need to step back a bit (no pun intended) because the 271 //divisor got too to large, do that here. This is the "or two" 272 //part of one or two bit division. 273 if (divisor > dividend) { 274 quotientBit >>= 1; 275 divisor >>= 1; 276 } 277 //Decrement the remainder and increment the quotient. 278 quotient += quotientBit; 279 remainder -= divisor; 280 } 281 } 282}}; 283 284let {{ 285 # Make these empty strings so that concatenating onto 286 # them will always work. 287 header_output = "" 288 decoder_output = "" 289 exec_output = "" 290 291 immTemplates = ( 292 MicroRegOpImmDeclare, 293 MicroRegOpImmConstructor, 294 MicroRegOpImmExecute) 295 296 regTemplates = ( 297 MicroRegOpDeclare, 298 MicroRegOpConstructor, 299 MicroRegOpExecute) 300 301 class RegOpMeta(type): 302 def buildCppClasses(self, name, Name, suffix, \ 303 code, flag_code, cond_check, else_code): 304 305 # Globals to stick the output in 306 global header_output 307 global decoder_output 308 global exec_output 309 310 # Stick all the code together so it can be searched at once 311 allCode = "|".join((code, flag_code, cond_check, else_code)) 312 313 # If op2 is used anywhere, make register and immediate versions 314 # of this code. 315 matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?") 316 match = matcher.search(allCode) 317 if match: 318 typeQual = "" 319 if match.group("typeQual"): 320 typeQual = match.group("typeQual") 321 src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 322 self.buildCppClasses(name, Name, suffix, 323 matcher.sub(src2_name, code), 324 matcher.sub(src2_name, flag_code), 325 matcher.sub(src2_name, cond_check), 326 matcher.sub(src2_name, else_code)) 327 self.buildCppClasses(name + "i", Name, suffix + "Imm", 328 matcher.sub("imm8", code), 329 matcher.sub("imm8", flag_code), 330 matcher.sub("imm8", cond_check), 331 matcher.sub("imm8", else_code)) 332 return 333 334 # If there's something optional to do with flags, generate 335 # a version without it and fix up this version to use it. 336 if flag_code != "" or cond_check != "true": 337 self.buildCppClasses(name, Name, suffix, 338 code, "", "true", else_code) 339 suffix = "Flags" + suffix 340 341 # If psrc1 or psrc2 is used, we need to actually insert code to 342 # compute it. 343 matcher = re.compile("(?<!\w)psrc1(?!\w)") 344 if matcher.search(allCode): 345 code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code 346 matcher = re.compile("(?<!\w)psrc2(?!\w)") 347 if matcher.search(allCode): 348 code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code 349 # Also make available versions which do sign extension 350 matcher = re.compile("(?<!\w)spsrc1(?!\w)") 351 if matcher.search(allCode): 352 code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code 353 matcher = re.compile("(?<!\w)spsrc2(?!\w)") 354 if matcher.search(allCode): 355 code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code 356 357 base = "X86ISA::RegOp" 358 359 # If imm8 shows up in the code, use the immediate templates, if 360 # not, hopefully the register ones will be correct. 361 templates = regTemplates 362 matcher = re.compile("(?<!\w)imm8(?!\w)") 363 if matcher.search(allCode): 364 base += "Imm" 365 templates = immTemplates 366 367 # Get everything ready for the substitution 368 iop = InstObjParams(name, Name + suffix, base, 369 {"code" : code, 370 "flag_code" : flag_code, 371 "cond_check" : cond_check, 372 "else_code" : else_code}) 373 374 # Generate the actual code (finally!) 375 header_output += templates[0].subst(iop) 376 decoder_output += templates[1].subst(iop) 377 exec_output += templates[2].subst(iop) 378 379 380 def __new__(mcls, Name, bases, dict): 381 abstract = False 382 name = Name.lower() 383 if "abstract" in dict: 384 abstract = dict['abstract'] 385 del dict['abstract'] 386 387 cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 388 if not abstract: 389 cls.className = Name 390 cls.base_mnemonic = name 391 code = cls.code 392 flag_code = cls.flag_code 393 cond_check = cls.cond_check 394 else_code = cls.else_code 395 396 # Set up the C++ classes 397 mcls.buildCppClasses(cls, name, Name, "", 398 code, flag_code, cond_check, else_code) 399 400 # Hook into the microassembler dict 401 global microopClasses 402 microopClasses[name] = cls 403 404 allCode = "|".join((code, flag_code, cond_check, else_code)) 405 406 # If op2 is used anywhere, make register and immediate versions 407 # of this code. 408 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 409 if matcher.search(allCode): 410 microopClasses[name + 'i'] = cls 411 return cls 412 413 414 class RegOp(X86Microop): 415 __metaclass__ = RegOpMeta 416 # This class itself doesn't act as a microop 417 abstract = True 418 419 # Default template parameter values 420 flag_code = "" 421 cond_check = "true" 422 else_code = ";" 423 424 def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 425 self.dest = dest 426 self.src1 = src1 427 self.op2 = op2 428 self.flags = flags 429 self.dataSize = dataSize 430 if flags is None: 431 self.ext = 0 432 else: 433 if not isinstance(flags, (list, tuple)): 434 raise Exception, "flags must be a list or tuple of flags" 435 self.ext = " | ".join(flags) 436 self.className += "Flags" 437 438 def getAllocator(self, *microFlags): 439 className = self.className 440 if self.mnemonic == self.base_mnemonic + 'i': 441 className += "Imm" 442 allocator = '''new %(class_name)s(machInst, macrocodeBlock 443 %(flags)s, %(src1)s, %(op2)s, %(dest)s, 444 %(dataSize)s, %(ext)s)''' % { 445 "class_name" : className, 446 "flags" : self.microFlagsText(microFlags), 447 "src1" : self.src1, "op2" : self.op2, 448 "dest" : self.dest, 449 "dataSize" : self.dataSize, 450 "ext" : self.ext} 451 return allocator 452 453 class LogicRegOp(RegOp): 454 abstract = True 455 flag_code = ''' 456 //Don't have genFlags handle the OF or CF bits 457 uint64_t mask = CFBit | ECFBit | OFBit; 458 ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); 459 //If a logic microop wants to set these, it wants to set them to 0. 460 ccFlagBits &= ~(CFBit & ext); 461 ccFlagBits &= ~(ECFBit & ext); 462 ccFlagBits &= ~(OFBit & ext); 463 ''' 464 465 class FlagRegOp(RegOp): 466 abstract = True 467 flag_code = \ 468 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" 469 470 class SubRegOp(RegOp): 471 abstract = True 472 flag_code = \ 473 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 474 475 class CondRegOp(RegOp): 476 abstract = True 477 cond_check = "checkCondition(ccFlagBits, ext)" 478 479 class RdRegOp(RegOp): 480 abstract = True 481 def __init__(self, dest, src1=None, dataSize="env.dataSize"): 482 if not src1: 483 src1 = dest 484 super(RdRegOp, self).__init__(dest, src1, \ 485 "InstRegIndex(NUM_INTREGS)", None, dataSize) 486 487 class WrRegOp(RegOp): 488 abstract = True 489 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 490 super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ 491 src1, src2, flags, dataSize) 492 493 class Add(FlagRegOp): 494 code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' 495 496 class Or(LogicRegOp): 497 code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' 498 499 class Adc(FlagRegOp): 500 code = ''' 501 CCFlagBits flags = ccFlagBits; 502 DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize); 503 ''' 504 505 class Sbb(SubRegOp): 506 code = ''' 507 CCFlagBits flags = ccFlagBits; 508 DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize); 509 ''' 510 511 class And(LogicRegOp): 512 code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)' 513 514 class Sub(SubRegOp): 515 code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)' 516 517 class Xor(LogicRegOp): 518 code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)' 519 520 class Mul1s(WrRegOp): 521 code = ''' 522 ProdLow = psrc1 * op2; 523 int halfSize = (dataSize * 8) / 2; 524 uint64_t shifter = (1ULL << halfSize); 525 uint64_t hiResult; 526 uint64_t psrc1_h = psrc1 / shifter; 527 uint64_t psrc1_l = psrc1 & mask(halfSize); 528 uint64_t psrc2_h = op2 / shifter; 529 uint64_t psrc2_l = op2 & mask(halfSize); 530 hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 531 ((psrc1_l * psrc2_l) / shifter)) /shifter) + 532 psrc1_h * psrc2_h; 533 if (spsrc1 < 0) 534 hiResult -= op2; 535 int64_t bigSop2 = sop2; 536 if (bigSop2 < 0) 537 hiResult -= psrc1; 538 ProdHi = hiResult; 539 ''' 540 541 class Mul1u(WrRegOp): 542 code = ''' 543 ProdLow = psrc1 * op2; 544 int halfSize = (dataSize * 8) / 2; 545 uint64_t shifter = (1ULL << halfSize); 546 uint64_t psrc1_h = psrc1 / shifter; 547 uint64_t psrc1_l = psrc1 & mask(halfSize); 548 uint64_t psrc2_h = op2 / shifter; 549 uint64_t psrc2_l = op2 & mask(halfSize); 550 ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 551 ((psrc1_l * psrc2_l) / shifter)) / shifter) + 552 psrc1_h * psrc2_h; 553 ''' 554 555 class Mulel(RdRegOp): 556 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 557 558 class Muleh(RdRegOp): 559 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 560 if not src1: 561 src1 = dest 562 super(RdRegOp, self).__init__(dest, src1, \ 563 "InstRegIndex(NUM_INTREGS)", flags, dataSize) 564 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 565 flag_code = ''' 566 if (ProdHi) 567 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 568 else 569 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 570 ''' 571 572 # One or two bit divide 573 class Div1(WrRegOp): 574 code = ''' 575 //These are temporaries so that modifying them later won't make 576 //the ISA parser think they're also sources. 577 uint64_t quotient = 0; 578 uint64_t remainder = psrc1; 579 //Similarly, this is a temporary so changing it doesn't make it 580 //a source. 581 uint64_t divisor = op2; 582 //This is a temporary just for consistency and clarity. 583 uint64_t dividend = remainder; 584 //Do the division. 585 divide(dividend, divisor, quotient, remainder); 586 //Record the final results. 587 Remainder = remainder; 588 Quotient = quotient; 589 Divisor = divisor; 590 ''' 591 592 # Step divide 593 class Div2(RegOp): 594 code = ''' 595 uint64_t dividend = Remainder; 596 uint64_t divisor = Divisor; 597 uint64_t quotient = Quotient; 598 uint64_t remainder = dividend; 599 int remaining = op2; 600 //If we overshot, do nothing. This lets us unrool division loops a 601 //little. 602 if (remaining) { 603 //Shift in bits from the low order portion of the dividend 604 while(dividend < divisor && remaining) { 605 dividend = (dividend << 1) | bits(SrcReg1, remaining - 1); 606 quotient <<= 1; 607 remaining--; 608 } 609 remainder = dividend; 610 //Do the division. 611 divide(dividend, divisor, quotient, remainder); 612 } 613 //Keep track of how many bits there are still to pull in. 614 DestReg = merge(DestReg, remaining, dataSize); 615 //Record the final results 616 Remainder = remainder; 617 Quotient = quotient; 618 ''' 619 flag_code = ''' 620 if (DestReg == 0) 621 ccFlagBits = ccFlagBits | (ext & EZFBit); 622 else 623 ccFlagBits = ccFlagBits & ~(ext & EZFBit); 624 ''' 625 626 class Divq(RdRegOp): 627 code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 628 629 class Divr(RdRegOp): 630 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 631 632 class Mov(CondRegOp): 633 code = 'DestReg = merge(SrcReg1, op2, dataSize)' 634 else_code = 'DestReg=DestReg;' 635 636 # Shift instructions 637 638 class Sll(RegOp): 639 code = ''' 640 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 641 DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 642 ''' 643 flag_code = ''' 644 // If the shift amount is zero, no flags should be modified. 645 if (shiftAmt) { 646 //Zero out any flags we might modify. This way we only have to 647 //worry about setting them. 648 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 649 int CFBits = 0; 650 //Figure out if we -would- set the CF bits if requested. 651 if (shiftAmt <= dataSize * 8 && 652 bits(SrcReg1, dataSize * 8 - shiftAmt)) { 653 CFBits = 1; 654 } 655 //If some combination of the CF bits need to be set, set them. 656 if ((ext & (CFBit | ECFBit)) && CFBits) 657 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 658 //Figure out what the OF bit should be. 659 if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) 660 ccFlagBits = ccFlagBits | OFBit; 661 //Use the regular mechanisms to calculate the other flags. 662 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 663 DestReg, psrc1, op2); 664 } 665 ''' 666 667 class Srl(RegOp): 668 code = ''' 669 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 670 // Because what happens to the bits shift -in- on a right shift 671 // is not defined in the C/C++ standard, we have to mask them out 672 // to be sure they're zero. 673 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 674 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 675 ''' 676 flag_code = ''' 677 // If the shift amount is zero, no flags should be modified. 678 if (shiftAmt) { 679 //Zero out any flags we might modify. This way we only have to 680 //worry about setting them. 681 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 682 //If some combination of the CF bits need to be set, set them. 683 if ((ext & (CFBit | ECFBit)) && 684 shiftAmt <= dataSize * 8 && 685 bits(SrcReg1, shiftAmt - 1)) { 686 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 687 } 688 //Figure out what the OF bit should be. 689 if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) 690 ccFlagBits = ccFlagBits | OFBit; 691 //Use the regular mechanisms to calculate the other flags. 692 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 693 DestReg, psrc1, op2); 694 } 695 ''' 696 697 class Sra(RegOp): 698 code = ''' 699 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 700 // Because what happens to the bits shift -in- on a right shift 701 // is not defined in the C/C++ standard, we have to sign extend 702 // them manually to be sure. 703 uint64_t arithMask = (shiftAmt == 0) ? 0 : 704 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 705 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 706 ''' 707 flag_code = ''' 708 // If the shift amount is zero, no flags should be modified. 709 if (shiftAmt) { 710 //Zero out any flags we might modify. This way we only have to 711 //worry about setting them. 712 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 713 //If some combination of the CF bits need to be set, set them. 714 uint8_t effectiveShift = 715 (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8); 716 if ((ext & (CFBit | ECFBit)) && 717 bits(SrcReg1, effectiveShift - 1)) { 718 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 719 } 720 //Use the regular mechanisms to calculate the other flags. 721 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 722 DestReg, psrc1, op2); 723 } 724 ''' 725 726 class Ror(RegOp): 727 code = ''' 728 uint8_t shiftAmt = 729 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 730 uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 731 if(realShiftAmt) 732 { 733 uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt); 734 uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt); 735 DestReg = merge(DestReg, top | bottom, dataSize); 736 } 737 else 738 DestReg = merge(DestReg, DestReg, dataSize); 739 ''' 740 flag_code = ''' 741 // If the shift amount is zero, no flags should be modified. 742 if (shiftAmt) { 743 //Zero out any flags we might modify. This way we only have to 744 //worry about setting them. 745 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 746 //Find the most and second most significant bits of the result. 747 int msb = bits(DestReg, dataSize * 8 - 1); 748 int smsb = bits(DestReg, dataSize * 8 - 2); 749 //If some combination of the CF bits need to be set, set them. 750 if ((ext & (CFBit | ECFBit)) && msb) 751 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 752 //Figure out what the OF bit should be. 753 if ((ext & OFBit) && (msb ^ smsb)) 754 ccFlagBits = ccFlagBits | OFBit; 755 //Use the regular mechanisms to calculate the other flags. 756 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 757 DestReg, psrc1, op2); 758 } 759 ''' 760 761 class Rcr(RegOp): 762 code = ''' 763 uint8_t shiftAmt = 764 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 765 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 766 if(realShiftAmt) 767 { 768 CCFlagBits flags = ccFlagBits; 769 uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt); 770 if (realShiftAmt > 1) 771 top |= psrc1 << (dataSize * 8 - realShiftAmt + 1); 772 uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt); 773 DestReg = merge(DestReg, top | bottom, dataSize); 774 } 775 else 776 DestReg = merge(DestReg, DestReg, dataSize); 777 ''' 778 flag_code = ''' 779 // If the shift amount is zero, no flags should be modified. 780 if (shiftAmt) { 781 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 782 //Zero out any flags we might modify. This way we only have to 783 //worry about setting them. 784 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 785 //Figure out what the OF bit should be. 786 if ((ext & OFBit) && (origCFBit ^ 787 bits(SrcReg1, dataSize * 8 - 1))) { 788 ccFlagBits = ccFlagBits | OFBit; 789 } 790 //If some combination of the CF bits need to be set, set them. 791 if ((ext & (CFBit | ECFBit)) && 792 (realShiftAmt == 0) ? origCFBit : 793 bits(SrcReg1, realShiftAmt - 1)) { 794 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 795 } 796 //Use the regular mechanisms to calculate the other flags. 797 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 798 DestReg, psrc1, op2); 799 } 800 ''' 801 802 class Rol(RegOp): 803 code = ''' 804 uint8_t shiftAmt = 805 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 806 uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 807 if(realShiftAmt) 808 { 809 uint64_t top = psrc1 << realShiftAmt; 810 uint64_t bottom = 811 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt); 812 DestReg = merge(DestReg, top | bottom, dataSize); 813 } 814 else 815 DestReg = merge(DestReg, DestReg, dataSize); 816 ''' 817 flag_code = ''' 818 // If the shift amount is zero, no flags should be modified. 819 if (shiftAmt) { 820 //Zero out any flags we might modify. This way we only have to 821 //worry about setting them. 822 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 823 //The CF bits, if set, would be set to the lsb of the result. 824 int lsb = DestReg & 0x1; 825 int msb = bits(DestReg, dataSize * 8 - 1); 826 //If some combination of the CF bits need to be set, set them. 827 if ((ext & (CFBit | ECFBit)) && lsb) 828 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 829 //Figure out what the OF bit should be. 830 if ((ext & OFBit) && (msb ^ lsb)) 831 ccFlagBits = ccFlagBits | OFBit; 832 //Use the regular mechanisms to calculate the other flags. 833 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 834 DestReg, psrc1, op2); 835 } 836 ''' 837 838 class Rcl(RegOp): 839 code = ''' 840 uint8_t shiftAmt = 841 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 842 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 843 if(realShiftAmt) 844 { 845 CCFlagBits flags = ccFlagBits; 846 uint64_t top = psrc1 << realShiftAmt; 847 uint64_t bottom = flags.cf << (realShiftAmt - 1); 848 if(shiftAmt > 1) 849 bottom |= 850 bits(psrc1, dataSize * 8 - 1, 851 dataSize * 8 - realShiftAmt + 1); 852 DestReg = merge(DestReg, top | bottom, dataSize); 853 } 854 else 855 DestReg = merge(DestReg, DestReg, dataSize); 856 ''' 857 flag_code = ''' 858 // If the shift amount is zero, no flags should be modified. 859 if (shiftAmt) { 860 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 861 //Zero out any flags we might modify. This way we only have to 862 //worry about setting them. 863 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 864 int msb = bits(DestReg, dataSize * 8 - 1); 865 int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt); 866 //If some combination of the CF bits need to be set, set them. 867 if ((ext & (CFBit | ECFBit)) && 868 (realShiftAmt == 0) ? origCFBit : CFBits) 869 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 870 //Figure out what the OF bit should be. 871 if ((ext & OFBit) && (msb ^ CFBits)) 872 ccFlagBits = ccFlagBits | OFBit; 873 //Use the regular mechanisms to calculate the other flags. 874 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 875 DestReg, psrc1, op2); 876 } 877 ''' 878 879 class Wrip(WrRegOp, CondRegOp): 880 code = 'RIP = psrc1 + sop2 + CSBase' 881 else_code="RIP = RIP;" 882 883 class Wruflags(WrRegOp): 884 code = 'ccFlagBits = psrc1 ^ op2' 885 886 class Wrflags(WrRegOp): 887 code = ''' 888 MiscReg newFlags = psrc1 ^ op2; 889 MiscReg userFlagMask = 0xDD5; 890 // Get only the user flags 891 ccFlagBits = newFlags & userFlagMask; 892 // Get everything else 893 nccFlagBits = newFlags & ~userFlagMask; 894 ''' 895 896 class Rdip(RdRegOp): 897 code = 'DestReg = RIP - CSBase' 898 899 class Ruflags(RdRegOp): 900 code = 'DestReg = ccFlagBits' 901 902 class Rflags(RdRegOp): 903 code = 'DestReg = ccFlagBits | nccFlagBits' 904 905 class Ruflag(RegOp): 906 code = ''' 907 int flag = bits(ccFlagBits, imm8); 908 DestReg = merge(DestReg, flag, dataSize); 909 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 910 (ccFlagBits & ~EZFBit); 911 ''' 912 def __init__(self, dest, imm, flags=None, \ 913 dataSize="env.dataSize"): 914 super(Ruflag, self).__init__(dest, \ 915 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 916 917 class Rflag(RegOp): 918 code = ''' 919 MiscReg flagMask = 0x3F7FDD5; 920 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 921 int flag = bits(flags, imm8); 922 DestReg = merge(DestReg, flag, dataSize); 923 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 924 (ccFlagBits & ~EZFBit); 925 ''' 926 def __init__(self, dest, imm, flags=None, \ 927 dataSize="env.dataSize"): 928 super(Rflag, self).__init__(dest, \ 929 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 930 931 class Sext(RegOp): 932 code = ''' 933 IntReg val = psrc1; 934 // Mask the bit position so that it wraps. 935 int bitPos = op2 & (dataSize * 8 - 1); 936 int sign_bit = bits(val, bitPos, bitPos); 937 uint64_t maskVal = mask(bitPos+1); 938 val = sign_bit ? (val | ~maskVal) : (val & maskVal); 939 DestReg = merge(DestReg, val, dataSize); 940 ''' 941 flag_code = ''' 942 if (!sign_bit) 943 ccFlagBits = ccFlagBits & 944 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit)); 945 else 946 ccFlagBits = ccFlagBits | 947 (ext & (CFBit | ECFBit | ZFBit | EZFBit)); 948 ''' 949 950 class Zext(RegOp): 951 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' 952 953 class Rddr(RegOp): 954 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 955 super(Rddr, self).__init__(dest, \ 956 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 957 code = ''' 958 CR4 cr4 = CR4Op; 959 DR7 dr7 = DR7Op; 960 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 961 fault = new InvalidOpcode(); 962 } else if (dr7.gd) { 963 fault = new DebugException(); 964 } else { 965 DestReg = merge(DestReg, DebugSrc1, dataSize); 966 } 967 ''' 968 969 class Wrdr(RegOp): 970 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 971 super(Wrdr, self).__init__(dest, \ 972 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 973 code = ''' 974 CR4 cr4 = CR4Op; 975 DR7 dr7 = DR7Op; 976 if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { 977 fault = new InvalidOpcode(); 978 } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) && 979 machInst.mode.mode == LongMode) { 980 fault = new GeneralProtection(0); 981 } else if (dr7.gd) { 982 fault = new DebugException(); 983 } else { 984 DebugDest = psrc1; 985 } 986 ''' 987 988 class Rdcr(RegOp): 989 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 990 super(Rdcr, self).__init__(dest, \ 991 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 992 code = ''' 993 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 994 fault = new InvalidOpcode(); 995 } else { 996 DestReg = merge(DestReg, ControlSrc1, dataSize); 997 } 998 ''' 999 1000 class Wrcr(RegOp): 1001 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1002 super(Wrcr, self).__init__(dest, \ 1003 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1004 code = ''' 1005 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 1006 fault = new InvalidOpcode(); 1007 } else { 1008 // There are *s in the line below so it doesn't confuse the 1009 // parser. They may be unnecessary. 1010 //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 1011 MiscReg newVal = psrc1; 1012 1013 // Check for any modifications that would cause a fault. 1014 switch(dest) { 1015 case 0: 1016 { 1017 Efer efer = EferOp; 1018 CR0 cr0 = newVal; 1019 CR4 oldCr4 = CR4Op; 1020 if (bits(newVal, 63, 32) || 1021 (!cr0.pe && cr0.pg) || 1022 (!cr0.cd && cr0.nw) || 1023 (cr0.pg && efer.lme && !oldCr4.pae)) 1024 fault = new GeneralProtection(0); 1025 } 1026 break; 1027 case 2: 1028 break; 1029 case 3: 1030 break; 1031 case 4: 1032 { 1033 CR4 cr4 = newVal; 1034 // PAE can't be disabled in long mode. 1035 if (bits(newVal, 63, 11) || 1036 (machInst.mode.mode == LongMode && !cr4.pae)) 1037 fault = new GeneralProtection(0); 1038 } 1039 break; 1040 case 8: 1041 { 1042 if (bits(newVal, 63, 4)) 1043 fault = new GeneralProtection(0); 1044 } 1045 default: 1046 panic("Unrecognized control register %d.\\n", dest); 1047 } 1048 ControlDest = newVal; 1049 } 1050 ''' 1051 1052 # Microops for manipulating segmentation registers 1053 class SegOp(CondRegOp): 1054 abstract = True 1055 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1056 super(SegOp, self).__init__(dest, \ 1057 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1058 1059 class Wrbase(SegOp): 1060 code = ''' 1061 SegBaseDest = psrc1; 1062 ''' 1063 1064 class Wrlimit(SegOp): 1065 code = ''' 1066 SegLimitDest = psrc1; 1067 ''' 1068 1069 class Wrsel(SegOp): 1070 code = ''' 1071 SegSelDest = psrc1; 1072 ''' 1073 1074 class WrAttr(SegOp): 1075 code = ''' 1076 SegAttrDest = psrc1; 1077 ''' 1078 1079 class Rdbase(SegOp): 1080 code = ''' 1081 DestReg = merge(DestReg, SegBaseSrc1, dataSize); 1082 ''' 1083 1084 class Rdlimit(SegOp): 1085 code = ''' 1086 DestReg = merge(DestReg, SegLimitSrc1, dataSize); 1087 ''' 1088 1089 class RdAttr(SegOp): 1090 code = ''' 1091 DestReg = merge(DestReg, SegAttrSrc1, dataSize); 1092 ''' 1093 1094 class Rdsel(SegOp): 1095 code = ''' 1096 DestReg = merge(DestReg, SegSelSrc1, dataSize); 1097 ''' 1098 1099 class Rdval(RegOp): 1100 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1101 super(Rdval, self).__init__(dest, src1, \ 1102 "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1103 code = ''' 1104 DestReg = MiscRegSrc1; 1105 ''' 1106 1107 class Wrval(RegOp): 1108 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1109 super(Wrval, self).__init__(dest, src1, \ 1110 "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1111 code = ''' 1112 MiscRegDest = SrcReg1; 1113 ''' 1114 1115 class Chks(RegOp): 1116 def __init__(self, dest, src1, src2=0, 1117 flags=None, dataSize="env.dataSize"): 1118 super(Chks, self).__init__(dest, 1119 src1, src2, flags, dataSize) 1120 code = ''' 1121 // The selector is in source 1 and can be at most 16 bits. 1122 SegSelector selector = DestReg; 1123 SegDescriptor desc = SrcReg1; 1124 HandyM5Reg m5reg = M5Reg; 1125 1126 switch (imm8) 1127 { 1128 case SegNoCheck: 1129 break; 1130 case SegCSCheck: 1131 // Make sure it's the right type 1132 if (desc.s == 0 || desc.type.codeOrData != 1) { 1133 fault = new GeneralProtection(0); 1134 } else if (m5reg.cpl != desc.dpl) { 1135 fault = new GeneralProtection(0); 1136 } 1137 break; 1138 case SegCallGateCheck: 1139 panic("CS checks for far calls/jumps through call gates" 1140 "not implemented.\\n"); 1141 break; 1142 case SegSoftIntGateCheck: 1143 // Check permissions. 1144 if (desc.dpl < m5reg.cpl) { 1145 fault = new GeneralProtection(selector); 1146 break; 1147 } 1148 // Fall through on purpose 1149 case SegIntGateCheck: 1150 // Make sure the gate's the right type. 1151 if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) || 1152 ((desc.type & 0x6) != 0x6)) { 1153 fault = new GeneralProtection(0); 1154 } 1155 break; 1156 case SegSSCheck: 1157 if (selector.si || selector.ti) { 1158 if (!desc.p) { 1159 fault = new StackFault(selector); 1160 } 1161 } else { 1162 if ((m5reg.submode != SixtyFourBitMode || 1163 m5reg.cpl == 3) || 1164 !(desc.s == 1 && 1165 desc.type.codeOrData == 0 && desc.type.w) || 1166 (desc.dpl != m5reg.cpl) || 1167 (selector.rpl != m5reg.cpl)) { 1168 fault = new GeneralProtection(selector); 1169 } 1170 } 1171 break; 1172 case SegIretCheck: 1173 { 1174 if ((!selector.si && !selector.ti) || 1175 (selector.rpl < m5reg.cpl) || 1176 !(desc.s == 1 && desc.type.codeOrData == 1) || 1177 (!desc.type.c && desc.dpl != selector.rpl) || 1178 (desc.type.c && desc.dpl > selector.rpl)) { 1179 fault = new GeneralProtection(selector); 1180 } else if (!desc.p) { 1181 fault = new SegmentNotPresent(selector); 1182 } 1183 break; 1184 } 1185 case SegIntCSCheck: 1186 if (m5reg.mode == LongMode) { 1187 if (desc.l != 1 || desc.d != 0) { 1188 fault = new GeneralProtection(selector); 1189 } 1190 } else { 1191 panic("Interrupt CS checks not implemented " 1192 "in legacy mode.\\n"); 1193 } 1194 break; 1195 case SegTRCheck: 1196 if (!selector.si || selector.ti) { 1197 fault = new GeneralProtection(selector); 1198 } 1199 break; 1200 case SegTSSCheck: 1201 if (!desc.p) { 1202 fault = new SegmentNotPresent(selector); 1203 } else if (!(desc.type == 0x9 || 1204 (desc.type == 1 && 1205 m5reg.mode != LongMode))) { 1206 fault = new GeneralProtection(selector); 1207 } 1208 break; 1209 case SegInGDTCheck: 1210 if (selector.ti) { 1211 fault = new GeneralProtection(selector); 1212 } 1213 break; 1214 case SegLDTCheck: 1215 if (!desc.p) { 1216 fault = new SegmentNotPresent(selector); 1217 } else if (desc.type != 0x2) { 1218 fault = new GeneralProtection(selector); 1219 } 1220 break; 1221 default: 1222 panic("Undefined segment check type.\\n"); 1223 } 1224 ''' 1225 flag_code = ''' 1226 // Check for a NULL selector and set ZF,EZF appropriately. 1227 ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit)); 1228 if (!selector.si && !selector.ti) 1229 ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit)); 1230 ''' 1231 1232 class Wrdh(RegOp): 1233 code = ''' 1234 SegDescriptor desc = SrcReg1; 1235 1236 uint64_t target = bits(SrcReg2, 31, 0) << 32; 1237 switch(desc.type) { 1238 case LDT64: 1239 case AvailableTSS64: 1240 case BusyTSS64: 1241 replaceBits(target, 23, 0, desc.baseLow); 1242 replaceBits(target, 31, 24, desc.baseHigh); 1243 break; 1244 case CallGate64: 1245 case IntGate64: 1246 case TrapGate64: 1247 replaceBits(target, 15, 0, bits(desc, 15, 0)); 1248 replaceBits(target, 31, 16, bits(desc, 63, 48)); 1249 break; 1250 default: 1251 panic("Wrdh used with wrong descriptor type!\\n"); 1252 } 1253 DestReg = target; 1254 ''' 1255 1256 class Wrtsc(WrRegOp): 1257 code = ''' 1258 TscOp = psrc1; 1259 ''' 1260 1261 class Rdtsc(RdRegOp): 1262 code = ''' 1263 DestReg = TscOp; 1264 ''' 1265 1266 class Rdm5reg(RdRegOp): 1267 code = ''' 1268 DestReg = M5Reg; 1269 ''' 1270 1271 class Wrdl(RegOp): 1272 code = ''' 1273 SegDescriptor desc = SrcReg1; 1274 SegSelector selector = SrcReg2; 1275 if (selector.si || selector.ti) { 1276 if (!desc.p) 1277 panic("Segment not present.\\n"); 1278 SegAttr attr = 0; 1279 attr.dpl = desc.dpl; 1280 attr.unusable = 0; 1281 attr.defaultSize = desc.d; 1282 attr.longMode = desc.l; 1283 attr.avl = desc.avl; 1284 attr.granularity = desc.g; 1285 attr.present = desc.p; 1286 attr.system = desc.s; 1287 attr.type = desc.type; 1288 if (!desc.s) { 1289 // The expand down bit happens to be set for gates. 1290 if (desc.type.e) { 1291 panic("Gate descriptor encountered.\\n"); 1292 } 1293 attr.readable = 1; 1294 attr.writable = 1; 1295 attr.expandDown = 0; 1296 } else { 1297 if (desc.type.codeOrData) { 1298 attr.expandDown = 0; 1299 attr.readable = desc.type.r; 1300 attr.writable = 0; 1301 } else { 1302 attr.expandDown = desc.type.e; 1303 attr.readable = 1; 1304 attr.writable = desc.type.w; 1305 } 1306 } 1307 Addr base = desc.baseLow | (desc.baseHigh << 24); 1308 Addr limit = desc.limitLow | (desc.limitHigh << 16); 1309 if (desc.g) 1310 limit = (limit << 12) | mask(12); 1311 SegBaseDest = base; 1312 SegLimitDest = limit; 1313 SegAttrDest = attr; 1314 } else { 1315 SegBaseDest = SegBaseDest; 1316 SegLimitDest = SegLimitDest; 1317 SegAttrDest = SegAttrDest; 1318 } 1319 ''' 1320}}; 1321