regop.isa revision 6430
15409Sgblack@eecs.umich.edu// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
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64519Sgblack@eecs.umich.edu// following conditions are met:
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534519Sgblack@eecs.umich.edu//
544519Sgblack@eecs.umich.edu// Authors: Gabe Black
554519Sgblack@eecs.umich.edu
564519Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////////////
574519Sgblack@eecs.umich.edu//
584519Sgblack@eecs.umich.edu// RegOp Microop templates
594519Sgblack@eecs.umich.edu//
604519Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////////////
614519Sgblack@eecs.umich.edu
624519Sgblack@eecs.umich.edudef template MicroRegOpExecute {{
634519Sgblack@eecs.umich.edu        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
644519Sgblack@eecs.umich.edu                Trace::InstRecord *traceData) const
654519Sgblack@eecs.umich.edu        {
664519Sgblack@eecs.umich.edu            Fault fault = NoFault;
674519Sgblack@eecs.umich.edu
684809Sgblack@eecs.umich.edu            DPRINTF(X86, "The data size is %d\n", dataSize);
694519Sgblack@eecs.umich.edu            %(op_decl)s;
704519Sgblack@eecs.umich.edu            %(op_rd)s;
714688Sgblack@eecs.umich.edu
724688Sgblack@eecs.umich.edu            if(%(cond_check)s)
734688Sgblack@eecs.umich.edu            {
744688Sgblack@eecs.umich.edu                %(code)s;
754688Sgblack@eecs.umich.edu                %(flag_code)s;
764688Sgblack@eecs.umich.edu            }
774708Sgblack@eecs.umich.edu            else
784708Sgblack@eecs.umich.edu            {
794708Sgblack@eecs.umich.edu                %(else_code)s;
804708Sgblack@eecs.umich.edu            }
814519Sgblack@eecs.umich.edu
824519Sgblack@eecs.umich.edu            //Write the resulting state to the execution context
834519Sgblack@eecs.umich.edu            if(fault == NoFault)
844519Sgblack@eecs.umich.edu            {
854519Sgblack@eecs.umich.edu                %(op_wb)s;
864519Sgblack@eecs.umich.edu            }
874519Sgblack@eecs.umich.edu            return fault;
884519Sgblack@eecs.umich.edu        }
894519Sgblack@eecs.umich.edu}};
904519Sgblack@eecs.umich.edu
914519Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{
924951Sgblack@eecs.umich.edu        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
934519Sgblack@eecs.umich.edu                Trace::InstRecord *traceData) const
944519Sgblack@eecs.umich.edu        {
954519Sgblack@eecs.umich.edu            Fault fault = NoFault;
964519Sgblack@eecs.umich.edu
974519Sgblack@eecs.umich.edu            %(op_decl)s;
984519Sgblack@eecs.umich.edu            %(op_rd)s;
994688Sgblack@eecs.umich.edu
1004688Sgblack@eecs.umich.edu            if(%(cond_check)s)
1014688Sgblack@eecs.umich.edu            {
1024688Sgblack@eecs.umich.edu                %(code)s;
1034688Sgblack@eecs.umich.edu                %(flag_code)s;
1044688Sgblack@eecs.umich.edu            }
1054708Sgblack@eecs.umich.edu            else
1064708Sgblack@eecs.umich.edu            {
1074708Sgblack@eecs.umich.edu                %(else_code)s;
1084708Sgblack@eecs.umich.edu            }
1094519Sgblack@eecs.umich.edu
1104519Sgblack@eecs.umich.edu            //Write the resulting state to the execution context
1114519Sgblack@eecs.umich.edu            if(fault == NoFault)
1124519Sgblack@eecs.umich.edu            {
1134519Sgblack@eecs.umich.edu                %(op_wb)s;
1144519Sgblack@eecs.umich.edu            }
1154519Sgblack@eecs.umich.edu            return fault;
1164519Sgblack@eecs.umich.edu        }
1174519Sgblack@eecs.umich.edu}};
1184519Sgblack@eecs.umich.edu
1194519Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{
1204519Sgblack@eecs.umich.edu    class %(class_name)s : public %(base_class)s
1214519Sgblack@eecs.umich.edu    {
1224519Sgblack@eecs.umich.edu      protected:
1234519Sgblack@eecs.umich.edu        void buildMe();
1244519Sgblack@eecs.umich.edu
1254519Sgblack@eecs.umich.edu      public:
1264519Sgblack@eecs.umich.edu        %(class_name)s(ExtMachInst _machInst,
1274519Sgblack@eecs.umich.edu                const char * instMnem,
1284519Sgblack@eecs.umich.edu                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
1296345Sgblack@eecs.umich.edu                InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
1304712Sgblack@eecs.umich.edu                uint8_t _dataSize, uint16_t _ext);
1314519Sgblack@eecs.umich.edu
1324519Sgblack@eecs.umich.edu        %(class_name)s(ExtMachInst _machInst,
1334519Sgblack@eecs.umich.edu                const char * instMnem,
1346345Sgblack@eecs.umich.edu                InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
1354712Sgblack@eecs.umich.edu                uint8_t _dataSize, uint16_t _ext);
1364519Sgblack@eecs.umich.edu
1374519Sgblack@eecs.umich.edu        %(BasicExecDeclare)s
1384519Sgblack@eecs.umich.edu    };
1394519Sgblack@eecs.umich.edu}};
1404519Sgblack@eecs.umich.edu
1414519Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{
1424519Sgblack@eecs.umich.edu
1434951Sgblack@eecs.umich.edu    class %(class_name)s : public %(base_class)s
1444519Sgblack@eecs.umich.edu    {
1454519Sgblack@eecs.umich.edu      protected:
1464519Sgblack@eecs.umich.edu        void buildMe();
1474519Sgblack@eecs.umich.edu
1484519Sgblack@eecs.umich.edu      public:
1494951Sgblack@eecs.umich.edu        %(class_name)s(ExtMachInst _machInst,
1504519Sgblack@eecs.umich.edu                const char * instMnem,
1514519Sgblack@eecs.umich.edu                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
1526345Sgblack@eecs.umich.edu                InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
1534712Sgblack@eecs.umich.edu                uint8_t _dataSize, uint16_t _ext);
1544519Sgblack@eecs.umich.edu
1554951Sgblack@eecs.umich.edu        %(class_name)s(ExtMachInst _machInst,
1564519Sgblack@eecs.umich.edu                const char * instMnem,
1576345Sgblack@eecs.umich.edu                InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
1584712Sgblack@eecs.umich.edu                uint8_t _dataSize, uint16_t _ext);
1594519Sgblack@eecs.umich.edu
1604519Sgblack@eecs.umich.edu        %(BasicExecDeclare)s
1614519Sgblack@eecs.umich.edu    };
1624519Sgblack@eecs.umich.edu}};
1634519Sgblack@eecs.umich.edu
1644519Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{
1654519Sgblack@eecs.umich.edu
1664519Sgblack@eecs.umich.edu    inline void %(class_name)s::buildMe()
1674519Sgblack@eecs.umich.edu    {
1684519Sgblack@eecs.umich.edu        %(constructor)s;
1694519Sgblack@eecs.umich.edu    }
1704519Sgblack@eecs.umich.edu
1714519Sgblack@eecs.umich.edu    inline %(class_name)s::%(class_name)s(
1724519Sgblack@eecs.umich.edu            ExtMachInst machInst, const char * instMnem,
1736345Sgblack@eecs.umich.edu            InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
1744712Sgblack@eecs.umich.edu            uint8_t _dataSize, uint16_t _ext) :
1754519Sgblack@eecs.umich.edu        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
1764581Sgblack@eecs.umich.edu                false, false, false, false,
1774688Sgblack@eecs.umich.edu                _src1, _src2, _dest, _dataSize, _ext,
1784581Sgblack@eecs.umich.edu                %(op_class)s)
1794519Sgblack@eecs.umich.edu    {
1804519Sgblack@eecs.umich.edu        buildMe();
1814519Sgblack@eecs.umich.edu    }
1824519Sgblack@eecs.umich.edu
1834519Sgblack@eecs.umich.edu    inline %(class_name)s::%(class_name)s(
1844519Sgblack@eecs.umich.edu            ExtMachInst machInst, const char * instMnem,
1854519Sgblack@eecs.umich.edu            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
1866345Sgblack@eecs.umich.edu            InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest,
1874712Sgblack@eecs.umich.edu            uint8_t _dataSize, uint16_t _ext) :
1884519Sgblack@eecs.umich.edu        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
1894581Sgblack@eecs.umich.edu                isMicro, isDelayed, isFirst, isLast,
1904688Sgblack@eecs.umich.edu                _src1, _src2, _dest, _dataSize, _ext,
1914581Sgblack@eecs.umich.edu                %(op_class)s)
1924519Sgblack@eecs.umich.edu    {
1934519Sgblack@eecs.umich.edu        buildMe();
1944519Sgblack@eecs.umich.edu    }
1954519Sgblack@eecs.umich.edu}};
1964519Sgblack@eecs.umich.edu
1974519Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{
1984519Sgblack@eecs.umich.edu
1994951Sgblack@eecs.umich.edu    inline void %(class_name)s::buildMe()
2004519Sgblack@eecs.umich.edu    {
2014519Sgblack@eecs.umich.edu        %(constructor)s;
2024519Sgblack@eecs.umich.edu    }
2034519Sgblack@eecs.umich.edu
2044951Sgblack@eecs.umich.edu    inline %(class_name)s::%(class_name)s(
2054519Sgblack@eecs.umich.edu            ExtMachInst machInst, const char * instMnem,
2066345Sgblack@eecs.umich.edu            InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
2074712Sgblack@eecs.umich.edu            uint8_t _dataSize, uint16_t _ext) :
2084519Sgblack@eecs.umich.edu        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
2094581Sgblack@eecs.umich.edu                false, false, false, false,
2104688Sgblack@eecs.umich.edu                _src1, _imm8, _dest, _dataSize, _ext,
2114581Sgblack@eecs.umich.edu                %(op_class)s)
2124519Sgblack@eecs.umich.edu    {
2134519Sgblack@eecs.umich.edu        buildMe();
2144519Sgblack@eecs.umich.edu    }
2154519Sgblack@eecs.umich.edu
2164951Sgblack@eecs.umich.edu    inline %(class_name)s::%(class_name)s(
2174519Sgblack@eecs.umich.edu            ExtMachInst machInst, const char * instMnem,
2184519Sgblack@eecs.umich.edu            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
2196345Sgblack@eecs.umich.edu            InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest,
2204712Sgblack@eecs.umich.edu            uint8_t _dataSize, uint16_t _ext) :
2214519Sgblack@eecs.umich.edu        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
2224581Sgblack@eecs.umich.edu                isMicro, isDelayed, isFirst, isLast,
2234688Sgblack@eecs.umich.edu                _src1, _imm8, _dest, _dataSize, _ext,
2244581Sgblack@eecs.umich.edu                %(op_class)s)
2254519Sgblack@eecs.umich.edu    {
2264519Sgblack@eecs.umich.edu        buildMe();
2274519Sgblack@eecs.umich.edu    }
2284519Sgblack@eecs.umich.edu}};
2294519Sgblack@eecs.umich.edu
2305075Sgblack@eecs.umich.eduoutput header {{
2315075Sgblack@eecs.umich.edu    void
2325075Sgblack@eecs.umich.edu    divide(uint64_t dividend, uint64_t divisor,
2335075Sgblack@eecs.umich.edu            uint64_t &quotient, uint64_t &remainder);
2345428Sgblack@eecs.umich.edu
2355428Sgblack@eecs.umich.edu    enum SegmentSelectorCheck {
2365674Sgblack@eecs.umich.edu      SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck,
2375899Sgblack@eecs.umich.edu      SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck,
2385936Sgblack@eecs.umich.edu      SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck
2395428Sgblack@eecs.umich.edu    };
2405678Sgblack@eecs.umich.edu
2415678Sgblack@eecs.umich.edu    enum LongModeDescriptorType {
2425678Sgblack@eecs.umich.edu        LDT64 = 2,
2435678Sgblack@eecs.umich.edu        AvailableTSS64 = 9,
2445678Sgblack@eecs.umich.edu        BusyTSS64 = 0xb,
2455678Sgblack@eecs.umich.edu        CallGate64 = 0xc,
2465678Sgblack@eecs.umich.edu        IntGate64 = 0xe,
2475678Sgblack@eecs.umich.edu        TrapGate64 = 0xf
2485678Sgblack@eecs.umich.edu    };
2495075Sgblack@eecs.umich.edu}};
2505075Sgblack@eecs.umich.edu
2515075Sgblack@eecs.umich.eduoutput decoder {{
2525075Sgblack@eecs.umich.edu    void
2535075Sgblack@eecs.umich.edu    divide(uint64_t dividend, uint64_t divisor,
2545075Sgblack@eecs.umich.edu            uint64_t &quotient, uint64_t &remainder)
2555075Sgblack@eecs.umich.edu    {
2565075Sgblack@eecs.umich.edu        //Check for divide by zero.
2575075Sgblack@eecs.umich.edu        if (divisor == 0)
2585075Sgblack@eecs.umich.edu            panic("Divide by zero!\\n");
2595075Sgblack@eecs.umich.edu        //If the divisor is bigger than the dividend, don't do anything.
2605075Sgblack@eecs.umich.edu        if (divisor <= dividend) {
2615075Sgblack@eecs.umich.edu            //Shift the divisor so it's msb lines up with the dividend.
2625075Sgblack@eecs.umich.edu            int dividendMsb = findMsbSet(dividend);
2635075Sgblack@eecs.umich.edu            int divisorMsb = findMsbSet(divisor);
2645075Sgblack@eecs.umich.edu            int shift = dividendMsb - divisorMsb;
2655075Sgblack@eecs.umich.edu            divisor <<= shift;
2665075Sgblack@eecs.umich.edu            //Compute what we'll add to the quotient if the divisor isn't
2675075Sgblack@eecs.umich.edu            //now larger than the dividend.
2685075Sgblack@eecs.umich.edu            uint64_t quotientBit = 1;
2695075Sgblack@eecs.umich.edu            quotientBit <<= shift;
2705075Sgblack@eecs.umich.edu            //If we need to step back a bit (no pun intended) because the
2715075Sgblack@eecs.umich.edu            //divisor got too to large, do that here. This is the "or two"
2725075Sgblack@eecs.umich.edu            //part of one or two bit division.
2735075Sgblack@eecs.umich.edu            if (divisor > dividend) {
2745075Sgblack@eecs.umich.edu                quotientBit >>= 1;
2755075Sgblack@eecs.umich.edu                divisor >>= 1;
2765075Sgblack@eecs.umich.edu            }
2775075Sgblack@eecs.umich.edu            //Decrement the remainder and increment the quotient.
2785075Sgblack@eecs.umich.edu            quotient += quotientBit;
2795075Sgblack@eecs.umich.edu            remainder -= divisor;
2805075Sgblack@eecs.umich.edu        }
2815075Sgblack@eecs.umich.edu    }
2825075Sgblack@eecs.umich.edu}};
2835075Sgblack@eecs.umich.edu
2844519Sgblack@eecs.umich.edulet {{
2855040Sgblack@eecs.umich.edu    # Make these empty strings so that concatenating onto
2865040Sgblack@eecs.umich.edu    # them will always work.
2875040Sgblack@eecs.umich.edu    header_output = ""
2885040Sgblack@eecs.umich.edu    decoder_output = ""
2895040Sgblack@eecs.umich.edu    exec_output = ""
2905040Sgblack@eecs.umich.edu
2915040Sgblack@eecs.umich.edu    immTemplates = (
2925040Sgblack@eecs.umich.edu            MicroRegOpImmDeclare,
2935040Sgblack@eecs.umich.edu            MicroRegOpImmConstructor,
2945040Sgblack@eecs.umich.edu            MicroRegOpImmExecute)
2955040Sgblack@eecs.umich.edu
2965040Sgblack@eecs.umich.edu    regTemplates = (
2975040Sgblack@eecs.umich.edu            MicroRegOpDeclare,
2985040Sgblack@eecs.umich.edu            MicroRegOpConstructor,
2995040Sgblack@eecs.umich.edu            MicroRegOpExecute)
3005040Sgblack@eecs.umich.edu
3015040Sgblack@eecs.umich.edu    class RegOpMeta(type):
3025040Sgblack@eecs.umich.edu        def buildCppClasses(self, name, Name, suffix, \
3035040Sgblack@eecs.umich.edu                code, flag_code, cond_check, else_code):
3045040Sgblack@eecs.umich.edu
3055040Sgblack@eecs.umich.edu            # Globals to stick the output in
3065040Sgblack@eecs.umich.edu            global header_output
3075040Sgblack@eecs.umich.edu            global decoder_output
3085040Sgblack@eecs.umich.edu            global exec_output
3095040Sgblack@eecs.umich.edu
3105040Sgblack@eecs.umich.edu            # Stick all the code together so it can be searched at once
3115040Sgblack@eecs.umich.edu            allCode = "|".join((code, flag_code, cond_check, else_code))
3125040Sgblack@eecs.umich.edu
3135040Sgblack@eecs.umich.edu            # If op2 is used anywhere, make register and immediate versions
3145040Sgblack@eecs.umich.edu            # of this code.
3155062Sgblack@eecs.umich.edu            matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?")
3165062Sgblack@eecs.umich.edu            match = matcher.search(allCode)
3175062Sgblack@eecs.umich.edu            if match:
3185062Sgblack@eecs.umich.edu                typeQual = ""
3195062Sgblack@eecs.umich.edu                if match.group("typeQual"):
3205062Sgblack@eecs.umich.edu                    typeQual = match.group("typeQual")
3215062Sgblack@eecs.umich.edu                src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual)
3225040Sgblack@eecs.umich.edu                self.buildCppClasses(name, Name, suffix,
3235062Sgblack@eecs.umich.edu                        matcher.sub(src2_name, code),
3245062Sgblack@eecs.umich.edu                        matcher.sub(src2_name, flag_code),
3255062Sgblack@eecs.umich.edu                        matcher.sub(src2_name, cond_check),
3265062Sgblack@eecs.umich.edu                        matcher.sub(src2_name, else_code))
3275040Sgblack@eecs.umich.edu                self.buildCppClasses(name + "i", Name, suffix + "Imm",
3285040Sgblack@eecs.umich.edu                        matcher.sub("imm8", code),
3295040Sgblack@eecs.umich.edu                        matcher.sub("imm8", flag_code),
3305040Sgblack@eecs.umich.edu                        matcher.sub("imm8", cond_check),
3315040Sgblack@eecs.umich.edu                        matcher.sub("imm8", else_code))
3325040Sgblack@eecs.umich.edu                return
3335040Sgblack@eecs.umich.edu
3345040Sgblack@eecs.umich.edu            # If there's something optional to do with flags, generate
3355040Sgblack@eecs.umich.edu            # a version without it and fix up this version to use it.
3365239Sgblack@eecs.umich.edu            if flag_code != "" or cond_check != "true":
3375040Sgblack@eecs.umich.edu                self.buildCppClasses(name, Name, suffix,
3385040Sgblack@eecs.umich.edu                        code, "", "true", else_code)
3395040Sgblack@eecs.umich.edu                suffix = "Flags" + suffix
3405040Sgblack@eecs.umich.edu
3415040Sgblack@eecs.umich.edu            # If psrc1 or psrc2 is used, we need to actually insert code to
3425040Sgblack@eecs.umich.edu            # compute it.
3435040Sgblack@eecs.umich.edu            matcher = re.compile("(?<!\w)psrc1(?!\w)")
3445040Sgblack@eecs.umich.edu            if matcher.search(allCode):
3455061Sgblack@eecs.umich.edu                code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code
3465040Sgblack@eecs.umich.edu            matcher = re.compile("(?<!\w)psrc2(?!\w)")
3475040Sgblack@eecs.umich.edu            if matcher.search(allCode):
3485061Sgblack@eecs.umich.edu                code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code
3495061Sgblack@eecs.umich.edu            # Also make available versions which do sign extension
3505061Sgblack@eecs.umich.edu            matcher = re.compile("(?<!\w)spsrc1(?!\w)")
3515061Sgblack@eecs.umich.edu            if matcher.search(allCode):
3525061Sgblack@eecs.umich.edu                code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code
3535061Sgblack@eecs.umich.edu            matcher = re.compile("(?<!\w)spsrc2(?!\w)")
3545061Sgblack@eecs.umich.edu            if matcher.search(allCode):
3555061Sgblack@eecs.umich.edu                code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code
3565040Sgblack@eecs.umich.edu
3575040Sgblack@eecs.umich.edu            base = "X86ISA::RegOp"
3585040Sgblack@eecs.umich.edu
3595040Sgblack@eecs.umich.edu            # If imm8 shows up in the code, use the immediate templates, if
3605040Sgblack@eecs.umich.edu            # not, hopefully the register ones will be correct.
3615040Sgblack@eecs.umich.edu            templates = regTemplates
3625040Sgblack@eecs.umich.edu            matcher = re.compile("(?<!\w)imm8(?!\w)")
3635040Sgblack@eecs.umich.edu            if matcher.search(allCode):
3645040Sgblack@eecs.umich.edu                base += "Imm"
3655040Sgblack@eecs.umich.edu                templates = immTemplates
3665040Sgblack@eecs.umich.edu
3675040Sgblack@eecs.umich.edu            # Get everything ready for the substitution
3685040Sgblack@eecs.umich.edu            iop = InstObjParams(name, Name + suffix, base,
3695040Sgblack@eecs.umich.edu                    {"code" : code,
3705040Sgblack@eecs.umich.edu                     "flag_code" : flag_code,
3715040Sgblack@eecs.umich.edu                     "cond_check" : cond_check,
3725040Sgblack@eecs.umich.edu                     "else_code" : else_code})
3735040Sgblack@eecs.umich.edu
3745040Sgblack@eecs.umich.edu            # Generate the actual code (finally!)
3755040Sgblack@eecs.umich.edu            header_output += templates[0].subst(iop)
3765040Sgblack@eecs.umich.edu            decoder_output += templates[1].subst(iop)
3775040Sgblack@eecs.umich.edu            exec_output += templates[2].subst(iop)
3785040Sgblack@eecs.umich.edu
3795040Sgblack@eecs.umich.edu
3805040Sgblack@eecs.umich.edu        def __new__(mcls, Name, bases, dict):
3814688Sgblack@eecs.umich.edu            abstract = False
3825040Sgblack@eecs.umich.edu            name = Name.lower()
3834688Sgblack@eecs.umich.edu            if "abstract" in dict:
3844688Sgblack@eecs.umich.edu                abstract = dict['abstract']
3854688Sgblack@eecs.umich.edu                del dict['abstract']
3864688Sgblack@eecs.umich.edu
3875040Sgblack@eecs.umich.edu            cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict)
3884688Sgblack@eecs.umich.edu            if not abstract:
3895040Sgblack@eecs.umich.edu                cls.className = Name
3905040Sgblack@eecs.umich.edu                cls.base_mnemonic = name
3915040Sgblack@eecs.umich.edu                code = cls.code
3925040Sgblack@eecs.umich.edu                flag_code = cls.flag_code
3935040Sgblack@eecs.umich.edu                cond_check = cls.cond_check
3945040Sgblack@eecs.umich.edu                else_code = cls.else_code
3955040Sgblack@eecs.umich.edu
3965040Sgblack@eecs.umich.edu                # Set up the C++ classes
3975040Sgblack@eecs.umich.edu                mcls.buildCppClasses(cls, name, Name, "",
3985040Sgblack@eecs.umich.edu                        code, flag_code, cond_check, else_code)
3995040Sgblack@eecs.umich.edu
4005040Sgblack@eecs.umich.edu                # Hook into the microassembler dict
4015040Sgblack@eecs.umich.edu                global microopClasses
4025040Sgblack@eecs.umich.edu                microopClasses[name] = cls
4035040Sgblack@eecs.umich.edu
4045040Sgblack@eecs.umich.edu                allCode = "|".join((code, flag_code, cond_check, else_code))
4055040Sgblack@eecs.umich.edu
4065040Sgblack@eecs.umich.edu                # If op2 is used anywhere, make register and immediate versions
4075040Sgblack@eecs.umich.edu                # of this code.
4085040Sgblack@eecs.umich.edu                matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
4095040Sgblack@eecs.umich.edu                if matcher.search(allCode):
4105040Sgblack@eecs.umich.edu                    microopClasses[name + 'i'] = cls
4114688Sgblack@eecs.umich.edu            return cls
4124688Sgblack@eecs.umich.edu
4135040Sgblack@eecs.umich.edu
4145040Sgblack@eecs.umich.edu    class RegOp(X86Microop):
4155040Sgblack@eecs.umich.edu        __metaclass__ = RegOpMeta
4165040Sgblack@eecs.umich.edu        # This class itself doesn't act as a microop
4174688Sgblack@eecs.umich.edu        abstract = True
4184688Sgblack@eecs.umich.edu
4195040Sgblack@eecs.umich.edu        # Default template parameter values
4205040Sgblack@eecs.umich.edu        flag_code = ""
4215040Sgblack@eecs.umich.edu        cond_check = "true"
4225040Sgblack@eecs.umich.edu        else_code = ";"
4235040Sgblack@eecs.umich.edu
4245040Sgblack@eecs.umich.edu        def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"):
4254519Sgblack@eecs.umich.edu            self.dest = dest
4264519Sgblack@eecs.umich.edu            self.src1 = src1
4275040Sgblack@eecs.umich.edu            self.op2 = op2
4284688Sgblack@eecs.umich.edu            self.flags = flags
4294701Sgblack@eecs.umich.edu            self.dataSize = dataSize
4304688Sgblack@eecs.umich.edu            if flags is None:
4314688Sgblack@eecs.umich.edu                self.ext = 0
4324688Sgblack@eecs.umich.edu            else:
4334688Sgblack@eecs.umich.edu                if not isinstance(flags, (list, tuple)):
4344688Sgblack@eecs.umich.edu                    raise Exception, "flags must be a list or tuple of flags"
4354688Sgblack@eecs.umich.edu                self.ext = " | ".join(flags)
4364688Sgblack@eecs.umich.edu                self.className += "Flags"
4374519Sgblack@eecs.umich.edu
4384519Sgblack@eecs.umich.edu        def getAllocator(self, *microFlags):
4395040Sgblack@eecs.umich.edu            className = self.className
4405040Sgblack@eecs.umich.edu            if self.mnemonic == self.base_mnemonic + 'i':
4415040Sgblack@eecs.umich.edu                className += "Imm"
4425788Sgblack@eecs.umich.edu            allocator = '''new %(class_name)s(machInst, macrocodeBlock
4435040Sgblack@eecs.umich.edu                    %(flags)s, %(src1)s, %(op2)s, %(dest)s,
4444688Sgblack@eecs.umich.edu                    %(dataSize)s, %(ext)s)''' % {
4455040Sgblack@eecs.umich.edu                "class_name" : className,
4464519Sgblack@eecs.umich.edu                "flags" : self.microFlagsText(microFlags),
4475040Sgblack@eecs.umich.edu                "src1" : self.src1, "op2" : self.op2,
4484519Sgblack@eecs.umich.edu                "dest" : self.dest,
4494519Sgblack@eecs.umich.edu                "dataSize" : self.dataSize,
4504519Sgblack@eecs.umich.edu                "ext" : self.ext}
4514539Sgblack@eecs.umich.edu            return allocator
4524519Sgblack@eecs.umich.edu
4535040Sgblack@eecs.umich.edu    class LogicRegOp(RegOp):
4544688Sgblack@eecs.umich.edu        abstract = True
4555040Sgblack@eecs.umich.edu        flag_code = '''
4565040Sgblack@eecs.umich.edu            //Don't have genFlags handle the OF or CF bits
4575115Sgblack@eecs.umich.edu            uint64_t mask = CFBit | ECFBit | OFBit;
4585040Sgblack@eecs.umich.edu            ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2);
4595040Sgblack@eecs.umich.edu            //If a logic microop wants to set these, it wants to set them to 0.
4605040Sgblack@eecs.umich.edu            ccFlagBits &= ~(CFBit & ext);
4615115Sgblack@eecs.umich.edu            ccFlagBits &= ~(ECFBit & ext);
4625040Sgblack@eecs.umich.edu            ccFlagBits &= ~(OFBit & ext);
4635040Sgblack@eecs.umich.edu        '''
4644519Sgblack@eecs.umich.edu
4655040Sgblack@eecs.umich.edu    class FlagRegOp(RegOp):
4665040Sgblack@eecs.umich.edu        abstract = True
4675040Sgblack@eecs.umich.edu        flag_code = \
4685040Sgblack@eecs.umich.edu            "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);"
4694519Sgblack@eecs.umich.edu
4705040Sgblack@eecs.umich.edu    class SubRegOp(RegOp):
4715040Sgblack@eecs.umich.edu        abstract = True
4725040Sgblack@eecs.umich.edu        flag_code = \
4735040Sgblack@eecs.umich.edu            "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);"
4744519Sgblack@eecs.umich.edu
4755040Sgblack@eecs.umich.edu    class CondRegOp(RegOp):
4765040Sgblack@eecs.umich.edu        abstract = True
4775083Sgblack@eecs.umich.edu        cond_check = "checkCondition(ccFlagBits, ext)"
4784519Sgblack@eecs.umich.edu
4795063Sgblack@eecs.umich.edu    class RdRegOp(RegOp):
4805063Sgblack@eecs.umich.edu        abstract = True
4815063Sgblack@eecs.umich.edu        def __init__(self, dest, src1=None, dataSize="env.dataSize"):
4825063Sgblack@eecs.umich.edu            if not src1:
4835063Sgblack@eecs.umich.edu                src1 = dest
4846345Sgblack@eecs.umich.edu            super(RdRegOp, self).__init__(dest, src1, \
4856345Sgblack@eecs.umich.edu                    "InstRegIndex(NUM_INTREGS)", None, dataSize)
4865063Sgblack@eecs.umich.edu
4875063Sgblack@eecs.umich.edu    class WrRegOp(RegOp):
4885063Sgblack@eecs.umich.edu        abstract = True
4895063Sgblack@eecs.umich.edu        def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
4906345Sgblack@eecs.umich.edu            super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \
4916345Sgblack@eecs.umich.edu                    src1, src2, flags, dataSize)
4925063Sgblack@eecs.umich.edu
4935040Sgblack@eecs.umich.edu    class Add(FlagRegOp):
4945040Sgblack@eecs.umich.edu        code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);'
4954595Sgblack@eecs.umich.edu
4965040Sgblack@eecs.umich.edu    class Or(LogicRegOp):
4975040Sgblack@eecs.umich.edu        code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);'
4984595Sgblack@eecs.umich.edu
4995040Sgblack@eecs.umich.edu    class Adc(FlagRegOp):
5005040Sgblack@eecs.umich.edu        code = '''
5014732Sgblack@eecs.umich.edu            CCFlagBits flags = ccFlagBits;
5025138Sgblack@eecs.umich.edu            DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize);
5035040Sgblack@eecs.umich.edu            '''
5045040Sgblack@eecs.umich.edu
5055040Sgblack@eecs.umich.edu    class Sbb(SubRegOp):
5065040Sgblack@eecs.umich.edu        code = '''
5074732Sgblack@eecs.umich.edu            CCFlagBits flags = ccFlagBits;
5085138Sgblack@eecs.umich.edu            DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize);
5095040Sgblack@eecs.umich.edu            '''
5105040Sgblack@eecs.umich.edu
5115040Sgblack@eecs.umich.edu    class And(LogicRegOp):
5125040Sgblack@eecs.umich.edu        code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)'
5135040Sgblack@eecs.umich.edu
5145040Sgblack@eecs.umich.edu    class Sub(SubRegOp):
5155040Sgblack@eecs.umich.edu        code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)'
5165040Sgblack@eecs.umich.edu
5175040Sgblack@eecs.umich.edu    class Xor(LogicRegOp):
5185040Sgblack@eecs.umich.edu        code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)'
5195040Sgblack@eecs.umich.edu
5205063Sgblack@eecs.umich.edu    class Mul1s(WrRegOp):
5215040Sgblack@eecs.umich.edu        code = '''
5225063Sgblack@eecs.umich.edu            ProdLow = psrc1 * op2;
5235063Sgblack@eecs.umich.edu            int halfSize = (dataSize * 8) / 2;
5246430Sgblack@eecs.umich.edu            uint64_t shifter = (1ULL << halfSize);
5256430Sgblack@eecs.umich.edu            uint64_t hiResult;
5266430Sgblack@eecs.umich.edu            uint64_t psrc1_h = psrc1 / shifter;
5276430Sgblack@eecs.umich.edu            uint64_t psrc1_l = psrc1 & mask(halfSize);
5286430Sgblack@eecs.umich.edu            uint64_t psrc2_h = op2 / shifter;
5296430Sgblack@eecs.umich.edu            uint64_t psrc2_l = op2 & mask(halfSize);
5306430Sgblack@eecs.umich.edu            hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
5316430Sgblack@eecs.umich.edu                        ((psrc1_l * psrc2_l) / shifter)) /shifter) +
5326430Sgblack@eecs.umich.edu                       psrc1_h * psrc2_h;
5336430Sgblack@eecs.umich.edu            if (spsrc1 < 0)
5346430Sgblack@eecs.umich.edu                hiResult -= op2;
5356430Sgblack@eecs.umich.edu            int64_t bigSop2 = sop2;
5366430Sgblack@eecs.umich.edu            if (bigSop2 < 0)
5376430Sgblack@eecs.umich.edu                hiResult -= psrc1;
5386430Sgblack@eecs.umich.edu            ProdHi = hiResult;
5395040Sgblack@eecs.umich.edu            '''
5405040Sgblack@eecs.umich.edu
5415063Sgblack@eecs.umich.edu    class Mul1u(WrRegOp):
5425040Sgblack@eecs.umich.edu        code = '''
5435063Sgblack@eecs.umich.edu            ProdLow = psrc1 * op2;
5444809Sgblack@eecs.umich.edu            int halfSize = (dataSize * 8) / 2;
5456430Sgblack@eecs.umich.edu            uint64_t shifter = (1ULL << halfSize);
5466430Sgblack@eecs.umich.edu            uint64_t psrc1_h = psrc1 / shifter;
5475063Sgblack@eecs.umich.edu            uint64_t psrc1_l = psrc1 & mask(halfSize);
5486430Sgblack@eecs.umich.edu            uint64_t psrc2_h = op2 / shifter;
5495063Sgblack@eecs.umich.edu            uint64_t psrc2_l = op2 & mask(halfSize);
5505063Sgblack@eecs.umich.edu            ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l +
5516430Sgblack@eecs.umich.edu                      ((psrc1_l * psrc2_l) / shifter)) / shifter) +
5525063Sgblack@eecs.umich.edu                     psrc1_h * psrc2_h;
5535040Sgblack@eecs.umich.edu            '''
5545040Sgblack@eecs.umich.edu
5555063Sgblack@eecs.umich.edu    class Mulel(RdRegOp):
5565063Sgblack@eecs.umich.edu        code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);'
5575040Sgblack@eecs.umich.edu
5585063Sgblack@eecs.umich.edu    class Muleh(RdRegOp):
5595063Sgblack@eecs.umich.edu        def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"):
5605063Sgblack@eecs.umich.edu            if not src1:
5615063Sgblack@eecs.umich.edu                src1 = dest
5626345Sgblack@eecs.umich.edu            super(RdRegOp, self).__init__(dest, src1, \
5636345Sgblack@eecs.umich.edu                    "InstRegIndex(NUM_INTREGS)", flags, dataSize)
5645063Sgblack@eecs.umich.edu        code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);'
5655063Sgblack@eecs.umich.edu        flag_code = '''
5665063Sgblack@eecs.umich.edu            if (ProdHi)
5675063Sgblack@eecs.umich.edu                ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
5685063Sgblack@eecs.umich.edu            else
5695063Sgblack@eecs.umich.edu                ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
5705063Sgblack@eecs.umich.edu        '''
5715062Sgblack@eecs.umich.edu
5725075Sgblack@eecs.umich.edu    # One or two bit divide
5735075Sgblack@eecs.umich.edu    class Div1(WrRegOp):
5745040Sgblack@eecs.umich.edu        code = '''
5755075Sgblack@eecs.umich.edu            //These are temporaries so that modifying them later won't make
5765075Sgblack@eecs.umich.edu            //the ISA parser think they're also sources.
5775075Sgblack@eecs.umich.edu            uint64_t quotient = 0;
5785075Sgblack@eecs.umich.edu            uint64_t remainder = psrc1;
5795075Sgblack@eecs.umich.edu            //Similarly, this is a temporary so changing it doesn't make it
5805075Sgblack@eecs.umich.edu            //a source.
5815075Sgblack@eecs.umich.edu            uint64_t divisor = op2;
5825075Sgblack@eecs.umich.edu            //This is a temporary just for consistency and clarity.
5835075Sgblack@eecs.umich.edu            uint64_t dividend = remainder;
5845075Sgblack@eecs.umich.edu            //Do the division.
5855075Sgblack@eecs.umich.edu            divide(dividend, divisor, quotient, remainder);
5865075Sgblack@eecs.umich.edu            //Record the final results.
5875075Sgblack@eecs.umich.edu            Remainder = remainder;
5885075Sgblack@eecs.umich.edu            Quotient = quotient;
5895075Sgblack@eecs.umich.edu            Divisor = divisor;
5905040Sgblack@eecs.umich.edu            '''
5914823Sgblack@eecs.umich.edu
5925075Sgblack@eecs.umich.edu    # Step divide
5935075Sgblack@eecs.umich.edu    class Div2(RegOp):
5945075Sgblack@eecs.umich.edu        code = '''
5955075Sgblack@eecs.umich.edu            uint64_t dividend = Remainder;
5965075Sgblack@eecs.umich.edu            uint64_t divisor = Divisor;
5975075Sgblack@eecs.umich.edu            uint64_t quotient = Quotient;
5985075Sgblack@eecs.umich.edu            uint64_t remainder = dividend;
5995075Sgblack@eecs.umich.edu            int remaining = op2;
6005075Sgblack@eecs.umich.edu            //If we overshot, do nothing. This lets us unrool division loops a
6015075Sgblack@eecs.umich.edu            //little.
6025075Sgblack@eecs.umich.edu            if (remaining) {
6035075Sgblack@eecs.umich.edu                //Shift in bits from the low order portion of the dividend
6045075Sgblack@eecs.umich.edu                while(dividend < divisor && remaining) {
6055075Sgblack@eecs.umich.edu                    dividend = (dividend << 1) | bits(SrcReg1, remaining - 1);
6065075Sgblack@eecs.umich.edu                    quotient <<= 1;
6075075Sgblack@eecs.umich.edu                    remaining--;
6085075Sgblack@eecs.umich.edu                }
6095075Sgblack@eecs.umich.edu                remainder = dividend;
6105075Sgblack@eecs.umich.edu                //Do the division.
6115075Sgblack@eecs.umich.edu                divide(dividend, divisor, quotient, remainder);
6125075Sgblack@eecs.umich.edu            }
6135075Sgblack@eecs.umich.edu            //Keep track of how many bits there are still to pull in.
6145075Sgblack@eecs.umich.edu            DestReg = merge(DestReg, remaining, dataSize);
6155075Sgblack@eecs.umich.edu            //Record the final results
6165075Sgblack@eecs.umich.edu            Remainder = remainder;
6175075Sgblack@eecs.umich.edu            Quotient = quotient;
6185075Sgblack@eecs.umich.edu        '''
6195075Sgblack@eecs.umich.edu        flag_code = '''
6205075Sgblack@eecs.umich.edu            if (DestReg == 0)
6215075Sgblack@eecs.umich.edu                ccFlagBits = ccFlagBits | (ext & EZFBit);
6225075Sgblack@eecs.umich.edu            else
6235075Sgblack@eecs.umich.edu                ccFlagBits = ccFlagBits & ~(ext & EZFBit);
6245075Sgblack@eecs.umich.edu        '''
6254732Sgblack@eecs.umich.edu
6265075Sgblack@eecs.umich.edu    class Divq(RdRegOp):
6275075Sgblack@eecs.umich.edu        code = 'DestReg = merge(SrcReg1, Quotient, dataSize);'
6285075Sgblack@eecs.umich.edu
6295075Sgblack@eecs.umich.edu    class Divr(RdRegOp):
6305075Sgblack@eecs.umich.edu        code = 'DestReg = merge(SrcReg1, Remainder, dataSize);'
6315040Sgblack@eecs.umich.edu
6325040Sgblack@eecs.umich.edu    class Mov(CondRegOp):
6335040Sgblack@eecs.umich.edu        code = 'DestReg = merge(SrcReg1, op2, dataSize)'
6345040Sgblack@eecs.umich.edu        else_code = 'DestReg=DestReg;'
6355040Sgblack@eecs.umich.edu
6364732Sgblack@eecs.umich.edu    # Shift instructions
6375040Sgblack@eecs.umich.edu
6385076Sgblack@eecs.umich.edu    class Sll(RegOp):
6395040Sgblack@eecs.umich.edu        code = '''
6404756Sgblack@eecs.umich.edu            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
6414823Sgblack@eecs.umich.edu            DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
6425040Sgblack@eecs.umich.edu            '''
6435076Sgblack@eecs.umich.edu        flag_code = '''
6445076Sgblack@eecs.umich.edu            // If the shift amount is zero, no flags should be modified.
6455076Sgblack@eecs.umich.edu            if (shiftAmt) {
6465076Sgblack@eecs.umich.edu                //Zero out any flags we might modify. This way we only have to
6475076Sgblack@eecs.umich.edu                //worry about setting them.
6485076Sgblack@eecs.umich.edu                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
6495076Sgblack@eecs.umich.edu                int CFBits = 0;
6505076Sgblack@eecs.umich.edu                //Figure out if we -would- set the CF bits if requested.
6515076Sgblack@eecs.umich.edu                if (bits(SrcReg1, dataSize * 8 - shiftAmt))
6525076Sgblack@eecs.umich.edu                    CFBits = 1;
6535076Sgblack@eecs.umich.edu                //If some combination of the CF bits need to be set, set them.
6545076Sgblack@eecs.umich.edu                if ((ext & (CFBit | ECFBit)) && CFBits)
6555076Sgblack@eecs.umich.edu                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
6565076Sgblack@eecs.umich.edu                //Figure out what the OF bit should be.
6575076Sgblack@eecs.umich.edu                if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1)))
6585076Sgblack@eecs.umich.edu                    ccFlagBits = ccFlagBits | OFBit;
6595076Sgblack@eecs.umich.edu                //Use the regular mechanisms to calculate the other flags.
6605076Sgblack@eecs.umich.edu                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
6615076Sgblack@eecs.umich.edu                        DestReg, psrc1, op2);
6625076Sgblack@eecs.umich.edu            }
6635076Sgblack@eecs.umich.edu        '''
6645040Sgblack@eecs.umich.edu
6655076Sgblack@eecs.umich.edu    class Srl(RegOp):
6665040Sgblack@eecs.umich.edu        code = '''
6674756Sgblack@eecs.umich.edu            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
6684732Sgblack@eecs.umich.edu            // Because what happens to the bits shift -in- on a right shift
6694732Sgblack@eecs.umich.edu            // is not defined in the C/C++ standard, we have to mask them out
6704732Sgblack@eecs.umich.edu            // to be sure they're zero.
6714732Sgblack@eecs.umich.edu            uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
6724823Sgblack@eecs.umich.edu            DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
6735040Sgblack@eecs.umich.edu            '''
6745076Sgblack@eecs.umich.edu        flag_code = '''
6755076Sgblack@eecs.umich.edu            // If the shift amount is zero, no flags should be modified.
6765076Sgblack@eecs.umich.edu            if (shiftAmt) {
6775076Sgblack@eecs.umich.edu                //Zero out any flags we might modify. This way we only have to
6785076Sgblack@eecs.umich.edu                //worry about setting them.
6795076Sgblack@eecs.umich.edu                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
6805076Sgblack@eecs.umich.edu                //If some combination of the CF bits need to be set, set them.
6815076Sgblack@eecs.umich.edu                if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1))
6825076Sgblack@eecs.umich.edu                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
6835076Sgblack@eecs.umich.edu                //Figure out what the OF bit should be.
6845076Sgblack@eecs.umich.edu                if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1))
6855076Sgblack@eecs.umich.edu                    ccFlagBits = ccFlagBits | OFBit;
6865076Sgblack@eecs.umich.edu                //Use the regular mechanisms to calculate the other flags.
6875076Sgblack@eecs.umich.edu                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
6885076Sgblack@eecs.umich.edu                        DestReg, psrc1, op2);
6895076Sgblack@eecs.umich.edu            }
6905076Sgblack@eecs.umich.edu        '''
6915040Sgblack@eecs.umich.edu
6925076Sgblack@eecs.umich.edu    class Sra(RegOp):
6935040Sgblack@eecs.umich.edu        code = '''
6944756Sgblack@eecs.umich.edu            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
6954732Sgblack@eecs.umich.edu            // Because what happens to the bits shift -in- on a right shift
6964732Sgblack@eecs.umich.edu            // is not defined in the C/C++ standard, we have to sign extend
6974732Sgblack@eecs.umich.edu            // them manually to be sure.
6984732Sgblack@eecs.umich.edu            uint64_t arithMask =
6995032Sgblack@eecs.umich.edu                -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
7004823Sgblack@eecs.umich.edu            DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
7015040Sgblack@eecs.umich.edu            '''
7025076Sgblack@eecs.umich.edu        flag_code = '''
7035076Sgblack@eecs.umich.edu            // If the shift amount is zero, no flags should be modified.
7045076Sgblack@eecs.umich.edu            if (shiftAmt) {
7055076Sgblack@eecs.umich.edu                //Zero out any flags we might modify. This way we only have to
7065076Sgblack@eecs.umich.edu                //worry about setting them.
7075076Sgblack@eecs.umich.edu                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
7085076Sgblack@eecs.umich.edu                //If some combination of the CF bits need to be set, set them.
7095076Sgblack@eecs.umich.edu                if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1))
7105076Sgblack@eecs.umich.edu                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
7115076Sgblack@eecs.umich.edu                //Use the regular mechanisms to calculate the other flags.
7125076Sgblack@eecs.umich.edu                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
7135076Sgblack@eecs.umich.edu                        DestReg, psrc1, op2);
7145076Sgblack@eecs.umich.edu            }
7155076Sgblack@eecs.umich.edu        '''
7165040Sgblack@eecs.umich.edu
7175076Sgblack@eecs.umich.edu    class Ror(RegOp):
7185040Sgblack@eecs.umich.edu        code = '''
7194732Sgblack@eecs.umich.edu            uint8_t shiftAmt =
7204756Sgblack@eecs.umich.edu                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
7214732Sgblack@eecs.umich.edu            if(shiftAmt)
7224732Sgblack@eecs.umich.edu            {
7234823Sgblack@eecs.umich.edu                uint64_t top = psrc1 << (dataSize * 8 - shiftAmt);
7244823Sgblack@eecs.umich.edu                uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
7254732Sgblack@eecs.umich.edu                DestReg = merge(DestReg, top | bottom, dataSize);
7264732Sgblack@eecs.umich.edu            }
7274732Sgblack@eecs.umich.edu            else
7284732Sgblack@eecs.umich.edu                DestReg = DestReg;
7295040Sgblack@eecs.umich.edu            '''
7305076Sgblack@eecs.umich.edu        flag_code = '''
7315076Sgblack@eecs.umich.edu            // If the shift amount is zero, no flags should be modified.
7325076Sgblack@eecs.umich.edu            if (shiftAmt) {
7335076Sgblack@eecs.umich.edu                //Zero out any flags we might modify. This way we only have to
7345076Sgblack@eecs.umich.edu                //worry about setting them.
7355076Sgblack@eecs.umich.edu                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
7365076Sgblack@eecs.umich.edu                //Find the most and second most significant bits of the result.
7375076Sgblack@eecs.umich.edu                int msb = bits(DestReg, dataSize * 8 - 1);
7385076Sgblack@eecs.umich.edu                int smsb = bits(DestReg, dataSize * 8 - 2);
7395076Sgblack@eecs.umich.edu                //If some combination of the CF bits need to be set, set them.
7405076Sgblack@eecs.umich.edu                if ((ext & (CFBit | ECFBit)) && msb)
7415076Sgblack@eecs.umich.edu                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
7425076Sgblack@eecs.umich.edu                //Figure out what the OF bit should be.
7435076Sgblack@eecs.umich.edu                if ((ext & OFBit) && (msb ^ smsb))
7445076Sgblack@eecs.umich.edu                    ccFlagBits = ccFlagBits | OFBit;
7455076Sgblack@eecs.umich.edu                //Use the regular mechanisms to calculate the other flags.
7465076Sgblack@eecs.umich.edu                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
7475076Sgblack@eecs.umich.edu                        DestReg, psrc1, op2);
7485076Sgblack@eecs.umich.edu            }
7495076Sgblack@eecs.umich.edu        '''
7505040Sgblack@eecs.umich.edu
7515076Sgblack@eecs.umich.edu    class Rcr(RegOp):
7525040Sgblack@eecs.umich.edu        code = '''
7534733Sgblack@eecs.umich.edu            uint8_t shiftAmt =
7544756Sgblack@eecs.umich.edu                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
7554733Sgblack@eecs.umich.edu            if(shiftAmt)
7564733Sgblack@eecs.umich.edu            {
7574733Sgblack@eecs.umich.edu                CCFlagBits flags = ccFlagBits;
7585138Sgblack@eecs.umich.edu                uint64_t top = flags.cf << (dataSize * 8 - shiftAmt);
7594733Sgblack@eecs.umich.edu                if(shiftAmt > 1)
7604823Sgblack@eecs.umich.edu                    top |= psrc1 << (dataSize * 8 - shiftAmt - 1);
7614823Sgblack@eecs.umich.edu                uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
7624733Sgblack@eecs.umich.edu                DestReg = merge(DestReg, top | bottom, dataSize);
7634733Sgblack@eecs.umich.edu            }
7644733Sgblack@eecs.umich.edu            else
7654733Sgblack@eecs.umich.edu                DestReg = DestReg;
7665040Sgblack@eecs.umich.edu            '''
7675076Sgblack@eecs.umich.edu        flag_code = '''
7685076Sgblack@eecs.umich.edu            // If the shift amount is zero, no flags should be modified.
7695076Sgblack@eecs.umich.edu            if (shiftAmt) {
7705076Sgblack@eecs.umich.edu                //Zero out any flags we might modify. This way we only have to
7715076Sgblack@eecs.umich.edu                //worry about setting them.
7725076Sgblack@eecs.umich.edu                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
7735076Sgblack@eecs.umich.edu                //Figure out what the OF bit should be.
7745076Sgblack@eecs.umich.edu                if ((ext & OFBit) && ((ccFlagBits & CFBit) ^
7755076Sgblack@eecs.umich.edu                                      bits(SrcReg1, dataSize * 8 - 1)))
7765076Sgblack@eecs.umich.edu                    ccFlagBits = ccFlagBits | OFBit;
7775076Sgblack@eecs.umich.edu                //If some combination of the CF bits need to be set, set them.
7785076Sgblack@eecs.umich.edu                if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1))
7795076Sgblack@eecs.umich.edu                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
7805076Sgblack@eecs.umich.edu                //Use the regular mechanisms to calculate the other flags.
7815076Sgblack@eecs.umich.edu                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
7825076Sgblack@eecs.umich.edu                        DestReg, psrc1, op2);
7835076Sgblack@eecs.umich.edu            }
7845076Sgblack@eecs.umich.edu        '''
7855040Sgblack@eecs.umich.edu
7865076Sgblack@eecs.umich.edu    class Rol(RegOp):
7875040Sgblack@eecs.umich.edu        code = '''
7884732Sgblack@eecs.umich.edu            uint8_t shiftAmt =
7894756Sgblack@eecs.umich.edu                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
7904732Sgblack@eecs.umich.edu            if(shiftAmt)
7914732Sgblack@eecs.umich.edu            {
7924823Sgblack@eecs.umich.edu                uint64_t top = psrc1 << shiftAmt;
7934732Sgblack@eecs.umich.edu                uint64_t bottom =
7944823Sgblack@eecs.umich.edu                    bits(psrc1, dataSize * 8 - 1, dataSize * 8 - shiftAmt);
7954732Sgblack@eecs.umich.edu                DestReg = merge(DestReg, top | bottom, dataSize);
7964732Sgblack@eecs.umich.edu            }
7974732Sgblack@eecs.umich.edu            else
7984732Sgblack@eecs.umich.edu                DestReg = DestReg;
7995040Sgblack@eecs.umich.edu            '''
8005076Sgblack@eecs.umich.edu        flag_code = '''
8015076Sgblack@eecs.umich.edu            // If the shift amount is zero, no flags should be modified.
8025076Sgblack@eecs.umich.edu            if (shiftAmt) {
8035076Sgblack@eecs.umich.edu                //Zero out any flags we might modify. This way we only have to
8045076Sgblack@eecs.umich.edu                //worry about setting them.
8055076Sgblack@eecs.umich.edu                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
8065076Sgblack@eecs.umich.edu                //The CF bits, if set, would be set to the lsb of the result.
8075076Sgblack@eecs.umich.edu                int lsb = DestReg & 0x1;
8085076Sgblack@eecs.umich.edu                int msb = bits(DestReg, dataSize * 8 - 1);
8095076Sgblack@eecs.umich.edu                //If some combination of the CF bits need to be set, set them.
8105076Sgblack@eecs.umich.edu                if ((ext & (CFBit | ECFBit)) && lsb)
8115076Sgblack@eecs.umich.edu                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
8125076Sgblack@eecs.umich.edu                //Figure out what the OF bit should be.
8135076Sgblack@eecs.umich.edu                if ((ext & OFBit) && (msb ^ lsb))
8145076Sgblack@eecs.umich.edu                    ccFlagBits = ccFlagBits | OFBit;
8155076Sgblack@eecs.umich.edu                //Use the regular mechanisms to calculate the other flags.
8165076Sgblack@eecs.umich.edu                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
8175076Sgblack@eecs.umich.edu                        DestReg, psrc1, op2);
8185076Sgblack@eecs.umich.edu            }
8195076Sgblack@eecs.umich.edu        '''
8205040Sgblack@eecs.umich.edu
8215076Sgblack@eecs.umich.edu    class Rcl(RegOp):
8225040Sgblack@eecs.umich.edu        code = '''
8234733Sgblack@eecs.umich.edu            uint8_t shiftAmt =
8244756Sgblack@eecs.umich.edu                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
8254733Sgblack@eecs.umich.edu            if(shiftAmt)
8264733Sgblack@eecs.umich.edu            {
8274733Sgblack@eecs.umich.edu                CCFlagBits flags = ccFlagBits;
8284823Sgblack@eecs.umich.edu                uint64_t top = psrc1 << shiftAmt;
8295138Sgblack@eecs.umich.edu                uint64_t bottom = flags.cf << (shiftAmt - 1);
8304733Sgblack@eecs.umich.edu                if(shiftAmt > 1)
8314733Sgblack@eecs.umich.edu                    bottom |=
8324823Sgblack@eecs.umich.edu                        bits(psrc1, dataSize * 8 - 1,
8334809Sgblack@eecs.umich.edu                                   dataSize * 8 - shiftAmt + 1);
8344733Sgblack@eecs.umich.edu                DestReg = merge(DestReg, top | bottom, dataSize);
8354733Sgblack@eecs.umich.edu            }
8364733Sgblack@eecs.umich.edu            else
8374733Sgblack@eecs.umich.edu                DestReg = DestReg;
8385040Sgblack@eecs.umich.edu            '''
8395076Sgblack@eecs.umich.edu        flag_code = '''
8405076Sgblack@eecs.umich.edu            // If the shift amount is zero, no flags should be modified.
8415076Sgblack@eecs.umich.edu            if (shiftAmt) {
8425076Sgblack@eecs.umich.edu                //Zero out any flags we might modify. This way we only have to
8435076Sgblack@eecs.umich.edu                //worry about setting them.
8445076Sgblack@eecs.umich.edu                ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
8455076Sgblack@eecs.umich.edu                int msb = bits(DestReg, dataSize * 8 - 1);
8465076Sgblack@eecs.umich.edu                int CFBits = bits(SrcReg1, dataSize * 8 - shiftAmt);
8475076Sgblack@eecs.umich.edu                //If some combination of the CF bits need to be set, set them.
8485076Sgblack@eecs.umich.edu                if ((ext & (CFBit | ECFBit)) && CFBits)
8495076Sgblack@eecs.umich.edu                    ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
8505076Sgblack@eecs.umich.edu                //Figure out what the OF bit should be.
8515076Sgblack@eecs.umich.edu                if ((ext & OFBit) && (msb ^ CFBits))
8525076Sgblack@eecs.umich.edu                    ccFlagBits = ccFlagBits | OFBit;
8535076Sgblack@eecs.umich.edu                //Use the regular mechanisms to calculate the other flags.
8545076Sgblack@eecs.umich.edu                ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit),
8555076Sgblack@eecs.umich.edu                        DestReg, psrc1, op2);
8565076Sgblack@eecs.umich.edu            }
8575076Sgblack@eecs.umich.edu        '''
8584732Sgblack@eecs.umich.edu
8595040Sgblack@eecs.umich.edu    class Wrip(WrRegOp, CondRegOp):
8605246Sgblack@eecs.umich.edu        code = 'RIP = psrc1 + sop2 + CSBase'
8615040Sgblack@eecs.umich.edu        else_code="RIP = RIP;"
8625040Sgblack@eecs.umich.edu
8635040Sgblack@eecs.umich.edu    class Wruflags(WrRegOp):
8645040Sgblack@eecs.umich.edu        code = 'ccFlagBits = psrc1 ^ op2'
8655040Sgblack@eecs.umich.edu
8665426Sgblack@eecs.umich.edu    class Wrflags(WrRegOp):
8675426Sgblack@eecs.umich.edu        code = '''
8685426Sgblack@eecs.umich.edu            MiscReg newFlags = psrc1 ^ op2;
8695426Sgblack@eecs.umich.edu            MiscReg userFlagMask = 0xDD5;
8705426Sgblack@eecs.umich.edu            // Get only the user flags
8715426Sgblack@eecs.umich.edu            ccFlagBits = newFlags & userFlagMask;
8725426Sgblack@eecs.umich.edu            // Get everything else
8735426Sgblack@eecs.umich.edu            nccFlagBits = newFlags & ~userFlagMask;
8745426Sgblack@eecs.umich.edu        '''
8755426Sgblack@eecs.umich.edu
8765040Sgblack@eecs.umich.edu    class Rdip(RdRegOp):
8775246Sgblack@eecs.umich.edu        code = 'DestReg = RIP - CSBase'
8785040Sgblack@eecs.umich.edu
8795040Sgblack@eecs.umich.edu    class Ruflags(RdRegOp):
8805040Sgblack@eecs.umich.edu        code = 'DestReg = ccFlagBits'
8815040Sgblack@eecs.umich.edu
8825426Sgblack@eecs.umich.edu    class Rflags(RdRegOp):
8835426Sgblack@eecs.umich.edu        code = 'DestReg = ccFlagBits | nccFlagBits'
8845426Sgblack@eecs.umich.edu
8855040Sgblack@eecs.umich.edu    class Ruflag(RegOp):
8865040Sgblack@eecs.umich.edu        code = '''
8875116Sgblack@eecs.umich.edu            int flag = bits(ccFlagBits, imm8);
8884951Sgblack@eecs.umich.edu            DestReg = merge(DestReg, flag, dataSize);
8895011Sgblack@eecs.umich.edu            ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
8905011Sgblack@eecs.umich.edu                                       (ccFlagBits & ~EZFBit);
8915040Sgblack@eecs.umich.edu            '''
8925040Sgblack@eecs.umich.edu        def __init__(self, dest, imm, flags=None, \
8935040Sgblack@eecs.umich.edu                dataSize="env.dataSize"):
8945040Sgblack@eecs.umich.edu            super(Ruflag, self).__init__(dest, \
8956345Sgblack@eecs.umich.edu                    "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
8964732Sgblack@eecs.umich.edu
8975426Sgblack@eecs.umich.edu    class Rflag(RegOp):
8985426Sgblack@eecs.umich.edu        code = '''
8995426Sgblack@eecs.umich.edu            MiscReg flagMask = 0x3F7FDD5;
9005426Sgblack@eecs.umich.edu            MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask;
9015426Sgblack@eecs.umich.edu            int flag = bits(flags, imm8);
9025426Sgblack@eecs.umich.edu            DestReg = merge(DestReg, flag, dataSize);
9035426Sgblack@eecs.umich.edu            ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) :
9045426Sgblack@eecs.umich.edu                                       (ccFlagBits & ~EZFBit);
9055426Sgblack@eecs.umich.edu            '''
9065426Sgblack@eecs.umich.edu        def __init__(self, dest, imm, flags=None, \
9075426Sgblack@eecs.umich.edu                dataSize="env.dataSize"):
9085426Sgblack@eecs.umich.edu            super(Rflag, self).__init__(dest, \
9096345Sgblack@eecs.umich.edu                    "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize)
9105426Sgblack@eecs.umich.edu
9115040Sgblack@eecs.umich.edu    class Sext(RegOp):
9125040Sgblack@eecs.umich.edu        code = '''
9134823Sgblack@eecs.umich.edu            IntReg val = psrc1;
9145239Sgblack@eecs.umich.edu            // Mask the bit position so that it wraps.
9155239Sgblack@eecs.umich.edu            int bitPos = op2 & (dataSize * 8 - 1);
9165239Sgblack@eecs.umich.edu            int sign_bit = bits(val, bitPos, bitPos);
9175239Sgblack@eecs.umich.edu            uint64_t maskVal = mask(bitPos+1);
9185007Sgblack@eecs.umich.edu            val = sign_bit ? (val | ~maskVal) : (val & maskVal);
9195007Sgblack@eecs.umich.edu            DestReg = merge(DestReg, val, dataSize);
9205040Sgblack@eecs.umich.edu            '''
9215239Sgblack@eecs.umich.edu        flag_code = '''
9225239Sgblack@eecs.umich.edu            if (!sign_bit)
9235239Sgblack@eecs.umich.edu                ccFlagBits = ccFlagBits &
9245239Sgblack@eecs.umich.edu                    ~(ext & (CFBit | ECFBit | ZFBit | EZFBit));
9255239Sgblack@eecs.umich.edu            else
9265239Sgblack@eecs.umich.edu                ccFlagBits = ccFlagBits |
9275239Sgblack@eecs.umich.edu                    (ext & (CFBit | ECFBit | ZFBit | EZFBit));
9285239Sgblack@eecs.umich.edu            '''
9294714Sgblack@eecs.umich.edu
9305040Sgblack@eecs.umich.edu    class Zext(RegOp):
9315927Sgblack@eecs.umich.edu        code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);'
9325241Sgblack@eecs.umich.edu
9335926Sgblack@eecs.umich.edu    class Rddr(RegOp):
9345926Sgblack@eecs.umich.edu        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
9355926Sgblack@eecs.umich.edu            super(Rddr, self).__init__(dest, \
9366345Sgblack@eecs.umich.edu                    src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
9375926Sgblack@eecs.umich.edu        code = '''
9385926Sgblack@eecs.umich.edu            CR4 cr4 = CR4Op;
9395926Sgblack@eecs.umich.edu            DR7 dr7 = DR7Op;
9405926Sgblack@eecs.umich.edu            if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) {
9415926Sgblack@eecs.umich.edu                fault = new InvalidOpcode();
9425926Sgblack@eecs.umich.edu            } else if (dr7.gd) {
9435926Sgblack@eecs.umich.edu                fault = new DebugException();
9445926Sgblack@eecs.umich.edu            } else {
9455926Sgblack@eecs.umich.edu                DestReg = merge(DestReg, DebugSrc1, dataSize);
9465926Sgblack@eecs.umich.edu            }
9475926Sgblack@eecs.umich.edu        '''
9485926Sgblack@eecs.umich.edu
9495926Sgblack@eecs.umich.edu    class Wrdr(RegOp):
9505926Sgblack@eecs.umich.edu        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
9515926Sgblack@eecs.umich.edu            super(Wrdr, self).__init__(dest, \
9526345Sgblack@eecs.umich.edu                    src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
9535926Sgblack@eecs.umich.edu        code = '''
9545926Sgblack@eecs.umich.edu            CR4 cr4 = CR4Op;
9555926Sgblack@eecs.umich.edu            DR7 dr7 = DR7Op;
9565926Sgblack@eecs.umich.edu            if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) {
9575926Sgblack@eecs.umich.edu                fault = new InvalidOpcode();
9586345Sgblack@eecs.umich.edu            } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) &&
9595926Sgblack@eecs.umich.edu                    machInst.mode.mode == LongMode) {
9605926Sgblack@eecs.umich.edu                fault = new GeneralProtection(0);
9615926Sgblack@eecs.umich.edu            } else if (dr7.gd) {
9625926Sgblack@eecs.umich.edu                fault = new DebugException();
9635926Sgblack@eecs.umich.edu            } else {
9645926Sgblack@eecs.umich.edu                DebugDest = psrc1;
9655926Sgblack@eecs.umich.edu            }
9665926Sgblack@eecs.umich.edu        '''
9675926Sgblack@eecs.umich.edu
9685296Sgblack@eecs.umich.edu    class Rdcr(RegOp):
9695296Sgblack@eecs.umich.edu        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
9705296Sgblack@eecs.umich.edu            super(Rdcr, self).__init__(dest, \
9716345Sgblack@eecs.umich.edu                    src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
9725296Sgblack@eecs.umich.edu        code = '''
9735924Sgblack@eecs.umich.edu            if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) {
9745296Sgblack@eecs.umich.edu                fault = new InvalidOpcode();
9755296Sgblack@eecs.umich.edu            } else {
9765934Sgblack@eecs.umich.edu                DestReg = merge(DestReg, ControlSrc1, dataSize);
9775296Sgblack@eecs.umich.edu            }
9785296Sgblack@eecs.umich.edu        '''
9795296Sgblack@eecs.umich.edu
9805241Sgblack@eecs.umich.edu    class Wrcr(RegOp):
9815241Sgblack@eecs.umich.edu        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
9825241Sgblack@eecs.umich.edu            super(Wrcr, self).__init__(dest, \
9836345Sgblack@eecs.umich.edu                    src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
9845241Sgblack@eecs.umich.edu        code = '''
9855241Sgblack@eecs.umich.edu            if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) {
9865241Sgblack@eecs.umich.edu                fault = new InvalidOpcode();
9875241Sgblack@eecs.umich.edu            } else {
9885241Sgblack@eecs.umich.edu                // There are *s in the line below so it doesn't confuse the
9895241Sgblack@eecs.umich.edu                // parser. They may be unnecessary.
9905241Sgblack@eecs.umich.edu                //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize);
9915241Sgblack@eecs.umich.edu                MiscReg newVal = psrc1;
9925241Sgblack@eecs.umich.edu
9935241Sgblack@eecs.umich.edu                // Check for any modifications that would cause a fault.
9945241Sgblack@eecs.umich.edu                switch(dest) {
9955241Sgblack@eecs.umich.edu                  case 0:
9965241Sgblack@eecs.umich.edu                    {
9975241Sgblack@eecs.umich.edu                        Efer efer = EferOp;
9985241Sgblack@eecs.umich.edu                        CR0 cr0 = newVal;
9995241Sgblack@eecs.umich.edu                        CR4 oldCr4 = CR4Op;
10005241Sgblack@eecs.umich.edu                        if (bits(newVal, 63, 32) ||
10015241Sgblack@eecs.umich.edu                                (!cr0.pe && cr0.pg) ||
10025241Sgblack@eecs.umich.edu                                (!cr0.cd && cr0.nw) ||
10035241Sgblack@eecs.umich.edu                                (cr0.pg && efer.lme && !oldCr4.pae))
10045241Sgblack@eecs.umich.edu                            fault = new GeneralProtection(0);
10055241Sgblack@eecs.umich.edu                    }
10065241Sgblack@eecs.umich.edu                    break;
10075241Sgblack@eecs.umich.edu                  case 2:
10085241Sgblack@eecs.umich.edu                    break;
10095241Sgblack@eecs.umich.edu                  case 3:
10105241Sgblack@eecs.umich.edu                    break;
10115241Sgblack@eecs.umich.edu                  case 4:
10125241Sgblack@eecs.umich.edu                    {
10135241Sgblack@eecs.umich.edu                        CR4 cr4 = newVal;
10145241Sgblack@eecs.umich.edu                        // PAE can't be disabled in long mode.
10155241Sgblack@eecs.umich.edu                        if (bits(newVal, 63, 11) ||
10165241Sgblack@eecs.umich.edu                                (machInst.mode.mode == LongMode && !cr4.pae))
10175241Sgblack@eecs.umich.edu                            fault = new GeneralProtection(0);
10185241Sgblack@eecs.umich.edu                    }
10195241Sgblack@eecs.umich.edu                    break;
10205241Sgblack@eecs.umich.edu                  case 8:
10215241Sgblack@eecs.umich.edu                    {
10225241Sgblack@eecs.umich.edu                        if (bits(newVal, 63, 4))
10235241Sgblack@eecs.umich.edu                            fault = new GeneralProtection(0);
10245241Sgblack@eecs.umich.edu                    }
10255241Sgblack@eecs.umich.edu                  default:
10265241Sgblack@eecs.umich.edu                    panic("Unrecognized control register %d.\\n", dest);
10275241Sgblack@eecs.umich.edu                }
10285241Sgblack@eecs.umich.edu                ControlDest = newVal;
10295241Sgblack@eecs.umich.edu            }
10305241Sgblack@eecs.umich.edu            '''
10315290Sgblack@eecs.umich.edu
10325294Sgblack@eecs.umich.edu    # Microops for manipulating segmentation registers
10335672Sgblack@eecs.umich.edu    class SegOp(CondRegOp):
10345294Sgblack@eecs.umich.edu        abstract = True
10355290Sgblack@eecs.umich.edu        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
10365294Sgblack@eecs.umich.edu            super(SegOp, self).__init__(dest, \
10376345Sgblack@eecs.umich.edu                    src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize)
10385294Sgblack@eecs.umich.edu
10395294Sgblack@eecs.umich.edu    class Wrbase(SegOp):
10405290Sgblack@eecs.umich.edu        code = '''
10415294Sgblack@eecs.umich.edu            SegBaseDest = psrc1;
10425290Sgblack@eecs.umich.edu        '''
10435290Sgblack@eecs.umich.edu
10445294Sgblack@eecs.umich.edu    class Wrlimit(SegOp):
10455290Sgblack@eecs.umich.edu        code = '''
10465294Sgblack@eecs.umich.edu            SegLimitDest = psrc1;
10475294Sgblack@eecs.umich.edu        '''
10485294Sgblack@eecs.umich.edu
10495294Sgblack@eecs.umich.edu    class Wrsel(SegOp):
10505294Sgblack@eecs.umich.edu        code = '''
10515294Sgblack@eecs.umich.edu            SegSelDest = psrc1;
10525294Sgblack@eecs.umich.edu        '''
10535294Sgblack@eecs.umich.edu
10545905Sgblack@eecs.umich.edu    class WrAttr(SegOp):
10555905Sgblack@eecs.umich.edu        code = '''
10565905Sgblack@eecs.umich.edu            SegAttrDest = psrc1;
10575905Sgblack@eecs.umich.edu        '''
10585905Sgblack@eecs.umich.edu
10595294Sgblack@eecs.umich.edu    class Rdbase(SegOp):
10605294Sgblack@eecs.umich.edu        code = '''
10615932Sgblack@eecs.umich.edu            DestReg = merge(DestReg, SegBaseSrc1, dataSize);
10625294Sgblack@eecs.umich.edu        '''
10635294Sgblack@eecs.umich.edu
10645294Sgblack@eecs.umich.edu    class Rdlimit(SegOp):
10655294Sgblack@eecs.umich.edu        code = '''
10665932Sgblack@eecs.umich.edu            DestReg = merge(DestReg, SegLimitSrc1, dataSize);
10675294Sgblack@eecs.umich.edu        '''
10685294Sgblack@eecs.umich.edu
10695427Sgblack@eecs.umich.edu    class RdAttr(SegOp):
10705427Sgblack@eecs.umich.edu        code = '''
10715932Sgblack@eecs.umich.edu            DestReg = merge(DestReg, SegAttrSrc1, dataSize);
10725427Sgblack@eecs.umich.edu        '''
10735427Sgblack@eecs.umich.edu
10745294Sgblack@eecs.umich.edu    class Rdsel(SegOp):
10755294Sgblack@eecs.umich.edu        code = '''
10765932Sgblack@eecs.umich.edu            DestReg = merge(DestReg, SegSelSrc1, dataSize);
10775294Sgblack@eecs.umich.edu        '''
10785294Sgblack@eecs.umich.edu
10795682Sgblack@eecs.umich.edu    class Rdval(RegOp):
10805682Sgblack@eecs.umich.edu        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
10816345Sgblack@eecs.umich.edu            super(Rdval, self).__init__(dest, src1, \
10826345Sgblack@eecs.umich.edu                    "InstRegIndex(NUM_INTREGS)", flags, dataSize)
10835682Sgblack@eecs.umich.edu        code = '''
10845682Sgblack@eecs.umich.edu            DestReg = MiscRegSrc1;
10855682Sgblack@eecs.umich.edu        '''
10865682Sgblack@eecs.umich.edu
10875682Sgblack@eecs.umich.edu    class Wrval(RegOp):
10885682Sgblack@eecs.umich.edu        def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"):
10896345Sgblack@eecs.umich.edu            super(Wrval, self).__init__(dest, src1, \
10906345Sgblack@eecs.umich.edu                    "InstRegIndex(NUM_INTREGS)", flags, dataSize)
10915682Sgblack@eecs.umich.edu        code = '''
10925682Sgblack@eecs.umich.edu            MiscRegDest = SrcReg1;
10935682Sgblack@eecs.umich.edu        '''
10945682Sgblack@eecs.umich.edu
10955428Sgblack@eecs.umich.edu    class Chks(RegOp):
10965428Sgblack@eecs.umich.edu        def __init__(self, dest, src1, src2=0,
10975428Sgblack@eecs.umich.edu                flags=None, dataSize="env.dataSize"):
10985428Sgblack@eecs.umich.edu            super(Chks, self).__init__(dest,
10995428Sgblack@eecs.umich.edu                    src1, src2, flags, dataSize)
11005294Sgblack@eecs.umich.edu        code = '''
11015424Sgblack@eecs.umich.edu            // The selector is in source 1 and can be at most 16 bits.
11025433Sgblack@eecs.umich.edu            SegSelector selector = DestReg;
11035433Sgblack@eecs.umich.edu            SegDescriptor desc = SrcReg1;
11045433Sgblack@eecs.umich.edu            HandyM5Reg m5reg = M5Reg;
11055294Sgblack@eecs.umich.edu
11065428Sgblack@eecs.umich.edu            switch (imm8)
11075428Sgblack@eecs.umich.edu            {
11085428Sgblack@eecs.umich.edu              case SegNoCheck:
11095428Sgblack@eecs.umich.edu                break;
11105428Sgblack@eecs.umich.edu              case SegCSCheck:
11116060Sgblack@eecs.umich.edu                // Make sure it's the right type
11126060Sgblack@eecs.umich.edu                if (desc.s == 0 || desc.type.codeOrData != 1) {
11136060Sgblack@eecs.umich.edu                    fault = new GeneralProtection(0);
11146060Sgblack@eecs.umich.edu                } else if (m5reg.cpl != desc.dpl) {
11156060Sgblack@eecs.umich.edu                    fault = new GeneralProtection(0);
11166060Sgblack@eecs.umich.edu                }
11175428Sgblack@eecs.umich.edu                break;
11185428Sgblack@eecs.umich.edu              case SegCallGateCheck:
11195428Sgblack@eecs.umich.edu                panic("CS checks for far calls/jumps through call gates"
11205428Sgblack@eecs.umich.edu                        "not implemented.\\n");
11215428Sgblack@eecs.umich.edu                break;
11225855Sgblack@eecs.umich.edu              case SegSoftIntGateCheck:
11235853Sgblack@eecs.umich.edu                // Check permissions.
11245674Sgblack@eecs.umich.edu                if (desc.dpl < m5reg.cpl) {
11255857Sgblack@eecs.umich.edu                    fault = new GeneralProtection(selector);
11266058Sgblack@eecs.umich.edu                    break;
11275674Sgblack@eecs.umich.edu                }
11285855Sgblack@eecs.umich.edu                // Fall through on purpose
11295855Sgblack@eecs.umich.edu              case SegIntGateCheck:
11305853Sgblack@eecs.umich.edu                // Make sure the gate's the right type.
11315861Snate@binkert.org                if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) ||
11325853Sgblack@eecs.umich.edu                        ((desc.type & 0x6) != 0x6)) {
11335853Sgblack@eecs.umich.edu                    fault = new GeneralProtection(0);
11345853Sgblack@eecs.umich.edu                }
11355674Sgblack@eecs.umich.edu                break;
11365428Sgblack@eecs.umich.edu              case SegSSCheck:
11375433Sgblack@eecs.umich.edu                if (selector.si || selector.ti) {
11385433Sgblack@eecs.umich.edu                    if (!desc.p) {
11395857Sgblack@eecs.umich.edu                        fault = new StackFault(selector);
11405433Sgblack@eecs.umich.edu                    }
11415433Sgblack@eecs.umich.edu                } else {
11425673Sgblack@eecs.umich.edu                    if ((m5reg.submode != SixtyFourBitMode ||
11435673Sgblack@eecs.umich.edu                                m5reg.cpl == 3) ||
11445433Sgblack@eecs.umich.edu                            !(desc.s == 1 &&
11455433Sgblack@eecs.umich.edu                            desc.type.codeOrData == 0 && desc.type.w) ||
11465433Sgblack@eecs.umich.edu                            (desc.dpl != m5reg.cpl) ||
11475433Sgblack@eecs.umich.edu                            (selector.rpl != m5reg.cpl)) {
11485857Sgblack@eecs.umich.edu                        fault = new GeneralProtection(selector);
11495433Sgblack@eecs.umich.edu                    }
11505433Sgblack@eecs.umich.edu                }
11515428Sgblack@eecs.umich.edu                break;
11525428Sgblack@eecs.umich.edu              case SegIretCheck:
11535428Sgblack@eecs.umich.edu                {
11545433Sgblack@eecs.umich.edu                    if ((!selector.si && !selector.ti) ||
11555433Sgblack@eecs.umich.edu                            (selector.rpl < m5reg.cpl) ||
11565433Sgblack@eecs.umich.edu                            !(desc.s == 1 && desc.type.codeOrData == 1) ||
11575433Sgblack@eecs.umich.edu                            (!desc.type.c && desc.dpl != selector.rpl) ||
11585679Sgblack@eecs.umich.edu                            (desc.type.c && desc.dpl > selector.rpl)) {
11595857Sgblack@eecs.umich.edu                        fault = new GeneralProtection(selector);
11605679Sgblack@eecs.umich.edu                    } else if (!desc.p) {
11615857Sgblack@eecs.umich.edu                        fault = new SegmentNotPresent(selector);
11625679Sgblack@eecs.umich.edu                    }
11635428Sgblack@eecs.umich.edu                    break;
11645428Sgblack@eecs.umich.edu                }
11655428Sgblack@eecs.umich.edu              case SegIntCSCheck:
11665675Sgblack@eecs.umich.edu                if (m5reg.mode == LongMode) {
11675675Sgblack@eecs.umich.edu                    if (desc.l != 1 || desc.d != 0) {
11685679Sgblack@eecs.umich.edu                        fault = new GeneralProtection(selector);
11695675Sgblack@eecs.umich.edu                    }
11705675Sgblack@eecs.umich.edu                } else {
11715675Sgblack@eecs.umich.edu                    panic("Interrupt CS checks not implemented "
11725675Sgblack@eecs.umich.edu                            "in legacy mode.\\n");
11735675Sgblack@eecs.umich.edu                }
11745428Sgblack@eecs.umich.edu                break;
11755899Sgblack@eecs.umich.edu              case SegTRCheck:
11765899Sgblack@eecs.umich.edu                if (!selector.si || selector.ti) {
11775899Sgblack@eecs.umich.edu                    fault = new GeneralProtection(selector);
11785899Sgblack@eecs.umich.edu                }
11795899Sgblack@eecs.umich.edu                break;
11805900Sgblack@eecs.umich.edu              case SegTSSCheck:
11815900Sgblack@eecs.umich.edu                if (!desc.p) {
11825900Sgblack@eecs.umich.edu                    fault = new SegmentNotPresent(selector);
11835900Sgblack@eecs.umich.edu                } else if (!(desc.type == 0x9 ||
11845900Sgblack@eecs.umich.edu                        (desc.type == 1 &&
11855900Sgblack@eecs.umich.edu                         m5reg.mode != LongMode))) {
11865935Sgblack@eecs.umich.edu                    fault = new GeneralProtection(selector);
11875900Sgblack@eecs.umich.edu                }
11885900Sgblack@eecs.umich.edu                break;
11895936Sgblack@eecs.umich.edu              case SegInGDTCheck:
11905936Sgblack@eecs.umich.edu                if (selector.ti) {
11915936Sgblack@eecs.umich.edu                    fault = new GeneralProtection(selector);
11925936Sgblack@eecs.umich.edu                }
11935936Sgblack@eecs.umich.edu                break;
11945936Sgblack@eecs.umich.edu              case SegLDTCheck:
11955936Sgblack@eecs.umich.edu                if (!desc.p) {
11965936Sgblack@eecs.umich.edu                    fault = new SegmentNotPresent(selector);
11975936Sgblack@eecs.umich.edu                } else if (desc.type != 0x2) {
11985936Sgblack@eecs.umich.edu                    fault = new GeneralProtection(selector);
11995936Sgblack@eecs.umich.edu                }
12005936Sgblack@eecs.umich.edu                break;
12015428Sgblack@eecs.umich.edu              default:
12025428Sgblack@eecs.umich.edu                panic("Undefined segment check type.\\n");
12035428Sgblack@eecs.umich.edu            }
12045294Sgblack@eecs.umich.edu        '''
12055294Sgblack@eecs.umich.edu        flag_code = '''
12065294Sgblack@eecs.umich.edu            // Check for a NULL selector and set ZF,EZF appropriately.
12075294Sgblack@eecs.umich.edu            ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit));
12085424Sgblack@eecs.umich.edu            if (!selector.si && !selector.ti)
12095294Sgblack@eecs.umich.edu                ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit));
12105294Sgblack@eecs.umich.edu        '''
12115294Sgblack@eecs.umich.edu
12125294Sgblack@eecs.umich.edu    class Wrdh(RegOp):
12135294Sgblack@eecs.umich.edu        code = '''
12145678Sgblack@eecs.umich.edu            SegDescriptor desc = SrcReg1;
12155294Sgblack@eecs.umich.edu
12165678Sgblack@eecs.umich.edu            uint64_t target = bits(SrcReg2, 31, 0) << 32;
12175678Sgblack@eecs.umich.edu            switch(desc.type) {
12185678Sgblack@eecs.umich.edu              case LDT64:
12195678Sgblack@eecs.umich.edu              case AvailableTSS64:
12205678Sgblack@eecs.umich.edu              case BusyTSS64:
12215678Sgblack@eecs.umich.edu                replaceBits(target, 23, 0, desc.baseLow);
12225678Sgblack@eecs.umich.edu                replaceBits(target, 31, 24, desc.baseHigh);
12235678Sgblack@eecs.umich.edu                break;
12245678Sgblack@eecs.umich.edu              case CallGate64:
12255678Sgblack@eecs.umich.edu              case IntGate64:
12265678Sgblack@eecs.umich.edu              case TrapGate64:
12275678Sgblack@eecs.umich.edu                replaceBits(target, 15, 0, bits(desc, 15, 0));
12285678Sgblack@eecs.umich.edu                replaceBits(target, 31, 16, bits(desc, 63, 48));
12295678Sgblack@eecs.umich.edu                break;
12305678Sgblack@eecs.umich.edu              default:
12315678Sgblack@eecs.umich.edu                panic("Wrdh used with wrong descriptor type!\\n");
12325678Sgblack@eecs.umich.edu            }
12335678Sgblack@eecs.umich.edu            DestReg = target;
12345294Sgblack@eecs.umich.edu        '''
12355294Sgblack@eecs.umich.edu
12365409Sgblack@eecs.umich.edu    class Wrtsc(WrRegOp):
12375409Sgblack@eecs.umich.edu        code = '''
12385409Sgblack@eecs.umich.edu            TscOp = psrc1;
12395409Sgblack@eecs.umich.edu        '''
12405409Sgblack@eecs.umich.edu
12415409Sgblack@eecs.umich.edu    class Rdtsc(RdRegOp):
12425409Sgblack@eecs.umich.edu        code = '''
12435409Sgblack@eecs.umich.edu            DestReg = TscOp;
12445409Sgblack@eecs.umich.edu        '''
12455409Sgblack@eecs.umich.edu
12465429Sgblack@eecs.umich.edu    class Rdm5reg(RdRegOp):
12475429Sgblack@eecs.umich.edu        code = '''
12485429Sgblack@eecs.umich.edu            DestReg = M5Reg;
12495429Sgblack@eecs.umich.edu        '''
12505429Sgblack@eecs.umich.edu
12515294Sgblack@eecs.umich.edu    class Wrdl(RegOp):
12525294Sgblack@eecs.umich.edu        code = '''
12535294Sgblack@eecs.umich.edu            SegDescriptor desc = SrcReg1;
12545433Sgblack@eecs.umich.edu            SegSelector selector = SrcReg2;
12555433Sgblack@eecs.umich.edu            if (selector.si || selector.ti) {
12566222Sgblack@eecs.umich.edu                if (!desc.p)
12576222Sgblack@eecs.umich.edu                    panic("Segment not present.\\n");
12585433Sgblack@eecs.umich.edu                SegAttr attr = 0;
12595433Sgblack@eecs.umich.edu                attr.dpl = desc.dpl;
12606222Sgblack@eecs.umich.edu                attr.unusable = 0;
12615433Sgblack@eecs.umich.edu                attr.defaultSize = desc.d;
12626222Sgblack@eecs.umich.edu                attr.longMode = desc.l;
12636222Sgblack@eecs.umich.edu                attr.avl = desc.avl;
12646222Sgblack@eecs.umich.edu                attr.granularity = desc.g;
12656222Sgblack@eecs.umich.edu                attr.present = desc.p;
12666222Sgblack@eecs.umich.edu                attr.system = desc.s;
12676222Sgblack@eecs.umich.edu                attr.type = desc.type;
12685433Sgblack@eecs.umich.edu                if (!desc.s) {
12695901Sgblack@eecs.umich.edu                    // The expand down bit happens to be set for gates.
12705901Sgblack@eecs.umich.edu                    if (desc.type.e) {
12715901Sgblack@eecs.umich.edu                        panic("Gate descriptor encountered.\\n");
12725901Sgblack@eecs.umich.edu                    }
12735901Sgblack@eecs.umich.edu                    attr.readable = 1;
12745901Sgblack@eecs.umich.edu                    attr.writable = 1;
12756222Sgblack@eecs.umich.edu                    attr.expandDown = 0;
12765433Sgblack@eecs.umich.edu                } else {
12775433Sgblack@eecs.umich.edu                    if (desc.type.codeOrData) {
12786222Sgblack@eecs.umich.edu                        attr.expandDown = 0;
12795433Sgblack@eecs.umich.edu                        attr.readable = desc.type.r;
12806222Sgblack@eecs.umich.edu                        attr.writable = 0;
12815433Sgblack@eecs.umich.edu                    } else {
12825433Sgblack@eecs.umich.edu                        attr.expandDown = desc.type.e;
12835433Sgblack@eecs.umich.edu                        attr.readable = 1;
12845433Sgblack@eecs.umich.edu                        attr.writable = desc.type.w;
12855433Sgblack@eecs.umich.edu                    }
12865433Sgblack@eecs.umich.edu                }
12875901Sgblack@eecs.umich.edu                Addr base = desc.baseLow | (desc.baseHigh << 24);
12885901Sgblack@eecs.umich.edu                Addr limit = desc.limitLow | (desc.limitHigh << 16);
12895901Sgblack@eecs.umich.edu                if (desc.g)
12905901Sgblack@eecs.umich.edu                    limit = (limit << 12) | mask(12);
12915901Sgblack@eecs.umich.edu                SegBaseDest = base;
12925901Sgblack@eecs.umich.edu                SegLimitDest = limit;
12935901Sgblack@eecs.umich.edu                SegAttrDest = attr;
12945433Sgblack@eecs.umich.edu            } else {
12955295Sgblack@eecs.umich.edu                SegBaseDest = SegBaseDest;
12965295Sgblack@eecs.umich.edu                SegLimitDest = SegLimitDest;
12975295Sgblack@eecs.umich.edu                SegAttrDest = SegAttrDest;
12985294Sgblack@eecs.umich.edu            }
12995290Sgblack@eecs.umich.edu        '''
13004519Sgblack@eecs.umich.edu}};
1301