regop.isa revision 6430
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 2// All rights reserved. 3// 4// Redistribution and use of this software in source and binary forms, 5// with or without modification, are permitted provided that the 6// following conditions are met: 7// 8// The software must be used only for Non-Commercial Use which means any 9// use which is NOT directed to receiving any direct monetary 10// compensation for, or commercial advantage from such use. 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Neither the name of 30// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 31// contributors may be used to endorse or promote products derived from 32// this software without specific prior written permission. No right of 33// sublicense is granted herewith. Derivatives of the software and 34// output created using the software may be prepared, but only for 35// Non-Commercial Uses. Derivatives of the software may be shared with 36// others provided: (i) the others agree to abide by the list of 37// conditions herein which includes the Non-Commercial Use restrictions; 38// and (ii) such Derivatives of the software include the above copyright 39// notice to acknowledge the contribution from this software where 40// applicable, this list of conditions and the disclaimer below. 41// 42// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 43// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 44// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 45// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 46// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 47// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 48// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53// 54// Authors: Gabe Black 55 56////////////////////////////////////////////////////////////////////////// 57// 58// RegOp Microop templates 59// 60////////////////////////////////////////////////////////////////////////// 61 62def template MicroRegOpExecute {{ 63 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 64 Trace::InstRecord *traceData) const 65 { 66 Fault fault = NoFault; 67 68 DPRINTF(X86, "The data size is %d\n", dataSize); 69 %(op_decl)s; 70 %(op_rd)s; 71 72 if(%(cond_check)s) 73 { 74 %(code)s; 75 %(flag_code)s; 76 } 77 else 78 { 79 %(else_code)s; 80 } 81 82 //Write the resulting state to the execution context 83 if(fault == NoFault) 84 { 85 %(op_wb)s; 86 } 87 return fault; 88 } 89}}; 90 91def template MicroRegOpImmExecute {{ 92 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 93 Trace::InstRecord *traceData) const 94 { 95 Fault fault = NoFault; 96 97 %(op_decl)s; 98 %(op_rd)s; 99 100 if(%(cond_check)s) 101 { 102 %(code)s; 103 %(flag_code)s; 104 } 105 else 106 { 107 %(else_code)s; 108 } 109 110 //Write the resulting state to the execution context 111 if(fault == NoFault) 112 { 113 %(op_wb)s; 114 } 115 return fault; 116 } 117}}; 118 119def template MicroRegOpDeclare {{ 120 class %(class_name)s : public %(base_class)s 121 { 122 protected: 123 void buildMe(); 124 125 public: 126 %(class_name)s(ExtMachInst _machInst, 127 const char * instMnem, 128 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 129 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 130 uint8_t _dataSize, uint16_t _ext); 131 132 %(class_name)s(ExtMachInst _machInst, 133 const char * instMnem, 134 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 135 uint8_t _dataSize, uint16_t _ext); 136 137 %(BasicExecDeclare)s 138 }; 139}}; 140 141def template MicroRegOpImmDeclare {{ 142 143 class %(class_name)s : public %(base_class)s 144 { 145 protected: 146 void buildMe(); 147 148 public: 149 %(class_name)s(ExtMachInst _machInst, 150 const char * instMnem, 151 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 152 InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 153 uint8_t _dataSize, uint16_t _ext); 154 155 %(class_name)s(ExtMachInst _machInst, 156 const char * instMnem, 157 InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 158 uint8_t _dataSize, uint16_t _ext); 159 160 %(BasicExecDeclare)s 161 }; 162}}; 163 164def template MicroRegOpConstructor {{ 165 166 inline void %(class_name)s::buildMe() 167 { 168 %(constructor)s; 169 } 170 171 inline %(class_name)s::%(class_name)s( 172 ExtMachInst machInst, const char * instMnem, 173 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 174 uint8_t _dataSize, uint16_t _ext) : 175 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 176 false, false, false, false, 177 _src1, _src2, _dest, _dataSize, _ext, 178 %(op_class)s) 179 { 180 buildMe(); 181 } 182 183 inline %(class_name)s::%(class_name)s( 184 ExtMachInst machInst, const char * instMnem, 185 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 186 InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 187 uint8_t _dataSize, uint16_t _ext) : 188 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 189 isMicro, isDelayed, isFirst, isLast, 190 _src1, _src2, _dest, _dataSize, _ext, 191 %(op_class)s) 192 { 193 buildMe(); 194 } 195}}; 196 197def template MicroRegOpImmConstructor {{ 198 199 inline void %(class_name)s::buildMe() 200 { 201 %(constructor)s; 202 } 203 204 inline %(class_name)s::%(class_name)s( 205 ExtMachInst machInst, const char * instMnem, 206 InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 207 uint8_t _dataSize, uint16_t _ext) : 208 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 209 false, false, false, false, 210 _src1, _imm8, _dest, _dataSize, _ext, 211 %(op_class)s) 212 { 213 buildMe(); 214 } 215 216 inline %(class_name)s::%(class_name)s( 217 ExtMachInst machInst, const char * instMnem, 218 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 219 InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 220 uint8_t _dataSize, uint16_t _ext) : 221 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 222 isMicro, isDelayed, isFirst, isLast, 223 _src1, _imm8, _dest, _dataSize, _ext, 224 %(op_class)s) 225 { 226 buildMe(); 227 } 228}}; 229 230output header {{ 231 void 232 divide(uint64_t dividend, uint64_t divisor, 233 uint64_t "ient, uint64_t &remainder); 234 235 enum SegmentSelectorCheck { 236 SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck, 237 SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck, 238 SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck 239 }; 240 241 enum LongModeDescriptorType { 242 LDT64 = 2, 243 AvailableTSS64 = 9, 244 BusyTSS64 = 0xb, 245 CallGate64 = 0xc, 246 IntGate64 = 0xe, 247 TrapGate64 = 0xf 248 }; 249}}; 250 251output decoder {{ 252 void 253 divide(uint64_t dividend, uint64_t divisor, 254 uint64_t "ient, uint64_t &remainder) 255 { 256 //Check for divide by zero. 257 if (divisor == 0) 258 panic("Divide by zero!\\n"); 259 //If the divisor is bigger than the dividend, don't do anything. 260 if (divisor <= dividend) { 261 //Shift the divisor so it's msb lines up with the dividend. 262 int dividendMsb = findMsbSet(dividend); 263 int divisorMsb = findMsbSet(divisor); 264 int shift = dividendMsb - divisorMsb; 265 divisor <<= shift; 266 //Compute what we'll add to the quotient if the divisor isn't 267 //now larger than the dividend. 268 uint64_t quotientBit = 1; 269 quotientBit <<= shift; 270 //If we need to step back a bit (no pun intended) because the 271 //divisor got too to large, do that here. This is the "or two" 272 //part of one or two bit division. 273 if (divisor > dividend) { 274 quotientBit >>= 1; 275 divisor >>= 1; 276 } 277 //Decrement the remainder and increment the quotient. 278 quotient += quotientBit; 279 remainder -= divisor; 280 } 281 } 282}}; 283 284let {{ 285 # Make these empty strings so that concatenating onto 286 # them will always work. 287 header_output = "" 288 decoder_output = "" 289 exec_output = "" 290 291 immTemplates = ( 292 MicroRegOpImmDeclare, 293 MicroRegOpImmConstructor, 294 MicroRegOpImmExecute) 295 296 regTemplates = ( 297 MicroRegOpDeclare, 298 MicroRegOpConstructor, 299 MicroRegOpExecute) 300 301 class RegOpMeta(type): 302 def buildCppClasses(self, name, Name, suffix, \ 303 code, flag_code, cond_check, else_code): 304 305 # Globals to stick the output in 306 global header_output 307 global decoder_output 308 global exec_output 309 310 # Stick all the code together so it can be searched at once 311 allCode = "|".join((code, flag_code, cond_check, else_code)) 312 313 # If op2 is used anywhere, make register and immediate versions 314 # of this code. 315 matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?") 316 match = matcher.search(allCode) 317 if match: 318 typeQual = "" 319 if match.group("typeQual"): 320 typeQual = match.group("typeQual") 321 src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 322 self.buildCppClasses(name, Name, suffix, 323 matcher.sub(src2_name, code), 324 matcher.sub(src2_name, flag_code), 325 matcher.sub(src2_name, cond_check), 326 matcher.sub(src2_name, else_code)) 327 self.buildCppClasses(name + "i", Name, suffix + "Imm", 328 matcher.sub("imm8", code), 329 matcher.sub("imm8", flag_code), 330 matcher.sub("imm8", cond_check), 331 matcher.sub("imm8", else_code)) 332 return 333 334 # If there's something optional to do with flags, generate 335 # a version without it and fix up this version to use it. 336 if flag_code != "" or cond_check != "true": 337 self.buildCppClasses(name, Name, suffix, 338 code, "", "true", else_code) 339 suffix = "Flags" + suffix 340 341 # If psrc1 or psrc2 is used, we need to actually insert code to 342 # compute it. 343 matcher = re.compile("(?<!\w)psrc1(?!\w)") 344 if matcher.search(allCode): 345 code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code 346 matcher = re.compile("(?<!\w)psrc2(?!\w)") 347 if matcher.search(allCode): 348 code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code 349 # Also make available versions which do sign extension 350 matcher = re.compile("(?<!\w)spsrc1(?!\w)") 351 if matcher.search(allCode): 352 code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code 353 matcher = re.compile("(?<!\w)spsrc2(?!\w)") 354 if matcher.search(allCode): 355 code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code 356 357 base = "X86ISA::RegOp" 358 359 # If imm8 shows up in the code, use the immediate templates, if 360 # not, hopefully the register ones will be correct. 361 templates = regTemplates 362 matcher = re.compile("(?<!\w)imm8(?!\w)") 363 if matcher.search(allCode): 364 base += "Imm" 365 templates = immTemplates 366 367 # Get everything ready for the substitution 368 iop = InstObjParams(name, Name + suffix, base, 369 {"code" : code, 370 "flag_code" : flag_code, 371 "cond_check" : cond_check, 372 "else_code" : else_code}) 373 374 # Generate the actual code (finally!) 375 header_output += templates[0].subst(iop) 376 decoder_output += templates[1].subst(iop) 377 exec_output += templates[2].subst(iop) 378 379 380 def __new__(mcls, Name, bases, dict): 381 abstract = False 382 name = Name.lower() 383 if "abstract" in dict: 384 abstract = dict['abstract'] 385 del dict['abstract'] 386 387 cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 388 if not abstract: 389 cls.className = Name 390 cls.base_mnemonic = name 391 code = cls.code 392 flag_code = cls.flag_code 393 cond_check = cls.cond_check 394 else_code = cls.else_code 395 396 # Set up the C++ classes 397 mcls.buildCppClasses(cls, name, Name, "", 398 code, flag_code, cond_check, else_code) 399 400 # Hook into the microassembler dict 401 global microopClasses 402 microopClasses[name] = cls 403 404 allCode = "|".join((code, flag_code, cond_check, else_code)) 405 406 # If op2 is used anywhere, make register and immediate versions 407 # of this code. 408 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 409 if matcher.search(allCode): 410 microopClasses[name + 'i'] = cls 411 return cls 412 413 414 class RegOp(X86Microop): 415 __metaclass__ = RegOpMeta 416 # This class itself doesn't act as a microop 417 abstract = True 418 419 # Default template parameter values 420 flag_code = "" 421 cond_check = "true" 422 else_code = ";" 423 424 def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 425 self.dest = dest 426 self.src1 = src1 427 self.op2 = op2 428 self.flags = flags 429 self.dataSize = dataSize 430 if flags is None: 431 self.ext = 0 432 else: 433 if not isinstance(flags, (list, tuple)): 434 raise Exception, "flags must be a list or tuple of flags" 435 self.ext = " | ".join(flags) 436 self.className += "Flags" 437 438 def getAllocator(self, *microFlags): 439 className = self.className 440 if self.mnemonic == self.base_mnemonic + 'i': 441 className += "Imm" 442 allocator = '''new %(class_name)s(machInst, macrocodeBlock 443 %(flags)s, %(src1)s, %(op2)s, %(dest)s, 444 %(dataSize)s, %(ext)s)''' % { 445 "class_name" : className, 446 "flags" : self.microFlagsText(microFlags), 447 "src1" : self.src1, "op2" : self.op2, 448 "dest" : self.dest, 449 "dataSize" : self.dataSize, 450 "ext" : self.ext} 451 return allocator 452 453 class LogicRegOp(RegOp): 454 abstract = True 455 flag_code = ''' 456 //Don't have genFlags handle the OF or CF bits 457 uint64_t mask = CFBit | ECFBit | OFBit; 458 ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); 459 //If a logic microop wants to set these, it wants to set them to 0. 460 ccFlagBits &= ~(CFBit & ext); 461 ccFlagBits &= ~(ECFBit & ext); 462 ccFlagBits &= ~(OFBit & ext); 463 ''' 464 465 class FlagRegOp(RegOp): 466 abstract = True 467 flag_code = \ 468 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" 469 470 class SubRegOp(RegOp): 471 abstract = True 472 flag_code = \ 473 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 474 475 class CondRegOp(RegOp): 476 abstract = True 477 cond_check = "checkCondition(ccFlagBits, ext)" 478 479 class RdRegOp(RegOp): 480 abstract = True 481 def __init__(self, dest, src1=None, dataSize="env.dataSize"): 482 if not src1: 483 src1 = dest 484 super(RdRegOp, self).__init__(dest, src1, \ 485 "InstRegIndex(NUM_INTREGS)", None, dataSize) 486 487 class WrRegOp(RegOp): 488 abstract = True 489 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 490 super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ 491 src1, src2, flags, dataSize) 492 493 class Add(FlagRegOp): 494 code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' 495 496 class Or(LogicRegOp): 497 code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' 498 499 class Adc(FlagRegOp): 500 code = ''' 501 CCFlagBits flags = ccFlagBits; 502 DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize); 503 ''' 504 505 class Sbb(SubRegOp): 506 code = ''' 507 CCFlagBits flags = ccFlagBits; 508 DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize); 509 ''' 510 511 class And(LogicRegOp): 512 code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)' 513 514 class Sub(SubRegOp): 515 code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)' 516 517 class Xor(LogicRegOp): 518 code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)' 519 520 class Mul1s(WrRegOp): 521 code = ''' 522 ProdLow = psrc1 * op2; 523 int halfSize = (dataSize * 8) / 2; 524 uint64_t shifter = (1ULL << halfSize); 525 uint64_t hiResult; 526 uint64_t psrc1_h = psrc1 / shifter; 527 uint64_t psrc1_l = psrc1 & mask(halfSize); 528 uint64_t psrc2_h = op2 / shifter; 529 uint64_t psrc2_l = op2 & mask(halfSize); 530 hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 531 ((psrc1_l * psrc2_l) / shifter)) /shifter) + 532 psrc1_h * psrc2_h; 533 if (spsrc1 < 0) 534 hiResult -= op2; 535 int64_t bigSop2 = sop2; 536 if (bigSop2 < 0) 537 hiResult -= psrc1; 538 ProdHi = hiResult; 539 ''' 540 541 class Mul1u(WrRegOp): 542 code = ''' 543 ProdLow = psrc1 * op2; 544 int halfSize = (dataSize * 8) / 2; 545 uint64_t shifter = (1ULL << halfSize); 546 uint64_t psrc1_h = psrc1 / shifter; 547 uint64_t psrc1_l = psrc1 & mask(halfSize); 548 uint64_t psrc2_h = op2 / shifter; 549 uint64_t psrc2_l = op2 & mask(halfSize); 550 ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 551 ((psrc1_l * psrc2_l) / shifter)) / shifter) + 552 psrc1_h * psrc2_h; 553 ''' 554 555 class Mulel(RdRegOp): 556 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 557 558 class Muleh(RdRegOp): 559 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 560 if not src1: 561 src1 = dest 562 super(RdRegOp, self).__init__(dest, src1, \ 563 "InstRegIndex(NUM_INTREGS)", flags, dataSize) 564 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 565 flag_code = ''' 566 if (ProdHi) 567 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 568 else 569 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 570 ''' 571 572 # One or two bit divide 573 class Div1(WrRegOp): 574 code = ''' 575 //These are temporaries so that modifying them later won't make 576 //the ISA parser think they're also sources. 577 uint64_t quotient = 0; 578 uint64_t remainder = psrc1; 579 //Similarly, this is a temporary so changing it doesn't make it 580 //a source. 581 uint64_t divisor = op2; 582 //This is a temporary just for consistency and clarity. 583 uint64_t dividend = remainder; 584 //Do the division. 585 divide(dividend, divisor, quotient, remainder); 586 //Record the final results. 587 Remainder = remainder; 588 Quotient = quotient; 589 Divisor = divisor; 590 ''' 591 592 # Step divide 593 class Div2(RegOp): 594 code = ''' 595 uint64_t dividend = Remainder; 596 uint64_t divisor = Divisor; 597 uint64_t quotient = Quotient; 598 uint64_t remainder = dividend; 599 int remaining = op2; 600 //If we overshot, do nothing. This lets us unrool division loops a 601 //little. 602 if (remaining) { 603 //Shift in bits from the low order portion of the dividend 604 while(dividend < divisor && remaining) { 605 dividend = (dividend << 1) | bits(SrcReg1, remaining - 1); 606 quotient <<= 1; 607 remaining--; 608 } 609 remainder = dividend; 610 //Do the division. 611 divide(dividend, divisor, quotient, remainder); 612 } 613 //Keep track of how many bits there are still to pull in. 614 DestReg = merge(DestReg, remaining, dataSize); 615 //Record the final results 616 Remainder = remainder; 617 Quotient = quotient; 618 ''' 619 flag_code = ''' 620 if (DestReg == 0) 621 ccFlagBits = ccFlagBits | (ext & EZFBit); 622 else 623 ccFlagBits = ccFlagBits & ~(ext & EZFBit); 624 ''' 625 626 class Divq(RdRegOp): 627 code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 628 629 class Divr(RdRegOp): 630 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 631 632 class Mov(CondRegOp): 633 code = 'DestReg = merge(SrcReg1, op2, dataSize)' 634 else_code = 'DestReg=DestReg;' 635 636 # Shift instructions 637 638 class Sll(RegOp): 639 code = ''' 640 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 641 DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 642 ''' 643 flag_code = ''' 644 // If the shift amount is zero, no flags should be modified. 645 if (shiftAmt) { 646 //Zero out any flags we might modify. This way we only have to 647 //worry about setting them. 648 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 649 int CFBits = 0; 650 //Figure out if we -would- set the CF bits if requested. 651 if (bits(SrcReg1, dataSize * 8 - shiftAmt)) 652 CFBits = 1; 653 //If some combination of the CF bits need to be set, set them. 654 if ((ext & (CFBit | ECFBit)) && CFBits) 655 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 656 //Figure out what the OF bit should be. 657 if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) 658 ccFlagBits = ccFlagBits | OFBit; 659 //Use the regular mechanisms to calculate the other flags. 660 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 661 DestReg, psrc1, op2); 662 } 663 ''' 664 665 class Srl(RegOp): 666 code = ''' 667 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 668 // Because what happens to the bits shift -in- on a right shift 669 // is not defined in the C/C++ standard, we have to mask them out 670 // to be sure they're zero. 671 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 672 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 673 ''' 674 flag_code = ''' 675 // If the shift amount is zero, no flags should be modified. 676 if (shiftAmt) { 677 //Zero out any flags we might modify. This way we only have to 678 //worry about setting them. 679 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 680 //If some combination of the CF bits need to be set, set them. 681 if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1)) 682 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 683 //Figure out what the OF bit should be. 684 if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) 685 ccFlagBits = ccFlagBits | OFBit; 686 //Use the regular mechanisms to calculate the other flags. 687 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 688 DestReg, psrc1, op2); 689 } 690 ''' 691 692 class Sra(RegOp): 693 code = ''' 694 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 695 // Because what happens to the bits shift -in- on a right shift 696 // is not defined in the C/C++ standard, we have to sign extend 697 // them manually to be sure. 698 uint64_t arithMask = 699 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 700 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 701 ''' 702 flag_code = ''' 703 // If the shift amount is zero, no flags should be modified. 704 if (shiftAmt) { 705 //Zero out any flags we might modify. This way we only have to 706 //worry about setting them. 707 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 708 //If some combination of the CF bits need to be set, set them. 709 if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1)) 710 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 711 //Use the regular mechanisms to calculate the other flags. 712 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 713 DestReg, psrc1, op2); 714 } 715 ''' 716 717 class Ror(RegOp): 718 code = ''' 719 uint8_t shiftAmt = 720 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 721 if(shiftAmt) 722 { 723 uint64_t top = psrc1 << (dataSize * 8 - shiftAmt); 724 uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); 725 DestReg = merge(DestReg, top | bottom, dataSize); 726 } 727 else 728 DestReg = DestReg; 729 ''' 730 flag_code = ''' 731 // If the shift amount is zero, no flags should be modified. 732 if (shiftAmt) { 733 //Zero out any flags we might modify. This way we only have to 734 //worry about setting them. 735 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 736 //Find the most and second most significant bits of the result. 737 int msb = bits(DestReg, dataSize * 8 - 1); 738 int smsb = bits(DestReg, dataSize * 8 - 2); 739 //If some combination of the CF bits need to be set, set them. 740 if ((ext & (CFBit | ECFBit)) && msb) 741 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 742 //Figure out what the OF bit should be. 743 if ((ext & OFBit) && (msb ^ smsb)) 744 ccFlagBits = ccFlagBits | OFBit; 745 //Use the regular mechanisms to calculate the other flags. 746 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 747 DestReg, psrc1, op2); 748 } 749 ''' 750 751 class Rcr(RegOp): 752 code = ''' 753 uint8_t shiftAmt = 754 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 755 if(shiftAmt) 756 { 757 CCFlagBits flags = ccFlagBits; 758 uint64_t top = flags.cf << (dataSize * 8 - shiftAmt); 759 if(shiftAmt > 1) 760 top |= psrc1 << (dataSize * 8 - shiftAmt - 1); 761 uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); 762 DestReg = merge(DestReg, top | bottom, dataSize); 763 } 764 else 765 DestReg = DestReg; 766 ''' 767 flag_code = ''' 768 // If the shift amount is zero, no flags should be modified. 769 if (shiftAmt) { 770 //Zero out any flags we might modify. This way we only have to 771 //worry about setting them. 772 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 773 //Figure out what the OF bit should be. 774 if ((ext & OFBit) && ((ccFlagBits & CFBit) ^ 775 bits(SrcReg1, dataSize * 8 - 1))) 776 ccFlagBits = ccFlagBits | OFBit; 777 //If some combination of the CF bits need to be set, set them. 778 if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, shiftAmt - 1)) 779 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 780 //Use the regular mechanisms to calculate the other flags. 781 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 782 DestReg, psrc1, op2); 783 } 784 ''' 785 786 class Rol(RegOp): 787 code = ''' 788 uint8_t shiftAmt = 789 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 790 if(shiftAmt) 791 { 792 uint64_t top = psrc1 << shiftAmt; 793 uint64_t bottom = 794 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - shiftAmt); 795 DestReg = merge(DestReg, top | bottom, dataSize); 796 } 797 else 798 DestReg = DestReg; 799 ''' 800 flag_code = ''' 801 // If the shift amount is zero, no flags should be modified. 802 if (shiftAmt) { 803 //Zero out any flags we might modify. This way we only have to 804 //worry about setting them. 805 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 806 //The CF bits, if set, would be set to the lsb of the result. 807 int lsb = DestReg & 0x1; 808 int msb = bits(DestReg, dataSize * 8 - 1); 809 //If some combination of the CF bits need to be set, set them. 810 if ((ext & (CFBit | ECFBit)) && lsb) 811 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 812 //Figure out what the OF bit should be. 813 if ((ext & OFBit) && (msb ^ lsb)) 814 ccFlagBits = ccFlagBits | OFBit; 815 //Use the regular mechanisms to calculate the other flags. 816 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 817 DestReg, psrc1, op2); 818 } 819 ''' 820 821 class Rcl(RegOp): 822 code = ''' 823 uint8_t shiftAmt = 824 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 825 if(shiftAmt) 826 { 827 CCFlagBits flags = ccFlagBits; 828 uint64_t top = psrc1 << shiftAmt; 829 uint64_t bottom = flags.cf << (shiftAmt - 1); 830 if(shiftAmt > 1) 831 bottom |= 832 bits(psrc1, dataSize * 8 - 1, 833 dataSize * 8 - shiftAmt + 1); 834 DestReg = merge(DestReg, top | bottom, dataSize); 835 } 836 else 837 DestReg = DestReg; 838 ''' 839 flag_code = ''' 840 // If the shift amount is zero, no flags should be modified. 841 if (shiftAmt) { 842 //Zero out any flags we might modify. This way we only have to 843 //worry about setting them. 844 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 845 int msb = bits(DestReg, dataSize * 8 - 1); 846 int CFBits = bits(SrcReg1, dataSize * 8 - shiftAmt); 847 //If some combination of the CF bits need to be set, set them. 848 if ((ext & (CFBit | ECFBit)) && CFBits) 849 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 850 //Figure out what the OF bit should be. 851 if ((ext & OFBit) && (msb ^ CFBits)) 852 ccFlagBits = ccFlagBits | OFBit; 853 //Use the regular mechanisms to calculate the other flags. 854 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 855 DestReg, psrc1, op2); 856 } 857 ''' 858 859 class Wrip(WrRegOp, CondRegOp): 860 code = 'RIP = psrc1 + sop2 + CSBase' 861 else_code="RIP = RIP;" 862 863 class Wruflags(WrRegOp): 864 code = 'ccFlagBits = psrc1 ^ op2' 865 866 class Wrflags(WrRegOp): 867 code = ''' 868 MiscReg newFlags = psrc1 ^ op2; 869 MiscReg userFlagMask = 0xDD5; 870 // Get only the user flags 871 ccFlagBits = newFlags & userFlagMask; 872 // Get everything else 873 nccFlagBits = newFlags & ~userFlagMask; 874 ''' 875 876 class Rdip(RdRegOp): 877 code = 'DestReg = RIP - CSBase' 878 879 class Ruflags(RdRegOp): 880 code = 'DestReg = ccFlagBits' 881 882 class Rflags(RdRegOp): 883 code = 'DestReg = ccFlagBits | nccFlagBits' 884 885 class Ruflag(RegOp): 886 code = ''' 887 int flag = bits(ccFlagBits, imm8); 888 DestReg = merge(DestReg, flag, dataSize); 889 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 890 (ccFlagBits & ~EZFBit); 891 ''' 892 def __init__(self, dest, imm, flags=None, \ 893 dataSize="env.dataSize"): 894 super(Ruflag, self).__init__(dest, \ 895 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 896 897 class Rflag(RegOp): 898 code = ''' 899 MiscReg flagMask = 0x3F7FDD5; 900 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 901 int flag = bits(flags, imm8); 902 DestReg = merge(DestReg, flag, dataSize); 903 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 904 (ccFlagBits & ~EZFBit); 905 ''' 906 def __init__(self, dest, imm, flags=None, \ 907 dataSize="env.dataSize"): 908 super(Rflag, self).__init__(dest, \ 909 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 910 911 class Sext(RegOp): 912 code = ''' 913 IntReg val = psrc1; 914 // Mask the bit position so that it wraps. 915 int bitPos = op2 & (dataSize * 8 - 1); 916 int sign_bit = bits(val, bitPos, bitPos); 917 uint64_t maskVal = mask(bitPos+1); 918 val = sign_bit ? (val | ~maskVal) : (val & maskVal); 919 DestReg = merge(DestReg, val, dataSize); 920 ''' 921 flag_code = ''' 922 if (!sign_bit) 923 ccFlagBits = ccFlagBits & 924 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit)); 925 else 926 ccFlagBits = ccFlagBits | 927 (ext & (CFBit | ECFBit | ZFBit | EZFBit)); 928 ''' 929 930 class Zext(RegOp): 931 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' 932 933 class Rddr(RegOp): 934 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 935 super(Rddr, self).__init__(dest, \ 936 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 937 code = ''' 938 CR4 cr4 = CR4Op; 939 DR7 dr7 = DR7Op; 940 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 941 fault = new InvalidOpcode(); 942 } else if (dr7.gd) { 943 fault = new DebugException(); 944 } else { 945 DestReg = merge(DestReg, DebugSrc1, dataSize); 946 } 947 ''' 948 949 class Wrdr(RegOp): 950 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 951 super(Wrdr, self).__init__(dest, \ 952 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 953 code = ''' 954 CR4 cr4 = CR4Op; 955 DR7 dr7 = DR7Op; 956 if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { 957 fault = new InvalidOpcode(); 958 } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) && 959 machInst.mode.mode == LongMode) { 960 fault = new GeneralProtection(0); 961 } else if (dr7.gd) { 962 fault = new DebugException(); 963 } else { 964 DebugDest = psrc1; 965 } 966 ''' 967 968 class Rdcr(RegOp): 969 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 970 super(Rdcr, self).__init__(dest, \ 971 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 972 code = ''' 973 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 974 fault = new InvalidOpcode(); 975 } else { 976 DestReg = merge(DestReg, ControlSrc1, dataSize); 977 } 978 ''' 979 980 class Wrcr(RegOp): 981 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 982 super(Wrcr, self).__init__(dest, \ 983 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 984 code = ''' 985 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 986 fault = new InvalidOpcode(); 987 } else { 988 // There are *s in the line below so it doesn't confuse the 989 // parser. They may be unnecessary. 990 //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 991 MiscReg newVal = psrc1; 992 993 // Check for any modifications that would cause a fault. 994 switch(dest) { 995 case 0: 996 { 997 Efer efer = EferOp; 998 CR0 cr0 = newVal; 999 CR4 oldCr4 = CR4Op; 1000 if (bits(newVal, 63, 32) || 1001 (!cr0.pe && cr0.pg) || 1002 (!cr0.cd && cr0.nw) || 1003 (cr0.pg && efer.lme && !oldCr4.pae)) 1004 fault = new GeneralProtection(0); 1005 } 1006 break; 1007 case 2: 1008 break; 1009 case 3: 1010 break; 1011 case 4: 1012 { 1013 CR4 cr4 = newVal; 1014 // PAE can't be disabled in long mode. 1015 if (bits(newVal, 63, 11) || 1016 (machInst.mode.mode == LongMode && !cr4.pae)) 1017 fault = new GeneralProtection(0); 1018 } 1019 break; 1020 case 8: 1021 { 1022 if (bits(newVal, 63, 4)) 1023 fault = new GeneralProtection(0); 1024 } 1025 default: 1026 panic("Unrecognized control register %d.\\n", dest); 1027 } 1028 ControlDest = newVal; 1029 } 1030 ''' 1031 1032 # Microops for manipulating segmentation registers 1033 class SegOp(CondRegOp): 1034 abstract = True 1035 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1036 super(SegOp, self).__init__(dest, \ 1037 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1038 1039 class Wrbase(SegOp): 1040 code = ''' 1041 SegBaseDest = psrc1; 1042 ''' 1043 1044 class Wrlimit(SegOp): 1045 code = ''' 1046 SegLimitDest = psrc1; 1047 ''' 1048 1049 class Wrsel(SegOp): 1050 code = ''' 1051 SegSelDest = psrc1; 1052 ''' 1053 1054 class WrAttr(SegOp): 1055 code = ''' 1056 SegAttrDest = psrc1; 1057 ''' 1058 1059 class Rdbase(SegOp): 1060 code = ''' 1061 DestReg = merge(DestReg, SegBaseSrc1, dataSize); 1062 ''' 1063 1064 class Rdlimit(SegOp): 1065 code = ''' 1066 DestReg = merge(DestReg, SegLimitSrc1, dataSize); 1067 ''' 1068 1069 class RdAttr(SegOp): 1070 code = ''' 1071 DestReg = merge(DestReg, SegAttrSrc1, dataSize); 1072 ''' 1073 1074 class Rdsel(SegOp): 1075 code = ''' 1076 DestReg = merge(DestReg, SegSelSrc1, dataSize); 1077 ''' 1078 1079 class Rdval(RegOp): 1080 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1081 super(Rdval, self).__init__(dest, src1, \ 1082 "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1083 code = ''' 1084 DestReg = MiscRegSrc1; 1085 ''' 1086 1087 class Wrval(RegOp): 1088 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1089 super(Wrval, self).__init__(dest, src1, \ 1090 "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1091 code = ''' 1092 MiscRegDest = SrcReg1; 1093 ''' 1094 1095 class Chks(RegOp): 1096 def __init__(self, dest, src1, src2=0, 1097 flags=None, dataSize="env.dataSize"): 1098 super(Chks, self).__init__(dest, 1099 src1, src2, flags, dataSize) 1100 code = ''' 1101 // The selector is in source 1 and can be at most 16 bits. 1102 SegSelector selector = DestReg; 1103 SegDescriptor desc = SrcReg1; 1104 HandyM5Reg m5reg = M5Reg; 1105 1106 switch (imm8) 1107 { 1108 case SegNoCheck: 1109 break; 1110 case SegCSCheck: 1111 // Make sure it's the right type 1112 if (desc.s == 0 || desc.type.codeOrData != 1) { 1113 fault = new GeneralProtection(0); 1114 } else if (m5reg.cpl != desc.dpl) { 1115 fault = new GeneralProtection(0); 1116 } 1117 break; 1118 case SegCallGateCheck: 1119 panic("CS checks for far calls/jumps through call gates" 1120 "not implemented.\\n"); 1121 break; 1122 case SegSoftIntGateCheck: 1123 // Check permissions. 1124 if (desc.dpl < m5reg.cpl) { 1125 fault = new GeneralProtection(selector); 1126 break; 1127 } 1128 // Fall through on purpose 1129 case SegIntGateCheck: 1130 // Make sure the gate's the right type. 1131 if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) || 1132 ((desc.type & 0x6) != 0x6)) { 1133 fault = new GeneralProtection(0); 1134 } 1135 break; 1136 case SegSSCheck: 1137 if (selector.si || selector.ti) { 1138 if (!desc.p) { 1139 fault = new StackFault(selector); 1140 } 1141 } else { 1142 if ((m5reg.submode != SixtyFourBitMode || 1143 m5reg.cpl == 3) || 1144 !(desc.s == 1 && 1145 desc.type.codeOrData == 0 && desc.type.w) || 1146 (desc.dpl != m5reg.cpl) || 1147 (selector.rpl != m5reg.cpl)) { 1148 fault = new GeneralProtection(selector); 1149 } 1150 } 1151 break; 1152 case SegIretCheck: 1153 { 1154 if ((!selector.si && !selector.ti) || 1155 (selector.rpl < m5reg.cpl) || 1156 !(desc.s == 1 && desc.type.codeOrData == 1) || 1157 (!desc.type.c && desc.dpl != selector.rpl) || 1158 (desc.type.c && desc.dpl > selector.rpl)) { 1159 fault = new GeneralProtection(selector); 1160 } else if (!desc.p) { 1161 fault = new SegmentNotPresent(selector); 1162 } 1163 break; 1164 } 1165 case SegIntCSCheck: 1166 if (m5reg.mode == LongMode) { 1167 if (desc.l != 1 || desc.d != 0) { 1168 fault = new GeneralProtection(selector); 1169 } 1170 } else { 1171 panic("Interrupt CS checks not implemented " 1172 "in legacy mode.\\n"); 1173 } 1174 break; 1175 case SegTRCheck: 1176 if (!selector.si || selector.ti) { 1177 fault = new GeneralProtection(selector); 1178 } 1179 break; 1180 case SegTSSCheck: 1181 if (!desc.p) { 1182 fault = new SegmentNotPresent(selector); 1183 } else if (!(desc.type == 0x9 || 1184 (desc.type == 1 && 1185 m5reg.mode != LongMode))) { 1186 fault = new GeneralProtection(selector); 1187 } 1188 break; 1189 case SegInGDTCheck: 1190 if (selector.ti) { 1191 fault = new GeneralProtection(selector); 1192 } 1193 break; 1194 case SegLDTCheck: 1195 if (!desc.p) { 1196 fault = new SegmentNotPresent(selector); 1197 } else if (desc.type != 0x2) { 1198 fault = new GeneralProtection(selector); 1199 } 1200 break; 1201 default: 1202 panic("Undefined segment check type.\\n"); 1203 } 1204 ''' 1205 flag_code = ''' 1206 // Check for a NULL selector and set ZF,EZF appropriately. 1207 ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit)); 1208 if (!selector.si && !selector.ti) 1209 ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit)); 1210 ''' 1211 1212 class Wrdh(RegOp): 1213 code = ''' 1214 SegDescriptor desc = SrcReg1; 1215 1216 uint64_t target = bits(SrcReg2, 31, 0) << 32; 1217 switch(desc.type) { 1218 case LDT64: 1219 case AvailableTSS64: 1220 case BusyTSS64: 1221 replaceBits(target, 23, 0, desc.baseLow); 1222 replaceBits(target, 31, 24, desc.baseHigh); 1223 break; 1224 case CallGate64: 1225 case IntGate64: 1226 case TrapGate64: 1227 replaceBits(target, 15, 0, bits(desc, 15, 0)); 1228 replaceBits(target, 31, 16, bits(desc, 63, 48)); 1229 break; 1230 default: 1231 panic("Wrdh used with wrong descriptor type!\\n"); 1232 } 1233 DestReg = target; 1234 ''' 1235 1236 class Wrtsc(WrRegOp): 1237 code = ''' 1238 TscOp = psrc1; 1239 ''' 1240 1241 class Rdtsc(RdRegOp): 1242 code = ''' 1243 DestReg = TscOp; 1244 ''' 1245 1246 class Rdm5reg(RdRegOp): 1247 code = ''' 1248 DestReg = M5Reg; 1249 ''' 1250 1251 class Wrdl(RegOp): 1252 code = ''' 1253 SegDescriptor desc = SrcReg1; 1254 SegSelector selector = SrcReg2; 1255 if (selector.si || selector.ti) { 1256 if (!desc.p) 1257 panic("Segment not present.\\n"); 1258 SegAttr attr = 0; 1259 attr.dpl = desc.dpl; 1260 attr.unusable = 0; 1261 attr.defaultSize = desc.d; 1262 attr.longMode = desc.l; 1263 attr.avl = desc.avl; 1264 attr.granularity = desc.g; 1265 attr.present = desc.p; 1266 attr.system = desc.s; 1267 attr.type = desc.type; 1268 if (!desc.s) { 1269 // The expand down bit happens to be set for gates. 1270 if (desc.type.e) { 1271 panic("Gate descriptor encountered.\\n"); 1272 } 1273 attr.readable = 1; 1274 attr.writable = 1; 1275 attr.expandDown = 0; 1276 } else { 1277 if (desc.type.codeOrData) { 1278 attr.expandDown = 0; 1279 attr.readable = desc.type.r; 1280 attr.writable = 0; 1281 } else { 1282 attr.expandDown = desc.type.e; 1283 attr.readable = 1; 1284 attr.writable = desc.type.w; 1285 } 1286 } 1287 Addr base = desc.baseLow | (desc.baseHigh << 24); 1288 Addr limit = desc.limitLow | (desc.limitHigh << 16); 1289 if (desc.g) 1290 limit = (limit << 12) | mask(12); 1291 SegBaseDest = base; 1292 SegLimitDest = limit; 1293 SegAttrDest = attr; 1294 } else { 1295 SegBaseDest = SegBaseDest; 1296 SegLimitDest = SegLimitDest; 1297 SegAttrDest = SegAttrDest; 1298 } 1299 ''' 1300}}; 1301