regop.isa revision 4868
14519Sgblack@eecs.umich.edu// Copyright (c) 2007 The Hewlett-Packard Development Company 24519Sgblack@eecs.umich.edu// All rights reserved. 34519Sgblack@eecs.umich.edu// 44519Sgblack@eecs.umich.edu// Redistribution and use of this software in source and binary forms, 54519Sgblack@eecs.umich.edu// with or without modification, are permitted provided that the 64519Sgblack@eecs.umich.edu// following conditions are met: 74519Sgblack@eecs.umich.edu// 84519Sgblack@eecs.umich.edu// The software must be used only for Non-Commercial Use which means any 94519Sgblack@eecs.umich.edu// use which is NOT directed to receiving any direct monetary 104519Sgblack@eecs.umich.edu// compensation for, or commercial advantage from such use. Illustrative 114519Sgblack@eecs.umich.edu// examples of non-commercial use are academic research, personal study, 124519Sgblack@eecs.umich.edu// teaching, education and corporate research & development. 134519Sgblack@eecs.umich.edu// Illustrative examples of commercial use are distributing products for 144519Sgblack@eecs.umich.edu// commercial advantage and providing services using the software for 154519Sgblack@eecs.umich.edu// commercial advantage. 164519Sgblack@eecs.umich.edu// 174519Sgblack@eecs.umich.edu// If you wish to use this software or functionality therein that may be 184519Sgblack@eecs.umich.edu// covered by patents for commercial use, please contact: 194519Sgblack@eecs.umich.edu// Director of Intellectual Property Licensing 204519Sgblack@eecs.umich.edu// Office of Strategy and Technology 214519Sgblack@eecs.umich.edu// Hewlett-Packard Company 224519Sgblack@eecs.umich.edu// 1501 Page Mill Road 234519Sgblack@eecs.umich.edu// Palo Alto, California 94304 244519Sgblack@eecs.umich.edu// 254519Sgblack@eecs.umich.edu// Redistributions of source code must retain the above copyright notice, 264519Sgblack@eecs.umich.edu// this list of conditions and the following disclaimer. Redistributions 274519Sgblack@eecs.umich.edu// in binary form must reproduce the above copyright notice, this list of 284519Sgblack@eecs.umich.edu// conditions and the following disclaimer in the documentation and/or 294519Sgblack@eecs.umich.edu// other materials provided with the distribution. Neither the name of 304519Sgblack@eecs.umich.edu// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 314519Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 324519Sgblack@eecs.umich.edu// this software without specific prior written permission. No right of 334519Sgblack@eecs.umich.edu// sublicense is granted herewith. Derivatives of the software and 344519Sgblack@eecs.umich.edu// output created using the software may be prepared, but only for 354519Sgblack@eecs.umich.edu// Non-Commercial Uses. Derivatives of the software may be shared with 364519Sgblack@eecs.umich.edu// others provided: (i) the others agree to abide by the list of 374519Sgblack@eecs.umich.edu// conditions herein which includes the Non-Commercial Use restrictions; 384519Sgblack@eecs.umich.edu// and (ii) such Derivatives of the software include the above copyright 394519Sgblack@eecs.umich.edu// notice to acknowledge the contribution from this software where 404519Sgblack@eecs.umich.edu// applicable, this list of conditions and the disclaimer below. 414519Sgblack@eecs.umich.edu// 424519Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 434519Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 444519Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 454519Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 464519Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 474519Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 484519Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 494519Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 504519Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 514519Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 524519Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 534519Sgblack@eecs.umich.edu// 544519Sgblack@eecs.umich.edu// Authors: Gabe Black 554519Sgblack@eecs.umich.edu 564519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 574519Sgblack@eecs.umich.edu// 584519Sgblack@eecs.umich.edu// RegOp Microop templates 594519Sgblack@eecs.umich.edu// 604519Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 614519Sgblack@eecs.umich.edu 624519Sgblack@eecs.umich.edudef template MicroRegOpExecute {{ 634519Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 644519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 654519Sgblack@eecs.umich.edu { 664519Sgblack@eecs.umich.edu Fault fault = NoFault; 674519Sgblack@eecs.umich.edu 684809Sgblack@eecs.umich.edu DPRINTF(X86, "The data size is %d\n", dataSize); 694519Sgblack@eecs.umich.edu %(op_decl)s; 704519Sgblack@eecs.umich.edu %(op_rd)s; 714688Sgblack@eecs.umich.edu 724688Sgblack@eecs.umich.edu if(%(cond_check)s) 734688Sgblack@eecs.umich.edu { 744688Sgblack@eecs.umich.edu %(code)s; 754688Sgblack@eecs.umich.edu %(flag_code)s; 764688Sgblack@eecs.umich.edu } 774708Sgblack@eecs.umich.edu else 784708Sgblack@eecs.umich.edu { 794708Sgblack@eecs.umich.edu %(else_code)s; 804708Sgblack@eecs.umich.edu } 814519Sgblack@eecs.umich.edu 824519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 834519Sgblack@eecs.umich.edu if(fault == NoFault) 844519Sgblack@eecs.umich.edu { 854519Sgblack@eecs.umich.edu %(op_wb)s; 864519Sgblack@eecs.umich.edu } 874519Sgblack@eecs.umich.edu return fault; 884519Sgblack@eecs.umich.edu } 894519Sgblack@eecs.umich.edu}}; 904519Sgblack@eecs.umich.edu 914519Sgblack@eecs.umich.edudef template MicroRegOpImmExecute {{ 924519Sgblack@eecs.umich.edu Fault %(class_name)sImm::execute(%(CPU_exec_context)s *xc, 934519Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 944519Sgblack@eecs.umich.edu { 954519Sgblack@eecs.umich.edu Fault fault = NoFault; 964519Sgblack@eecs.umich.edu 974519Sgblack@eecs.umich.edu %(op_decl)s; 984519Sgblack@eecs.umich.edu %(op_rd)s; 994688Sgblack@eecs.umich.edu 1004688Sgblack@eecs.umich.edu if(%(cond_check)s) 1014688Sgblack@eecs.umich.edu { 1024688Sgblack@eecs.umich.edu %(code)s; 1034688Sgblack@eecs.umich.edu %(flag_code)s; 1044688Sgblack@eecs.umich.edu } 1054708Sgblack@eecs.umich.edu else 1064708Sgblack@eecs.umich.edu { 1074708Sgblack@eecs.umich.edu %(else_code)s; 1084708Sgblack@eecs.umich.edu } 1094519Sgblack@eecs.umich.edu 1104519Sgblack@eecs.umich.edu //Write the resulting state to the execution context 1114519Sgblack@eecs.umich.edu if(fault == NoFault) 1124519Sgblack@eecs.umich.edu { 1134519Sgblack@eecs.umich.edu %(op_wb)s; 1144519Sgblack@eecs.umich.edu } 1154519Sgblack@eecs.umich.edu return fault; 1164519Sgblack@eecs.umich.edu } 1174519Sgblack@eecs.umich.edu}}; 1184519Sgblack@eecs.umich.edu 1194519Sgblack@eecs.umich.edudef template MicroRegOpDeclare {{ 1204519Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 1214519Sgblack@eecs.umich.edu { 1224519Sgblack@eecs.umich.edu protected: 1234519Sgblack@eecs.umich.edu void buildMe(); 1244519Sgblack@eecs.umich.edu 1254519Sgblack@eecs.umich.edu public: 1264519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1274519Sgblack@eecs.umich.edu const char * instMnem, 1284519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1294519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1304712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1314519Sgblack@eecs.umich.edu 1324519Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 1334519Sgblack@eecs.umich.edu const char * instMnem, 1344519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1354712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1364519Sgblack@eecs.umich.edu 1374519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1384519Sgblack@eecs.umich.edu }; 1394519Sgblack@eecs.umich.edu}}; 1404519Sgblack@eecs.umich.edu 1414519Sgblack@eecs.umich.edudef template MicroRegOpImmDeclare {{ 1424519Sgblack@eecs.umich.edu 1434519Sgblack@eecs.umich.edu class %(class_name)sImm : public %(base_class)s 1444519Sgblack@eecs.umich.edu { 1454519Sgblack@eecs.umich.edu protected: 1464519Sgblack@eecs.umich.edu void buildMe(); 1474519Sgblack@eecs.umich.edu 1484519Sgblack@eecs.umich.edu public: 1494519Sgblack@eecs.umich.edu %(class_name)sImm(ExtMachInst _machInst, 1504519Sgblack@eecs.umich.edu const char * instMnem, 1514519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1524519Sgblack@eecs.umich.edu RegIndex _src1, uint8_t _imm8, RegIndex _dest, 1534712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1544519Sgblack@eecs.umich.edu 1554519Sgblack@eecs.umich.edu %(class_name)sImm(ExtMachInst _machInst, 1564519Sgblack@eecs.umich.edu const char * instMnem, 1574519Sgblack@eecs.umich.edu RegIndex _src1, uint8_t _imm8, RegIndex _dest, 1584712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext); 1594519Sgblack@eecs.umich.edu 1604519Sgblack@eecs.umich.edu %(BasicExecDeclare)s 1614519Sgblack@eecs.umich.edu }; 1624519Sgblack@eecs.umich.edu}}; 1634519Sgblack@eecs.umich.edu 1644519Sgblack@eecs.umich.edudef template MicroRegOpConstructor {{ 1654519Sgblack@eecs.umich.edu 1664519Sgblack@eecs.umich.edu inline void %(class_name)s::buildMe() 1674519Sgblack@eecs.umich.edu { 1684519Sgblack@eecs.umich.edu %(constructor)s; 1694519Sgblack@eecs.umich.edu } 1704519Sgblack@eecs.umich.edu 1714519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1724519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1734519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1744712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1754519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1764581Sgblack@eecs.umich.edu false, false, false, false, 1774688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1784581Sgblack@eecs.umich.edu %(op_class)s) 1794519Sgblack@eecs.umich.edu { 1804519Sgblack@eecs.umich.edu buildMe(); 1814519Sgblack@eecs.umich.edu } 1824519Sgblack@eecs.umich.edu 1834519Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 1844519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 1854519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1864519Sgblack@eecs.umich.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 1874712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 1884519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1894581Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 1904688Sgblack@eecs.umich.edu _src1, _src2, _dest, _dataSize, _ext, 1914581Sgblack@eecs.umich.edu %(op_class)s) 1924519Sgblack@eecs.umich.edu { 1934519Sgblack@eecs.umich.edu buildMe(); 1944519Sgblack@eecs.umich.edu } 1954519Sgblack@eecs.umich.edu}}; 1964519Sgblack@eecs.umich.edu 1974519Sgblack@eecs.umich.edudef template MicroRegOpImmConstructor {{ 1984519Sgblack@eecs.umich.edu 1994519Sgblack@eecs.umich.edu inline void %(class_name)sImm::buildMe() 2004519Sgblack@eecs.umich.edu { 2014519Sgblack@eecs.umich.edu %(constructor)s; 2024519Sgblack@eecs.umich.edu } 2034519Sgblack@eecs.umich.edu 2044519Sgblack@eecs.umich.edu inline %(class_name)sImm::%(class_name)sImm( 2054519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2064519Sgblack@eecs.umich.edu RegIndex _src1, uint8_t _imm8, RegIndex _dest, 2074712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2084519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2094581Sgblack@eecs.umich.edu false, false, false, false, 2104688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2114581Sgblack@eecs.umich.edu %(op_class)s) 2124519Sgblack@eecs.umich.edu { 2134519Sgblack@eecs.umich.edu buildMe(); 2144519Sgblack@eecs.umich.edu } 2154519Sgblack@eecs.umich.edu 2164519Sgblack@eecs.umich.edu inline %(class_name)sImm::%(class_name)sImm( 2174519Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 2184519Sgblack@eecs.umich.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 2194519Sgblack@eecs.umich.edu RegIndex _src1, uint8_t _imm8, RegIndex _dest, 2204712Sgblack@eecs.umich.edu uint8_t _dataSize, uint16_t _ext) : 2214519Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2224581Sgblack@eecs.umich.edu isMicro, isDelayed, isFirst, isLast, 2234688Sgblack@eecs.umich.edu _src1, _imm8, _dest, _dataSize, _ext, 2244581Sgblack@eecs.umich.edu %(op_class)s) 2254519Sgblack@eecs.umich.edu { 2264519Sgblack@eecs.umich.edu buildMe(); 2274519Sgblack@eecs.umich.edu } 2284519Sgblack@eecs.umich.edu}}; 2294519Sgblack@eecs.umich.edu 2304519Sgblack@eecs.umich.edulet {{ 2314688Sgblack@eecs.umich.edu class X86MicroMeta(type): 2324688Sgblack@eecs.umich.edu def __new__(mcls, name, bases, dict): 2334688Sgblack@eecs.umich.edu abstract = False 2344688Sgblack@eecs.umich.edu if "abstract" in dict: 2354688Sgblack@eecs.umich.edu abstract = dict['abstract'] 2364688Sgblack@eecs.umich.edu del dict['abstract'] 2374688Sgblack@eecs.umich.edu 2384688Sgblack@eecs.umich.edu cls = type.__new__(mcls, name, bases, dict) 2394688Sgblack@eecs.umich.edu if not abstract: 2404688Sgblack@eecs.umich.edu allClasses[name] = cls 2414688Sgblack@eecs.umich.edu return cls 2424688Sgblack@eecs.umich.edu 2434688Sgblack@eecs.umich.edu class XXX86Microop(object): 2444688Sgblack@eecs.umich.edu __metaclass__ = X86MicroMeta 2454688Sgblack@eecs.umich.edu abstract = True 2464688Sgblack@eecs.umich.edu 2474528Sgblack@eecs.umich.edu class RegOp(X86Microop): 2484688Sgblack@eecs.umich.edu abstract = True 2494701Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2, flags, dataSize): 2504519Sgblack@eecs.umich.edu self.dest = dest 2514519Sgblack@eecs.umich.edu self.src1 = src1 2524519Sgblack@eecs.umich.edu self.src2 = src2 2534688Sgblack@eecs.umich.edu self.flags = flags 2544701Sgblack@eecs.umich.edu self.dataSize = dataSize 2554688Sgblack@eecs.umich.edu if flags is None: 2564688Sgblack@eecs.umich.edu self.ext = 0 2574688Sgblack@eecs.umich.edu else: 2584688Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 2594688Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 2604688Sgblack@eecs.umich.edu self.ext = " | ".join(flags) 2614688Sgblack@eecs.umich.edu self.className += "Flags" 2624519Sgblack@eecs.umich.edu 2634519Sgblack@eecs.umich.edu def getAllocator(self, *microFlags): 2644560Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, mnemonic 2654539Sgblack@eecs.umich.edu %(flags)s, %(src1)s, %(src2)s, %(dest)s, 2664688Sgblack@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 2674519Sgblack@eecs.umich.edu "class_name" : self.className, 2684519Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 2694519Sgblack@eecs.umich.edu "src1" : self.src1, "src2" : self.src2, 2704519Sgblack@eecs.umich.edu "dest" : self.dest, 2714519Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 2724519Sgblack@eecs.umich.edu "ext" : self.ext} 2734539Sgblack@eecs.umich.edu return allocator 2744519Sgblack@eecs.umich.edu 2754528Sgblack@eecs.umich.edu class RegOpImm(X86Microop): 2764688Sgblack@eecs.umich.edu abstract = True 2774701Sgblack@eecs.umich.edu def __init__(self, dest, src1, imm8, flags, dataSize): 2784519Sgblack@eecs.umich.edu self.dest = dest 2794519Sgblack@eecs.umich.edu self.src1 = src1 2804560Sgblack@eecs.umich.edu self.imm8 = imm8 2814688Sgblack@eecs.umich.edu self.flags = flags 2824701Sgblack@eecs.umich.edu self.dataSize = dataSize 2834688Sgblack@eecs.umich.edu if flags is None: 2844688Sgblack@eecs.umich.edu self.ext = 0 2854688Sgblack@eecs.umich.edu else: 2864688Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 2874688Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 2884688Sgblack@eecs.umich.edu self.ext = " | ".join(flags) 2894688Sgblack@eecs.umich.edu self.className += "Flags" 2904519Sgblack@eecs.umich.edu 2914519Sgblack@eecs.umich.edu def getAllocator(self, *microFlags): 2924560Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, mnemonic 2934539Sgblack@eecs.umich.edu %(flags)s, %(src1)s, %(imm8)s, %(dest)s, 2944688Sgblack@eecs.umich.edu %(dataSize)s, %(ext)s)''' % { 2954519Sgblack@eecs.umich.edu "class_name" : self.className, 2964519Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 2974519Sgblack@eecs.umich.edu "src1" : self.src1, "imm8" : self.imm8, 2984519Sgblack@eecs.umich.edu "dest" : self.dest, 2994519Sgblack@eecs.umich.edu "dataSize" : self.dataSize, 3004519Sgblack@eecs.umich.edu "ext" : self.ext} 3014539Sgblack@eecs.umich.edu return allocator 3024519Sgblack@eecs.umich.edu}}; 3034519Sgblack@eecs.umich.edu 3044519Sgblack@eecs.umich.edulet {{ 3054519Sgblack@eecs.umich.edu 3064519Sgblack@eecs.umich.edu # Make these empty strings so that concatenating onto 3074519Sgblack@eecs.umich.edu # them will always work. 3084519Sgblack@eecs.umich.edu header_output = "" 3094519Sgblack@eecs.umich.edu decoder_output = "" 3104519Sgblack@eecs.umich.edu exec_output = "" 3114519Sgblack@eecs.umich.edu 3124688Sgblack@eecs.umich.edu # A function which builds the C++ classes that implement the microops 3134714Sgblack@eecs.umich.edu def setUpMicroRegOp(name, Name, base, code, flagCode = "", condCheck = "true", elseCode = ";"): 3144519Sgblack@eecs.umich.edu global header_output 3154519Sgblack@eecs.umich.edu global decoder_output 3164519Sgblack@eecs.umich.edu global exec_output 3174528Sgblack@eecs.umich.edu global microopClasses 3184595Sgblack@eecs.umich.edu 3194612Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, base, 3204612Sgblack@eecs.umich.edu {"code" : code, 3214688Sgblack@eecs.umich.edu "flag_code" : flagCode, 3224708Sgblack@eecs.umich.edu "cond_check" : condCheck, 3234708Sgblack@eecs.umich.edu "else_code" : elseCode}) 3244595Sgblack@eecs.umich.edu header_output += MicroRegOpDeclare.subst(iop) 3254595Sgblack@eecs.umich.edu decoder_output += MicroRegOpConstructor.subst(iop) 3264595Sgblack@eecs.umich.edu exec_output += MicroRegOpExecute.subst(iop) 3274595Sgblack@eecs.umich.edu 3284595Sgblack@eecs.umich.edu 3294688Sgblack@eecs.umich.edu checkCCFlagBits = "checkCondition(ccFlagBits)" 3304798Sgblack@eecs.umich.edu genCCFlagBits = \ 3314823Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" 3324798Sgblack@eecs.umich.edu genCCFlagBitsSub = \ 3334823Sgblack@eecs.umich.edu "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 3344798Sgblack@eecs.umich.edu genCCFlagBitsLogic = ''' 3354798Sgblack@eecs.umich.edu //Don't have genFlags handle the OF or CF bits 3364798Sgblack@eecs.umich.edu uint64_t mask = CFBit | OFBit; 3374823Sgblack@eecs.umich.edu ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); 3384798Sgblack@eecs.umich.edu //If a logic microop wants to set these, it wants to set them to 0. 3394798Sgblack@eecs.umich.edu ccFlagBits &= ~(CFBit & ext); 3404798Sgblack@eecs.umich.edu ccFlagBits &= ~(OFBit & ext); 3414798Sgblack@eecs.umich.edu ''' 3424688Sgblack@eecs.umich.edu 3434809Sgblack@eecs.umich.edu regPick = ''' 3444823Sgblack@eecs.umich.edu IntReg psrc1 = pick(SrcReg1, 0, dataSize); 3454823Sgblack@eecs.umich.edu IntReg psrc2 = pick(SrcReg2, 1, dataSize); 3464809Sgblack@eecs.umich.edu ''' 3474809Sgblack@eecs.umich.edu immPick = ''' 3484823Sgblack@eecs.umich.edu IntReg psrc1 = pick(SrcReg1, 0, dataSize); 3494809Sgblack@eecs.umich.edu ''' 3504809Sgblack@eecs.umich.edu 3514688Sgblack@eecs.umich.edu 3524688Sgblack@eecs.umich.edu # This creates a python representations of a microop which are a cross 3534688Sgblack@eecs.umich.edu # product of reg/immediate and flag/no flag versions. 3544798Sgblack@eecs.umich.edu def defineMicroRegOp(mnemonic, code, flagCode=genCCFlagBits, \ 3554798Sgblack@eecs.umich.edu cc=False, elseCode=";"): 3564519Sgblack@eecs.umich.edu Name = mnemonic 3574519Sgblack@eecs.umich.edu name = mnemonic.lower() 3584519Sgblack@eecs.umich.edu 3594519Sgblack@eecs.umich.edu # Find op2 in each of the instruction definitions. Create two versions 3604519Sgblack@eecs.umich.edu # of the code, one with an integer operand, and one with an immediate 3614519Sgblack@eecs.umich.edu # operand. 3624519Sgblack@eecs.umich.edu matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 3634823Sgblack@eecs.umich.edu regCode = regPick + matcher.sub("psrc2", code) 3644809Sgblack@eecs.umich.edu immCode = immPick + matcher.sub("imm8", code) 3654519Sgblack@eecs.umich.edu 3664688Sgblack@eecs.umich.edu if not cc: 3674688Sgblack@eecs.umich.edu condCode = "true" 3684688Sgblack@eecs.umich.edu else: 3694688Sgblack@eecs.umich.edu flagCode = "" 3704688Sgblack@eecs.umich.edu condCode = checkCCFlagBits 3714688Sgblack@eecs.umich.edu 3724823Sgblack@eecs.umich.edu regFlagCode = matcher.sub("psrc2", flagCode) 3734688Sgblack@eecs.umich.edu immFlagCode = matcher.sub("imm8", flagCode) 3744688Sgblack@eecs.umich.edu 3754519Sgblack@eecs.umich.edu class RegOpChild(RegOp): 3764688Sgblack@eecs.umich.edu mnemonic = name 3774688Sgblack@eecs.umich.edu className = Name 3784798Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2, \ 3794798Sgblack@eecs.umich.edu flags=None, dataSize="env.dataSize"): 3804798Sgblack@eecs.umich.edu super(RegOpChild, self).__init__(dest, src1, src2, \ 3814798Sgblack@eecs.umich.edu flags, dataSize) 3824519Sgblack@eecs.umich.edu 3834688Sgblack@eecs.umich.edu microopClasses[name] = RegOpChild 3844519Sgblack@eecs.umich.edu 3854714Sgblack@eecs.umich.edu setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode); 3864809Sgblack@eecs.umich.edu setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", 3874809Sgblack@eecs.umich.edu regCode, flagCode=regFlagCode, 3884809Sgblack@eecs.umich.edu condCheck=condCode, elseCode=elseCode); 3894688Sgblack@eecs.umich.edu 3904595Sgblack@eecs.umich.edu class RegOpChildImm(RegOpImm): 3914688Sgblack@eecs.umich.edu mnemonic = name + 'i' 3924688Sgblack@eecs.umich.edu className = Name + 'Imm' 3934798Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2, \ 3944798Sgblack@eecs.umich.edu flags=None, dataSize="env.dataSize"): 3954798Sgblack@eecs.umich.edu super(RegOpChildImm, self).__init__(dest, src1, src2, \ 3964798Sgblack@eecs.umich.edu flags, dataSize) 3974519Sgblack@eecs.umich.edu 3984688Sgblack@eecs.umich.edu microopClasses[name + 'i'] = RegOpChildImm 3994519Sgblack@eecs.umich.edu 4004714Sgblack@eecs.umich.edu setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode); 4014809Sgblack@eecs.umich.edu setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm", 4024809Sgblack@eecs.umich.edu immCode, flagCode=immFlagCode, 4034809Sgblack@eecs.umich.edu condCheck=condCode, elseCode=elseCode); 4044688Sgblack@eecs.umich.edu 4054592Sgblack@eecs.umich.edu # This has it's own function because Wr ops have implicit destinations 4064708Sgblack@eecs.umich.edu def defineMicroRegOpWr(mnemonic, code, elseCode=";"): 4074592Sgblack@eecs.umich.edu Name = mnemonic 4084592Sgblack@eecs.umich.edu name = mnemonic.lower() 4094592Sgblack@eecs.umich.edu 4104592Sgblack@eecs.umich.edu # Find op2 in each of the instruction definitions. Create two versions 4114592Sgblack@eecs.umich.edu # of the code, one with an integer operand, and one with an immediate 4124592Sgblack@eecs.umich.edu # operand. 4134592Sgblack@eecs.umich.edu matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 4144823Sgblack@eecs.umich.edu regCode = regPick + matcher.sub("psrc2", code) 4154809Sgblack@eecs.umich.edu immCode = immPick + matcher.sub("imm8", code) 4164592Sgblack@eecs.umich.edu 4174592Sgblack@eecs.umich.edu class RegOpChild(RegOp): 4184688Sgblack@eecs.umich.edu mnemonic = name 4194688Sgblack@eecs.umich.edu className = Name 4204701Sgblack@eecs.umich.edu def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 4214701Sgblack@eecs.umich.edu super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) 4224688Sgblack@eecs.umich.edu 4234688Sgblack@eecs.umich.edu microopClasses[name] = RegOpChild 4244688Sgblack@eecs.umich.edu 4254714Sgblack@eecs.umich.edu setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode); 4264714Sgblack@eecs.umich.edu setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode, 4274714Sgblack@eecs.umich.edu condCheck = checkCCFlagBits, elseCode = elseCode); 4284688Sgblack@eecs.umich.edu 4294688Sgblack@eecs.umich.edu class RegOpChildImm(RegOpImm): 4304708Sgblack@eecs.umich.edu mnemonic = name + 'i' 4314708Sgblack@eecs.umich.edu className = Name + 'Imm' 4324701Sgblack@eecs.umich.edu def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 4334701Sgblack@eecs.umich.edu super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize) 4344592Sgblack@eecs.umich.edu 4354688Sgblack@eecs.umich.edu microopClasses[name + 'i'] = RegOpChildImm 4364592Sgblack@eecs.umich.edu 4374714Sgblack@eecs.umich.edu setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode); 4384714Sgblack@eecs.umich.edu setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode, 4394714Sgblack@eecs.umich.edu condCheck = checkCCFlagBits, elseCode = elseCode); 4404592Sgblack@eecs.umich.edu 4414592Sgblack@eecs.umich.edu # This has it's own function because Rd ops don't always have two parameters 4424592Sgblack@eecs.umich.edu def defineMicroRegOpRd(mnemonic, code): 4434592Sgblack@eecs.umich.edu Name = mnemonic 4444592Sgblack@eecs.umich.edu name = mnemonic.lower() 4454592Sgblack@eecs.umich.edu 4464592Sgblack@eecs.umich.edu class RegOpChild(RegOp): 4474701Sgblack@eecs.umich.edu def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"): 4484701Sgblack@eecs.umich.edu super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize) 4494592Sgblack@eecs.umich.edu self.className = Name 4504592Sgblack@eecs.umich.edu self.mnemonic = name 4514592Sgblack@eecs.umich.edu 4524688Sgblack@eecs.umich.edu microopClasses[name] = RegOpChild 4534688Sgblack@eecs.umich.edu 4544714Sgblack@eecs.umich.edu setUpMicroRegOp(name, Name, "X86ISA::RegOp", code); 4554592Sgblack@eecs.umich.edu 4564595Sgblack@eecs.umich.edu def defineMicroRegOpImm(mnemonic, code): 4574595Sgblack@eecs.umich.edu Name = mnemonic 4584595Sgblack@eecs.umich.edu name = mnemonic.lower() 4594809Sgblack@eecs.umich.edu code = immPick + code 4604595Sgblack@eecs.umich.edu 4614595Sgblack@eecs.umich.edu class RegOpChild(RegOpImm): 4624701Sgblack@eecs.umich.edu def __init__(self, dest, src1, src2, dataSize="env.dataSize"): 4634701Sgblack@eecs.umich.edu super(RegOpChild, self).__init__(dest, src1, src2, None, dataSize) 4644595Sgblack@eecs.umich.edu self.className = Name 4654595Sgblack@eecs.umich.edu self.mnemonic = name 4664595Sgblack@eecs.umich.edu 4674688Sgblack@eecs.umich.edu microopClasses[name] = RegOpChild 4684688Sgblack@eecs.umich.edu 4694714Sgblack@eecs.umich.edu setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code); 4704595Sgblack@eecs.umich.edu 4714823Sgblack@eecs.umich.edu defineMicroRegOp('Add', 'DestReg = merge(DestReg, psrc1 + op2, dataSize)') 4724823Sgblack@eecs.umich.edu defineMicroRegOp('Or', 'DestReg = merge(DestReg, psrc1 | op2, dataSize);', 4734798Sgblack@eecs.umich.edu flagCode = genCCFlagBitsLogic) 4744732Sgblack@eecs.umich.edu defineMicroRegOp('Adc', ''' 4754732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 4764823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 + op2 + flags.CF, dataSize); 4774732Sgblack@eecs.umich.edu ''') 4784732Sgblack@eecs.umich.edu defineMicroRegOp('Sbb', ''' 4794732Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 4804823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 - op2 - flags.CF, dataSize); 4814798Sgblack@eecs.umich.edu ''', flagCode = genCCFlagBitsSub) 4824798Sgblack@eecs.umich.edu defineMicroRegOp('And', \ 4834823Sgblack@eecs.umich.edu 'DestReg = merge(DestReg, psrc1 & op2, dataSize)', \ 4844798Sgblack@eecs.umich.edu flagCode = genCCFlagBitsLogic) 4854798Sgblack@eecs.umich.edu defineMicroRegOp('Sub', \ 4864823Sgblack@eecs.umich.edu 'DestReg = merge(DestReg, psrc1 - op2, dataSize)', \ 4874798Sgblack@eecs.umich.edu flagCode = genCCFlagBitsSub) 4884798Sgblack@eecs.umich.edu defineMicroRegOp('Xor', \ 4894823Sgblack@eecs.umich.edu 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)', \ 4904798Sgblack@eecs.umich.edu flagCode = genCCFlagBitsLogic) 4914809Sgblack@eecs.umich.edu defineMicroRegOp('Mul1s', ''' 4924809Sgblack@eecs.umich.edu int signPos = (dataSize * 8) / 2 - 1; 4934823Sgblack@eecs.umich.edu IntReg srcVal1 = psrc1 | (-bits(psrc1, signPos) << signPos); 4944823Sgblack@eecs.umich.edu IntReg srcVal2 = op2 | (-bits(psrc1, signPos) << signPos); 4954809Sgblack@eecs.umich.edu DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize) 4964809Sgblack@eecs.umich.edu ''') 4974809Sgblack@eecs.umich.edu defineMicroRegOp('Mul1u', ''' 4984809Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 4994823Sgblack@eecs.umich.edu IntReg srcVal1 = psrc1 & mask(halfSize); 5004809Sgblack@eecs.umich.edu IntReg srcVal2 = op2 & mask(halfSize); 5014809Sgblack@eecs.umich.edu DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize) 5024809Sgblack@eecs.umich.edu ''') 5034809Sgblack@eecs.umich.edu defineMicroRegOp('Mulel', \ 5044823Sgblack@eecs.umich.edu 'DestReg = merge(DestReg, psrc1 * op2, dataSize)') 5054809Sgblack@eecs.umich.edu defineMicroRegOp('Muleh', ''' 5064809Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5074823Sgblack@eecs.umich.edu uint64_t psrc1_h = psrc1 >> halfSize; 5084823Sgblack@eecs.umich.edu uint64_t psrc1_l = psrc1 & mask(halfSize); 5094823Sgblack@eecs.umich.edu uint64_t psrc2_h = op2 >> halfSize; 5104823Sgblack@eecs.umich.edu uint64_t psrc2_l = op2 & mask(halfSize); 5114809Sgblack@eecs.umich.edu uint64_t result = 5124823Sgblack@eecs.umich.edu ((psrc1_l * psrc2_h) >> halfSize) + 5134823Sgblack@eecs.umich.edu ((psrc1_h * psrc2_l) >> halfSize) + 5144823Sgblack@eecs.umich.edu psrc1_h * psrc2_h; 5154809Sgblack@eecs.umich.edu DestReg = merge(DestReg, result, dataSize); 5164809Sgblack@eecs.umich.edu ''') 5174823Sgblack@eecs.umich.edu defineMicroRegOp('Div1', ''' 5184823Sgblack@eecs.umich.edu int halfSize = (dataSize * 8) / 2; 5194823Sgblack@eecs.umich.edu IntReg quotient = (psrc1 / op2) & mask(halfSize); 5204823Sgblack@eecs.umich.edu IntReg remainder = (psrc1 % op2) & mask(halfSize); 5214823Sgblack@eecs.umich.edu IntReg result = quotient | (remainder << halfSize); 5224823Sgblack@eecs.umich.edu DestReg = merge(DestReg, result, dataSize); 5234823Sgblack@eecs.umich.edu ''') 5244823Sgblack@eecs.umich.edu defineMicroRegOp('Divq', ''' 5254823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 / op2, dataSize); 5264823Sgblack@eecs.umich.edu ''') 5274823Sgblack@eecs.umich.edu defineMicroRegOp('Divr', ''' 5284823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 % op2, dataSize); 5294823Sgblack@eecs.umich.edu ''') 5304823Sgblack@eecs.umich.edu 5314809Sgblack@eecs.umich.edu # 5324823Sgblack@eecs.umich.edu # HACK HACK HACK HACK - Put psrc1 in here but make it inert to shut up gcc. 5334809Sgblack@eecs.umich.edu # 5344823Sgblack@eecs.umich.edu defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, psrc1 * 0 + op2, dataSize)', 5354732Sgblack@eecs.umich.edu elseCode='DestReg=DestReg;', cc=True) 5364732Sgblack@eecs.umich.edu 5374732Sgblack@eecs.umich.edu # Shift instructions 5384732Sgblack@eecs.umich.edu defineMicroRegOp('Sll', ''' 5394756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 5404823Sgblack@eecs.umich.edu DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 5414732Sgblack@eecs.umich.edu ''') 5424732Sgblack@eecs.umich.edu defineMicroRegOp('Srl', ''' 5434756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 5444732Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 5454732Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to mask them out 5464732Sgblack@eecs.umich.edu // to be sure they're zero. 5474732Sgblack@eecs.umich.edu uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 5484823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 5494732Sgblack@eecs.umich.edu ''') 5504732Sgblack@eecs.umich.edu defineMicroRegOp('Sra', ''' 5514756Sgblack@eecs.umich.edu uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 5524732Sgblack@eecs.umich.edu // Because what happens to the bits shift -in- on a right shift 5534732Sgblack@eecs.umich.edu // is not defined in the C/C++ standard, we have to sign extend 5544732Sgblack@eecs.umich.edu // them manually to be sure. 5554732Sgblack@eecs.umich.edu uint64_t arithMask = 5564732Sgblack@eecs.umich.edu -bits(op2, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 5574823Sgblack@eecs.umich.edu DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 5584732Sgblack@eecs.umich.edu ''') 5594732Sgblack@eecs.umich.edu defineMicroRegOp('Ror', ''' 5604732Sgblack@eecs.umich.edu uint8_t shiftAmt = 5614756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 5624732Sgblack@eecs.umich.edu if(shiftAmt) 5634732Sgblack@eecs.umich.edu { 5644823Sgblack@eecs.umich.edu uint64_t top = psrc1 << (dataSize * 8 - shiftAmt); 5654823Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); 5664732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 5674732Sgblack@eecs.umich.edu } 5684732Sgblack@eecs.umich.edu else 5694732Sgblack@eecs.umich.edu DestReg = DestReg; 5704732Sgblack@eecs.umich.edu ''') 5714732Sgblack@eecs.umich.edu defineMicroRegOp('Rcr', ''' 5724733Sgblack@eecs.umich.edu uint8_t shiftAmt = 5734756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 5744733Sgblack@eecs.umich.edu if(shiftAmt) 5754733Sgblack@eecs.umich.edu { 5764733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 5774733Sgblack@eecs.umich.edu uint64_t top = flags.CF << (dataSize * 8 - shiftAmt); 5784733Sgblack@eecs.umich.edu if(shiftAmt > 1) 5794823Sgblack@eecs.umich.edu top |= psrc1 << (dataSize * 8 - shiftAmt - 1); 5804823Sgblack@eecs.umich.edu uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt); 5814733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 5824733Sgblack@eecs.umich.edu } 5834733Sgblack@eecs.umich.edu else 5844733Sgblack@eecs.umich.edu DestReg = DestReg; 5854732Sgblack@eecs.umich.edu ''') 5864732Sgblack@eecs.umich.edu defineMicroRegOp('Rol', ''' 5874732Sgblack@eecs.umich.edu uint8_t shiftAmt = 5884756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 5894732Sgblack@eecs.umich.edu if(shiftAmt) 5904732Sgblack@eecs.umich.edu { 5914823Sgblack@eecs.umich.edu uint64_t top = psrc1 << shiftAmt; 5924732Sgblack@eecs.umich.edu uint64_t bottom = 5934823Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, dataSize * 8 - shiftAmt); 5944732Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 5954732Sgblack@eecs.umich.edu } 5964732Sgblack@eecs.umich.edu else 5974732Sgblack@eecs.umich.edu DestReg = DestReg; 5984732Sgblack@eecs.umich.edu ''') 5994732Sgblack@eecs.umich.edu defineMicroRegOp('Rcl', ''' 6004733Sgblack@eecs.umich.edu uint8_t shiftAmt = 6014756Sgblack@eecs.umich.edu (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 6024733Sgblack@eecs.umich.edu if(shiftAmt) 6034733Sgblack@eecs.umich.edu { 6044733Sgblack@eecs.umich.edu CCFlagBits flags = ccFlagBits; 6054823Sgblack@eecs.umich.edu uint64_t top = psrc1 << shiftAmt; 6064733Sgblack@eecs.umich.edu uint64_t bottom = flags.CF << (shiftAmt - 1); 6074733Sgblack@eecs.umich.edu if(shiftAmt > 1) 6084733Sgblack@eecs.umich.edu bottom |= 6094823Sgblack@eecs.umich.edu bits(psrc1, dataSize * 8 - 1, 6104809Sgblack@eecs.umich.edu dataSize * 8 - shiftAmt + 1); 6114733Sgblack@eecs.umich.edu DestReg = merge(DestReg, top | bottom, dataSize); 6124733Sgblack@eecs.umich.edu } 6134733Sgblack@eecs.umich.edu else 6144733Sgblack@eecs.umich.edu DestReg = DestReg; 6154732Sgblack@eecs.umich.edu ''') 6164732Sgblack@eecs.umich.edu 6174823Sgblack@eecs.umich.edu defineMicroRegOpWr('Wrip', 'RIP = psrc1 + op2', elseCode="RIP = RIP;") 6184868Sgblack@eecs.umich.edu defineMicroRegOpWr('Wruflags', 'ccFlagBits = psrc1 ^ op2') 6194732Sgblack@eecs.umich.edu 6204732Sgblack@eecs.umich.edu defineMicroRegOpRd('Rdip', 'DestReg = RIP') 6214868Sgblack@eecs.umich.edu defineMicroRegOpRd('Ruflags', 'DestReg = ccFlagBits') 6224868Sgblack@eecs.umich.edu defineMicroRegOpImm('Ruflag', 'DestReg = bits(ccFlagBits, imm8);', \ 6234868Sgblack@eecs.umich.edu flagCode = genCCFlagBitsLogic) 6244732Sgblack@eecs.umich.edu 6254595Sgblack@eecs.umich.edu defineMicroRegOpImm('Sext', ''' 6264823Sgblack@eecs.umich.edu IntReg val = psrc1; 6274595Sgblack@eecs.umich.edu int sign_bit = bits(val, imm8-1, imm8-1); 6284595Sgblack@eecs.umich.edu val = sign_bit ? (val | ~mask(imm8)) : val; 6294595Sgblack@eecs.umich.edu DestReg = merge(DestReg, val, dataSize);''') 6304714Sgblack@eecs.umich.edu 6314823Sgblack@eecs.umich.edu defineMicroRegOpImm('Zext', 'DestReg = bits(psrc1, imm8-1, 0);') 6324519Sgblack@eecs.umich.edu}}; 633