regop.isa revision 4868
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41//
42// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
43// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
44// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
45// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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47// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
48// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
49// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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51// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
52// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
53//
54// Authors: Gabe Black
55
56//////////////////////////////////////////////////////////////////////////
57//
58// RegOp Microop templates
59//
60//////////////////////////////////////////////////////////////////////////
61
62def template MicroRegOpExecute {{
63        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
64                Trace::InstRecord *traceData) const
65        {
66            Fault fault = NoFault;
67
68            DPRINTF(X86, "The data size is %d\n", dataSize);
69            %(op_decl)s;
70            %(op_rd)s;
71
72            if(%(cond_check)s)
73            {
74                %(code)s;
75                %(flag_code)s;
76            }
77            else
78            {
79                %(else_code)s;
80            }
81
82            //Write the resulting state to the execution context
83            if(fault == NoFault)
84            {
85                %(op_wb)s;
86            }
87            return fault;
88        }
89}};
90
91def template MicroRegOpImmExecute {{
92        Fault %(class_name)sImm::execute(%(CPU_exec_context)s *xc,
93                Trace::InstRecord *traceData) const
94        {
95            Fault fault = NoFault;
96
97            %(op_decl)s;
98            %(op_rd)s;
99
100            if(%(cond_check)s)
101            {
102                %(code)s;
103                %(flag_code)s;
104            }
105            else
106            {
107                %(else_code)s;
108            }
109
110            //Write the resulting state to the execution context
111            if(fault == NoFault)
112            {
113                %(op_wb)s;
114            }
115            return fault;
116        }
117}};
118
119def template MicroRegOpDeclare {{
120    class %(class_name)s : public %(base_class)s
121    {
122      protected:
123        void buildMe();
124
125      public:
126        %(class_name)s(ExtMachInst _machInst,
127                const char * instMnem,
128                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
129                RegIndex _src1, RegIndex _src2, RegIndex _dest,
130                uint8_t _dataSize, uint16_t _ext);
131
132        %(class_name)s(ExtMachInst _machInst,
133                const char * instMnem,
134                RegIndex _src1, RegIndex _src2, RegIndex _dest,
135                uint8_t _dataSize, uint16_t _ext);
136
137        %(BasicExecDeclare)s
138    };
139}};
140
141def template MicroRegOpImmDeclare {{
142
143    class %(class_name)sImm : public %(base_class)s
144    {
145      protected:
146        void buildMe();
147
148      public:
149        %(class_name)sImm(ExtMachInst _machInst,
150                const char * instMnem,
151                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
152                RegIndex _src1, uint8_t _imm8, RegIndex _dest,
153                uint8_t _dataSize, uint16_t _ext);
154
155        %(class_name)sImm(ExtMachInst _machInst,
156                const char * instMnem,
157                RegIndex _src1, uint8_t _imm8, RegIndex _dest,
158                uint8_t _dataSize, uint16_t _ext);
159
160        %(BasicExecDeclare)s
161    };
162}};
163
164def template MicroRegOpConstructor {{
165
166    inline void %(class_name)s::buildMe()
167    {
168        %(constructor)s;
169    }
170
171    inline %(class_name)s::%(class_name)s(
172            ExtMachInst machInst, const char * instMnem,
173            RegIndex _src1, RegIndex _src2, RegIndex _dest,
174            uint8_t _dataSize, uint16_t _ext) :
175        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
176                false, false, false, false,
177                _src1, _src2, _dest, _dataSize, _ext,
178                %(op_class)s)
179    {
180        buildMe();
181    }
182
183    inline %(class_name)s::%(class_name)s(
184            ExtMachInst machInst, const char * instMnem,
185            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
186            RegIndex _src1, RegIndex _src2, RegIndex _dest,
187            uint8_t _dataSize, uint16_t _ext) :
188        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
189                isMicro, isDelayed, isFirst, isLast,
190                _src1, _src2, _dest, _dataSize, _ext,
191                %(op_class)s)
192    {
193        buildMe();
194    }
195}};
196
197def template MicroRegOpImmConstructor {{
198
199    inline void %(class_name)sImm::buildMe()
200    {
201        %(constructor)s;
202    }
203
204    inline %(class_name)sImm::%(class_name)sImm(
205            ExtMachInst machInst, const char * instMnem,
206            RegIndex _src1, uint8_t _imm8, RegIndex _dest,
207            uint8_t _dataSize, uint16_t _ext) :
208        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
209                false, false, false, false,
210                _src1, _imm8, _dest, _dataSize, _ext,
211                %(op_class)s)
212    {
213        buildMe();
214    }
215
216    inline %(class_name)sImm::%(class_name)sImm(
217            ExtMachInst machInst, const char * instMnem,
218            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
219            RegIndex _src1, uint8_t _imm8, RegIndex _dest,
220            uint8_t _dataSize, uint16_t _ext) :
221        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
222                isMicro, isDelayed, isFirst, isLast,
223                _src1, _imm8, _dest, _dataSize, _ext,
224                %(op_class)s)
225    {
226        buildMe();
227    }
228}};
229
230let {{
231    class X86MicroMeta(type):
232        def __new__(mcls, name, bases, dict):
233            abstract = False
234            if "abstract" in dict:
235                abstract = dict['abstract']
236                del dict['abstract']
237
238            cls = type.__new__(mcls, name, bases, dict)
239            if not abstract:
240                allClasses[name] = cls
241            return cls
242
243    class XXX86Microop(object):
244        __metaclass__ = X86MicroMeta
245        abstract = True
246
247    class RegOp(X86Microop):
248        abstract = True
249        def __init__(self, dest, src1, src2, flags, dataSize):
250            self.dest = dest
251            self.src1 = src1
252            self.src2 = src2
253            self.flags = flags
254            self.dataSize = dataSize
255            if flags is None:
256                self.ext = 0
257            else:
258                if not isinstance(flags, (list, tuple)):
259                    raise Exception, "flags must be a list or tuple of flags"
260                self.ext = " | ".join(flags)
261                self.className += "Flags"
262
263        def getAllocator(self, *microFlags):
264            allocator = '''new %(class_name)s(machInst, mnemonic
265                    %(flags)s, %(src1)s, %(src2)s, %(dest)s,
266                    %(dataSize)s, %(ext)s)''' % {
267                "class_name" : self.className,
268                "flags" : self.microFlagsText(microFlags),
269                "src1" : self.src1, "src2" : self.src2,
270                "dest" : self.dest,
271                "dataSize" : self.dataSize,
272                "ext" : self.ext}
273            return allocator
274
275    class RegOpImm(X86Microop):
276        abstract = True
277        def __init__(self, dest, src1, imm8, flags, dataSize):
278            self.dest = dest
279            self.src1 = src1
280            self.imm8 = imm8
281            self.flags = flags
282            self.dataSize = dataSize
283            if flags is None:
284                self.ext = 0
285            else:
286                if not isinstance(flags, (list, tuple)):
287                    raise Exception, "flags must be a list or tuple of flags"
288                self.ext = " | ".join(flags)
289                self.className += "Flags"
290
291        def getAllocator(self, *microFlags):
292            allocator = '''new %(class_name)s(machInst, mnemonic
293                    %(flags)s, %(src1)s, %(imm8)s, %(dest)s,
294                    %(dataSize)s, %(ext)s)''' % {
295                "class_name" : self.className,
296                "flags" : self.microFlagsText(microFlags),
297                "src1" : self.src1, "imm8" : self.imm8,
298                "dest" : self.dest,
299                "dataSize" : self.dataSize,
300                "ext" : self.ext}
301            return allocator
302}};
303
304let {{
305
306    # Make these empty strings so that concatenating onto
307    # them will always work.
308    header_output = ""
309    decoder_output = ""
310    exec_output = ""
311
312    # A function which builds the C++ classes that implement the microops
313    def setUpMicroRegOp(name, Name, base, code, flagCode = "", condCheck = "true", elseCode = ";"):
314        global header_output
315        global decoder_output
316        global exec_output
317        global microopClasses
318
319        iop = InstObjParams(name, Name, base,
320                {"code" : code,
321                 "flag_code" : flagCode,
322                 "cond_check" : condCheck,
323                 "else_code" : elseCode})
324        header_output += MicroRegOpDeclare.subst(iop)
325        decoder_output += MicroRegOpConstructor.subst(iop)
326        exec_output += MicroRegOpExecute.subst(iop)
327
328
329    checkCCFlagBits = "checkCondition(ccFlagBits)"
330    genCCFlagBits = \
331        "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);"
332    genCCFlagBitsSub = \
333        "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);"
334    genCCFlagBitsLogic = '''
335        //Don't have genFlags handle the OF or CF bits
336        uint64_t mask = CFBit | OFBit;
337        ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2);
338        //If a logic microop wants to set these, it wants to set them to 0.
339        ccFlagBits &= ~(CFBit & ext);
340        ccFlagBits &= ~(OFBit & ext);
341    '''
342
343    regPick = '''
344        IntReg psrc1 = pick(SrcReg1, 0, dataSize);
345        IntReg psrc2 = pick(SrcReg2, 1, dataSize);
346    '''
347    immPick = '''
348        IntReg psrc1 = pick(SrcReg1, 0, dataSize);
349    '''
350
351
352    # This creates a python representations of a microop which are a cross
353    # product of reg/immediate and flag/no flag versions.
354    def defineMicroRegOp(mnemonic, code, flagCode=genCCFlagBits, \
355            cc=False, elseCode=";"):
356        Name = mnemonic
357        name = mnemonic.lower()
358
359        # Find op2 in each of the instruction definitions. Create two versions
360        # of the code, one with an integer operand, and one with an immediate
361        # operand.
362        matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
363        regCode = regPick + matcher.sub("psrc2", code)
364        immCode = immPick + matcher.sub("imm8", code)
365
366        if not cc:
367            condCode = "true"
368        else:
369            flagCode = ""
370            condCode = checkCCFlagBits
371
372        regFlagCode = matcher.sub("psrc2", flagCode)
373        immFlagCode = matcher.sub("imm8", flagCode)
374
375        class RegOpChild(RegOp):
376            mnemonic = name
377            className = Name
378            def __init__(self, dest, src1, src2, \
379                    flags=None, dataSize="env.dataSize"):
380                super(RegOpChild, self).__init__(dest, src1, src2, \
381                        flags, dataSize)
382
383        microopClasses[name] = RegOpChild
384
385        setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode);
386        setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp",
387                regCode, flagCode=regFlagCode,
388                condCheck=condCode, elseCode=elseCode);
389
390        class RegOpChildImm(RegOpImm):
391            mnemonic = name + 'i'
392            className = Name + 'Imm'
393            def __init__(self, dest, src1, src2, \
394                    flags=None, dataSize="env.dataSize"):
395                super(RegOpChildImm, self).__init__(dest, src1, src2, \
396                        flags, dataSize)
397
398        microopClasses[name + 'i'] = RegOpChildImm
399
400        setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode);
401        setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm",
402                immCode, flagCode=immFlagCode,
403                condCheck=condCode, elseCode=elseCode);
404
405    # This has it's own function because Wr ops have implicit destinations
406    def defineMicroRegOpWr(mnemonic, code, elseCode=";"):
407        Name = mnemonic
408        name = mnemonic.lower()
409
410        # Find op2 in each of the instruction definitions. Create two versions
411        # of the code, one with an integer operand, and one with an immediate
412        # operand.
413        matcher = re.compile("op2(?P<typeQual>\\.\\w+)?")
414        regCode = regPick + matcher.sub("psrc2", code)
415        immCode = immPick + matcher.sub("imm8", code)
416
417        class RegOpChild(RegOp):
418            mnemonic = name
419            className = Name
420            def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
421                super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
422
423        microopClasses[name] = RegOpChild
424
425        setUpMicroRegOp(name, Name, "X86ISA::RegOp", regCode);
426        setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOp", regCode,
427                condCheck = checkCCFlagBits, elseCode = elseCode);
428
429        class RegOpChildImm(RegOpImm):
430            mnemonic = name + 'i'
431            className = Name + 'Imm'
432            def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"):
433                super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, flags, dataSize)
434
435        microopClasses[name + 'i'] = RegOpChildImm
436
437        setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode);
438        setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode,
439                condCheck = checkCCFlagBits, elseCode = elseCode);
440
441    # This has it's own function because Rd ops don't always have two parameters
442    def defineMicroRegOpRd(mnemonic, code):
443        Name = mnemonic
444        name = mnemonic.lower()
445
446        class RegOpChild(RegOp):
447            def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"):
448                super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
449                self.className = Name
450                self.mnemonic = name
451
452        microopClasses[name] = RegOpChild
453
454        setUpMicroRegOp(name, Name, "X86ISA::RegOp", code);
455
456    def defineMicroRegOpImm(mnemonic, code):
457        Name = mnemonic
458        name = mnemonic.lower()
459        code = immPick + code
460
461        class RegOpChild(RegOpImm):
462            def __init__(self, dest, src1, src2, dataSize="env.dataSize"):
463                super(RegOpChild, self).__init__(dest, src1, src2, None, dataSize)
464                self.className = Name
465                self.mnemonic = name
466
467        microopClasses[name] = RegOpChild
468
469        setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code);
470
471    defineMicroRegOp('Add', 'DestReg = merge(DestReg, psrc1 + op2, dataSize)')
472    defineMicroRegOp('Or', 'DestReg = merge(DestReg, psrc1 | op2, dataSize);',
473            flagCode = genCCFlagBitsLogic)
474    defineMicroRegOp('Adc', '''
475            CCFlagBits flags = ccFlagBits;
476            DestReg = merge(DestReg, psrc1 + op2 + flags.CF, dataSize);
477            ''')
478    defineMicroRegOp('Sbb', '''
479            CCFlagBits flags = ccFlagBits;
480            DestReg = merge(DestReg, psrc1 - op2 - flags.CF, dataSize);
481            ''', flagCode = genCCFlagBitsSub)
482    defineMicroRegOp('And', \
483            'DestReg = merge(DestReg, psrc1 & op2, dataSize)', \
484            flagCode = genCCFlagBitsLogic)
485    defineMicroRegOp('Sub', \
486            'DestReg = merge(DestReg, psrc1 - op2, dataSize)', \
487            flagCode = genCCFlagBitsSub)
488    defineMicroRegOp('Xor', \
489            'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)', \
490            flagCode = genCCFlagBitsLogic)
491    defineMicroRegOp('Mul1s', '''
492            int signPos = (dataSize * 8) / 2 - 1;
493            IntReg srcVal1 = psrc1 | (-bits(psrc1, signPos) << signPos);
494            IntReg srcVal2 = op2 | (-bits(psrc1, signPos) << signPos);
495            DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize)
496            ''')
497    defineMicroRegOp('Mul1u', '''
498            int halfSize = (dataSize * 8) / 2;
499            IntReg srcVal1 = psrc1 & mask(halfSize);
500            IntReg srcVal2 = op2 & mask(halfSize);
501            DestReg = merge(DestReg, srcVal1 * srcVal2, dataSize)
502            ''')
503    defineMicroRegOp('Mulel', \
504            'DestReg = merge(DestReg, psrc1 * op2, dataSize)')
505    defineMicroRegOp('Muleh', '''
506            int halfSize = (dataSize * 8) / 2;
507            uint64_t psrc1_h = psrc1 >> halfSize;
508            uint64_t psrc1_l = psrc1 & mask(halfSize);
509            uint64_t psrc2_h = op2 >> halfSize;
510            uint64_t psrc2_l = op2 & mask(halfSize);
511            uint64_t result =
512                ((psrc1_l * psrc2_h) >> halfSize) +
513                ((psrc1_h * psrc2_l) >> halfSize) +
514                psrc1_h * psrc2_h;
515            DestReg = merge(DestReg, result, dataSize);
516            ''')
517    defineMicroRegOp('Div1', '''
518            int halfSize = (dataSize * 8) / 2;
519            IntReg quotient = (psrc1 / op2) & mask(halfSize);
520            IntReg remainder = (psrc1 % op2) & mask(halfSize);
521            IntReg result = quotient | (remainder << halfSize);
522            DestReg = merge(DestReg, result, dataSize);
523            ''')
524    defineMicroRegOp('Divq', '''
525            DestReg = merge(DestReg, psrc1 / op2, dataSize);
526            ''')
527    defineMicroRegOp('Divr', '''
528            DestReg = merge(DestReg, psrc1 % op2, dataSize);
529            ''')
530
531    #
532    # HACK HACK HACK HACK - Put psrc1 in here but make it inert to shut up gcc.
533    #
534    defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, psrc1 * 0 + op2, dataSize)',
535            elseCode='DestReg=DestReg;', cc=True)
536
537    # Shift instructions
538    defineMicroRegOp('Sll', '''
539            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
540            DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize);
541            ''')
542    defineMicroRegOp('Srl', '''
543            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
544            // Because what happens to the bits shift -in- on a right shift
545            // is not defined in the C/C++ standard, we have to mask them out
546            // to be sure they're zero.
547            uint64_t logicalMask = mask(dataSize * 8 - shiftAmt);
548            DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize);
549            ''')
550    defineMicroRegOp('Sra', '''
551            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
552            // Because what happens to the bits shift -in- on a right shift
553            // is not defined in the C/C++ standard, we have to sign extend
554            // them manually to be sure.
555            uint64_t arithMask =
556                -bits(op2, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt);
557            DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize);
558            ''')
559    defineMicroRegOp('Ror', '''
560            uint8_t shiftAmt =
561                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
562            if(shiftAmt)
563            {
564                uint64_t top = psrc1 << (dataSize * 8 - shiftAmt);
565                uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
566                DestReg = merge(DestReg, top | bottom, dataSize);
567            }
568            else
569                DestReg = DestReg;
570            ''')
571    defineMicroRegOp('Rcr', '''
572            uint8_t shiftAmt =
573                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
574            if(shiftAmt)
575            {
576                CCFlagBits flags = ccFlagBits;
577                uint64_t top = flags.CF << (dataSize * 8 - shiftAmt);
578                if(shiftAmt > 1)
579                    top |= psrc1 << (dataSize * 8 - shiftAmt - 1);
580                uint64_t bottom = bits(psrc1, dataSize * 8, shiftAmt);
581                DestReg = merge(DestReg, top | bottom, dataSize);
582            }
583            else
584                DestReg = DestReg;
585            ''')
586    defineMicroRegOp('Rol', '''
587            uint8_t shiftAmt =
588                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
589            if(shiftAmt)
590            {
591                uint64_t top = psrc1 << shiftAmt;
592                uint64_t bottom =
593                    bits(psrc1, dataSize * 8 - 1, dataSize * 8 - shiftAmt);
594                DestReg = merge(DestReg, top | bottom, dataSize);
595            }
596            else
597                DestReg = DestReg;
598            ''')
599    defineMicroRegOp('Rcl', '''
600            uint8_t shiftAmt =
601                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
602            if(shiftAmt)
603            {
604                CCFlagBits flags = ccFlagBits;
605                uint64_t top = psrc1 << shiftAmt;
606                uint64_t bottom = flags.CF << (shiftAmt - 1);
607                if(shiftAmt > 1)
608                    bottom |=
609                        bits(psrc1, dataSize * 8 - 1,
610                                   dataSize * 8 - shiftAmt + 1);
611                DestReg = merge(DestReg, top | bottom, dataSize);
612            }
613            else
614                DestReg = DestReg;
615            ''')
616
617    defineMicroRegOpWr('Wrip', 'RIP = psrc1 + op2', elseCode="RIP = RIP;")
618    defineMicroRegOpWr('Wruflags', 'ccFlagBits = psrc1 ^ op2')
619
620    defineMicroRegOpRd('Rdip', 'DestReg = RIP')
621    defineMicroRegOpRd('Ruflags', 'DestReg = ccFlagBits')
622    defineMicroRegOpImm('Ruflag', 'DestReg = bits(ccFlagBits, imm8);', \
623            flagCode = genCCFlagBitsLogic)
624
625    defineMicroRegOpImm('Sext', '''
626            IntReg val = psrc1;
627            int sign_bit = bits(val, imm8-1, imm8-1);
628            val = sign_bit ? (val | ~mask(imm8)) : val;
629            DestReg = merge(DestReg, val, dataSize);''')
630
631    defineMicroRegOpImm('Zext', 'DestReg = bits(psrc1, imm8-1, 0);')
632}};
633