bit_scan.py revision 5414
15332Sgblack@eecs.umich.edu# Copyright (c) 2008 The Regents of The University of Michigan 25332Sgblack@eecs.umich.edu# All rights reserved. 35332Sgblack@eecs.umich.edu# 45332Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 55332Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 65332Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 75332Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 85332Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 95332Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 105332Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 115332Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 125332Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 135332Sgblack@eecs.umich.edu# this software without specific prior written permission. 145332Sgblack@eecs.umich.edu# 155332Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 165332Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 175332Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 185332Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 195332Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 205332Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 215332Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 225332Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 235332Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 245332Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 255332Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 265332Sgblack@eecs.umich.edu# 275332Sgblack@eecs.umich.edu# Authors: Gabe Black 285332Sgblack@eecs.umich.edu 295332Sgblack@eecs.umich.edu# Copyright (c) 2007-2008 The Hewlett-Packard Development Company 305081Sgblack@eecs.umich.edu# All rights reserved. 315081Sgblack@eecs.umich.edu# 325081Sgblack@eecs.umich.edu# Redistribution and use of this software in source and binary forms, 335081Sgblack@eecs.umich.edu# with or without modification, are permitted provided that the 345081Sgblack@eecs.umich.edu# following conditions are met: 355081Sgblack@eecs.umich.edu# 365081Sgblack@eecs.umich.edu# The software must be used only for Non-Commercial Use which means any 375081Sgblack@eecs.umich.edu# use which is NOT directed to receiving any direct monetary 385081Sgblack@eecs.umich.edu# compensation for, or commercial advantage from such use. Illustrative 395081Sgblack@eecs.umich.edu# examples of non-commercial use are academic research, personal study, 405081Sgblack@eecs.umich.edu# teaching, education and corporate research & development. 415081Sgblack@eecs.umich.edu# Illustrative examples of commercial use are distributing products for 425081Sgblack@eecs.umich.edu# commercial advantage and providing services using the software for 435081Sgblack@eecs.umich.edu# commercial advantage. 445081Sgblack@eecs.umich.edu# 455081Sgblack@eecs.umich.edu# If you wish to use this software or functionality therein that may be 465081Sgblack@eecs.umich.edu# covered by patents for commercial use, please contact: 475081Sgblack@eecs.umich.edu# Director of Intellectual Property Licensing 485081Sgblack@eecs.umich.edu# Office of Strategy and Technology 495081Sgblack@eecs.umich.edu# Hewlett-Packard Company 505081Sgblack@eecs.umich.edu# 1501 Page Mill Road 515081Sgblack@eecs.umich.edu# Palo Alto, California 94304 525081Sgblack@eecs.umich.edu# 535081Sgblack@eecs.umich.edu# Redistributions of source code must retain the above copyright notice, 545081Sgblack@eecs.umich.edu# this list of conditions and the following disclaimer. Redistributions 555081Sgblack@eecs.umich.edu# in binary form must reproduce the above copyright notice, this list of 565081Sgblack@eecs.umich.edu# conditions and the following disclaimer in the documentation and/or 575081Sgblack@eecs.umich.edu# other materials provided with the distribution. Neither the name of 585081Sgblack@eecs.umich.edu# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 595081Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 605081Sgblack@eecs.umich.edu# this software without specific prior written permission. No right of 615081Sgblack@eecs.umich.edu# sublicense is granted herewith. Derivatives of the software and 625081Sgblack@eecs.umich.edu# output created using the software may be prepared, but only for 635081Sgblack@eecs.umich.edu# Non-Commercial Uses. Derivatives of the software may be shared with 645081Sgblack@eecs.umich.edu# others provided: (i) the others agree to abide by the list of 655081Sgblack@eecs.umich.edu# conditions herein which includes the Non-Commercial Use restrictions; 665081Sgblack@eecs.umich.edu# and (ii) such Derivatives of the software include the above copyright 675081Sgblack@eecs.umich.edu# notice to acknowledge the contribution from this software where 685081Sgblack@eecs.umich.edu# applicable, this list of conditions and the disclaimer below. 695081Sgblack@eecs.umich.edu# 705081Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 715081Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 725081Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 735081Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 745081Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 755081Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 765081Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 775081Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 785081Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 795081Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 805081Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 815081Sgblack@eecs.umich.edu# 825081Sgblack@eecs.umich.edu# Authors: Gabe Black 835081Sgblack@eecs.umich.edu 845332Sgblack@eecs.umich.edumicrocode = ''' 855414Sgblack@eecs.umich.edudef macroop BSR_R_R { 865332Sgblack@eecs.umich.edu # Determine if the input was zero, and also move it to a temp reg. 875333Sgblack@eecs.umich.edu movi t1, t1, t0, dataSize=8 885332Sgblack@eecs.umich.edu and t1, regm, regm, flags=(ZF,) 895332Sgblack@eecs.umich.edu bri t0, label("end"), flags=(CZF,) 905332Sgblack@eecs.umich.edu 915332Sgblack@eecs.umich.edu # Zero out the result register 925332Sgblack@eecs.umich.edu movi reg, reg, 0x0 935332Sgblack@eecs.umich.edu 945332Sgblack@eecs.umich.edu # Bit 6 955333Sgblack@eecs.umich.edu srli t3, t1, 32, dataSize=8, flags=(EZF,) 965332Sgblack@eecs.umich.edu ori t4, reg, 0x20 975332Sgblack@eecs.umich.edu mov reg, reg, t4, flags=(nCEZF,) 985332Sgblack@eecs.umich.edu mov t1, t1, t3, flags=(nCEZF,) 995332Sgblack@eecs.umich.edu 1005332Sgblack@eecs.umich.edu # Bit 5 1015333Sgblack@eecs.umich.edu srli t3, t1, 16, dataSize=8, flags=(EZF,) 1025332Sgblack@eecs.umich.edu ori t4, reg, 0x10 1035332Sgblack@eecs.umich.edu mov reg, reg, t4, flags=(nCEZF,) 1045332Sgblack@eecs.umich.edu mov t1, t1, t3, flags=(nCEZF,) 1055332Sgblack@eecs.umich.edu 1065332Sgblack@eecs.umich.edu # Bit 4 1075333Sgblack@eecs.umich.edu srli t3, t1, 8, dataSize=8, flags=(EZF,) 1085332Sgblack@eecs.umich.edu ori t4, reg, 0x8 1095332Sgblack@eecs.umich.edu mov reg, reg, t4, flags=(nCEZF,) 1105332Sgblack@eecs.umich.edu mov t1, t1, t3, flags=(nCEZF,) 1115332Sgblack@eecs.umich.edu 1125332Sgblack@eecs.umich.edu # Bit 3 1135333Sgblack@eecs.umich.edu srli t3, t1, 4, dataSize=8, flags=(EZF,) 1145332Sgblack@eecs.umich.edu ori t4, reg, 0x4 1155332Sgblack@eecs.umich.edu mov reg, reg, t4, flags=(nCEZF,) 1165332Sgblack@eecs.umich.edu mov t1, t1, t3, flags=(nCEZF,) 1175332Sgblack@eecs.umich.edu 1185332Sgblack@eecs.umich.edu # Bit 2 1195333Sgblack@eecs.umich.edu srli t3, t1, 2, dataSize=8, flags=(EZF,) 1205332Sgblack@eecs.umich.edu ori t4, reg, 0x2 1215332Sgblack@eecs.umich.edu mov reg, reg, t4, flags=(nCEZF,) 1225332Sgblack@eecs.umich.edu mov t1, t1, t3, flags=(nCEZF,) 1235332Sgblack@eecs.umich.edu 1245332Sgblack@eecs.umich.edu # Bit 1 1255333Sgblack@eecs.umich.edu srli t3, t1, 1, dataSize=8, flags=(EZF,) 1265332Sgblack@eecs.umich.edu ori t4, reg, 0x1 1275332Sgblack@eecs.umich.edu mov reg, reg, t4, flags=(nCEZF,) 1285332Sgblack@eecs.umich.edu mov t1, t1, t3, flags=(nCEZF,) 1295332Sgblack@eecs.umich.edu 1305332Sgblack@eecs.umich.eduend: 1315332Sgblack@eecs.umich.edu fault "NoFault" 1325332Sgblack@eecs.umich.edu}; 1335332Sgblack@eecs.umich.edu 1345414Sgblack@eecs.umich.edudef macroop BSR_R_M { 1355332Sgblack@eecs.umich.edu 1365333Sgblack@eecs.umich.edu movi t1, t1, t0, dataSize=8 1375332Sgblack@eecs.umich.edu ld t1, seg, sib, disp 1385332Sgblack@eecs.umich.edu 1395332Sgblack@eecs.umich.edu # Determine if the input was zero, and also move it to a temp reg. 1405332Sgblack@eecs.umich.edu and t1, t1, t1, flags=(ZF,) 1415332Sgblack@eecs.umich.edu bri t0, label("end"), flags=(CZF,) 1425332Sgblack@eecs.umich.edu 1435332Sgblack@eecs.umich.edu # Zero out the result register 1445332Sgblack@eecs.umich.edu movi reg, reg, 0x0 1455332Sgblack@eecs.umich.edu 1465332Sgblack@eecs.umich.edu # Bit 6 1475333Sgblack@eecs.umich.edu srli t3, t1, 32, dataSize=8, flags=(EZF,) 1485332Sgblack@eecs.umich.edu ori t4, reg, 0x20 1495332Sgblack@eecs.umich.edu mov reg, reg, t4, flags=(nCEZF,) 1505332Sgblack@eecs.umich.edu mov t1, t1, t3, flags=(nCEZF,) 1515332Sgblack@eecs.umich.edu 1525332Sgblack@eecs.umich.edu # Bit 5 1535333Sgblack@eecs.umich.edu srli t3, t1, 16, dataSize=8, flags=(EZF,) 1545332Sgblack@eecs.umich.edu ori t4, reg, 0x10 1555332Sgblack@eecs.umich.edu mov reg, reg, t4, flags=(nCEZF,) 1565332Sgblack@eecs.umich.edu mov t1, t1, t3, flags=(nCEZF,) 1575332Sgblack@eecs.umich.edu 1585332Sgblack@eecs.umich.edu # Bit 4 1595333Sgblack@eecs.umich.edu srli t3, t1, 8, dataSize=8, flags=(EZF,) 1605332Sgblack@eecs.umich.edu ori t4, reg, 0x8 1615332Sgblack@eecs.umich.edu mov reg, reg, t4, flags=(nCEZF,) 1625332Sgblack@eecs.umich.edu mov t1, t1, t3, flags=(nCEZF,) 1635332Sgblack@eecs.umich.edu 1645332Sgblack@eecs.umich.edu # Bit 3 1655333Sgblack@eecs.umich.edu srli t3, t1, 4, dataSize=8, flags=(EZF,) 1665332Sgblack@eecs.umich.edu ori t4, reg, 0x4 1675332Sgblack@eecs.umich.edu mov reg, reg, t4, flags=(nCEZF,) 1685332Sgblack@eecs.umich.edu mov t1, t1, t3, flags=(nCEZF,) 1695332Sgblack@eecs.umich.edu 1705332Sgblack@eecs.umich.edu # Bit 2 1715333Sgblack@eecs.umich.edu srli t3, t1, 2, dataSize=8, flags=(EZF,) 1725332Sgblack@eecs.umich.edu ori t4, reg, 0x2 1735332Sgblack@eecs.umich.edu mov reg, reg, t4, flags=(nCEZF,) 1745332Sgblack@eecs.umich.edu mov t1, t1, t3, flags=(nCEZF,) 1755332Sgblack@eecs.umich.edu 1765332Sgblack@eecs.umich.edu # Bit 1 1775333Sgblack@eecs.umich.edu srli t3, t1, 1, dataSize=8, flags=(EZF,) 1785332Sgblack@eecs.umich.edu ori t4, reg, 0x1 1795332Sgblack@eecs.umich.edu mov reg, reg, t4, flags=(nCEZF,) 1805332Sgblack@eecs.umich.edu mov t1, t1, t3, flags=(nCEZF,) 1815332Sgblack@eecs.umich.edu 1825332Sgblack@eecs.umich.eduend: 1835332Sgblack@eecs.umich.edu fault "NoFault" 1845332Sgblack@eecs.umich.edu}; 1855332Sgblack@eecs.umich.edu 1865414Sgblack@eecs.umich.edudef macroop BSR_R_P { 1875332Sgblack@eecs.umich.edu 1885332Sgblack@eecs.umich.edu rdip t7 1895333Sgblack@eecs.umich.edu movi t1, t1, t0, dataSize=8 1905332Sgblack@eecs.umich.edu ld t1, seg, riprel, disp 1915332Sgblack@eecs.umich.edu 1925332Sgblack@eecs.umich.edu # Determine if the input was zero, and also move it to a temp reg. 1935332Sgblack@eecs.umich.edu and t1, t1, t1, flags=(ZF,) 1945332Sgblack@eecs.umich.edu bri t0, label("end"), flags=(CZF,) 1955332Sgblack@eecs.umich.edu 1965332Sgblack@eecs.umich.edu # Zero out the result register 1975332Sgblack@eecs.umich.edu movi reg, reg, 0x0 1985332Sgblack@eecs.umich.edu 1995332Sgblack@eecs.umich.edu # Bit 6 2005333Sgblack@eecs.umich.edu srli t3, t1, 32, dataSize=8, flags=(EZF,) 2015332Sgblack@eecs.umich.edu ori t4, reg, 0x20 2025332Sgblack@eecs.umich.edu mov reg, reg, t4, flags=(nCEZF,) 2035332Sgblack@eecs.umich.edu mov t1, t1, t3, flags=(nCEZF,) 2045332Sgblack@eecs.umich.edu 2055332Sgblack@eecs.umich.edu # Bit 5 2065333Sgblack@eecs.umich.edu srli t3, t1, 16, dataSize=8, flags=(EZF,) 2075332Sgblack@eecs.umich.edu ori t4, reg, 0x10 2085332Sgblack@eecs.umich.edu mov reg, reg, t4, flags=(nCEZF,) 2095332Sgblack@eecs.umich.edu mov t1, t1, t3, flags=(nCEZF,) 2105332Sgblack@eecs.umich.edu 2115332Sgblack@eecs.umich.edu # Bit 4 2125333Sgblack@eecs.umich.edu srli t3, t1, 8, dataSize=8, flags=(EZF,) 2135332Sgblack@eecs.umich.edu ori t4, reg, 0x8 2145332Sgblack@eecs.umich.edu mov reg, reg, t4, flags=(nCEZF,) 2155332Sgblack@eecs.umich.edu mov t1, t1, t3, flags=(nCEZF,) 2165332Sgblack@eecs.umich.edu 2175332Sgblack@eecs.umich.edu # Bit 3 2185333Sgblack@eecs.umich.edu srli t3, t1, 4, dataSize=8, flags=(EZF,) 2195332Sgblack@eecs.umich.edu ori t4, reg, 0x4 2205332Sgblack@eecs.umich.edu mov reg, reg, t4, flags=(nCEZF,) 2215332Sgblack@eecs.umich.edu mov t1, t1, t3, flags=(nCEZF,) 2225332Sgblack@eecs.umich.edu 2235332Sgblack@eecs.umich.edu # Bit 2 2245333Sgblack@eecs.umich.edu srli t3, t1, 2, dataSize=8, flags=(EZF,) 2255332Sgblack@eecs.umich.edu ori t4, reg, 0x2 2265332Sgblack@eecs.umich.edu mov reg, reg, t4, flags=(nCEZF,) 2275332Sgblack@eecs.umich.edu mov t1, t1, t3, flags=(nCEZF,) 2285332Sgblack@eecs.umich.edu 2295332Sgblack@eecs.umich.edu # Bit 1 2305333Sgblack@eecs.umich.edu srli t3, t1, 1, dataSize=8, flags=(EZF,) 2315332Sgblack@eecs.umich.edu ori t4, reg, 0x1 2325332Sgblack@eecs.umich.edu mov reg, reg, t4, flags=(nCEZF,) 2335332Sgblack@eecs.umich.edu mov t1, t1, t3, flags=(nCEZF,) 2345332Sgblack@eecs.umich.edu 2355332Sgblack@eecs.umich.eduend: 2365332Sgblack@eecs.umich.edu fault "NoFault" 2375332Sgblack@eecs.umich.edu}; 2385332Sgblack@eecs.umich.edu 2395414Sgblack@eecs.umich.edudef macroop BSF_R_R { 2405332Sgblack@eecs.umich.edu # Determine if the input was zero, and also move it to a temp reg. 2415333Sgblack@eecs.umich.edu mov t1, t1, t0, dataSize=8 2425332Sgblack@eecs.umich.edu and t1, regm, regm, flags=(ZF,) 2435332Sgblack@eecs.umich.edu bri t0, label("end"), flags=(CZF,) 2445332Sgblack@eecs.umich.edu 2455332Sgblack@eecs.umich.edu # Zero out the result register 2465332Sgblack@eecs.umich.edu movi reg, reg, 0 2475332Sgblack@eecs.umich.edu 2485333Sgblack@eecs.umich.edu subi t2, t1, 1 2495333Sgblack@eecs.umich.edu xor t1, t2, t1 2505333Sgblack@eecs.umich.edu 2515332Sgblack@eecs.umich.edu # Bit 6 2525333Sgblack@eecs.umich.edu srli t3, t1, 32, dataSize=8 2535333Sgblack@eecs.umich.edu andi t3, t3, 32 2545333Sgblack@eecs.umich.edu or reg, reg, t3 2555332Sgblack@eecs.umich.edu 2565332Sgblack@eecs.umich.edu # Bit 5 2575333Sgblack@eecs.umich.edu srli t3, t1, 16, dataSize=8 2585333Sgblack@eecs.umich.edu andi t3, t3, 16 2595333Sgblack@eecs.umich.edu or reg, reg, t3 2605332Sgblack@eecs.umich.edu 2615332Sgblack@eecs.umich.edu # Bit 4 2625333Sgblack@eecs.umich.edu srli t3, t1, 8, dataSize=8 2635333Sgblack@eecs.umich.edu andi t3, t3, 8 2645333Sgblack@eecs.umich.edu or reg, reg, t3 2655332Sgblack@eecs.umich.edu 2665332Sgblack@eecs.umich.edu # Bit 3 2675333Sgblack@eecs.umich.edu srli t3, t1, 4, dataSize=8 2685333Sgblack@eecs.umich.edu andi t3, t3, 4 2695333Sgblack@eecs.umich.edu or reg, reg, t3 2705332Sgblack@eecs.umich.edu 2715332Sgblack@eecs.umich.edu # Bit 2 2725333Sgblack@eecs.umich.edu srli t3, t1, 2, dataSize=8 2735333Sgblack@eecs.umich.edu andi t3, t3, 2 2745333Sgblack@eecs.umich.edu or reg, reg, t3 2755332Sgblack@eecs.umich.edu 2765332Sgblack@eecs.umich.edu # Bit 1 2775333Sgblack@eecs.umich.edu srli t3, t1, 1, dataSize=8 2785333Sgblack@eecs.umich.edu andi t3, t3, 1 2795333Sgblack@eecs.umich.edu or reg, reg, t3 2805332Sgblack@eecs.umich.edu 2815332Sgblack@eecs.umich.eduend: 2825332Sgblack@eecs.umich.edu fault "NoFault" 2835332Sgblack@eecs.umich.edu}; 2845332Sgblack@eecs.umich.edu 2855414Sgblack@eecs.umich.edudef macroop BSF_R_M { 2865332Sgblack@eecs.umich.edu 2875333Sgblack@eecs.umich.edu mov t1, t1, t0, dataSize=8 2885332Sgblack@eecs.umich.edu ld t1, seg, sib, disp 2895332Sgblack@eecs.umich.edu 2905332Sgblack@eecs.umich.edu # Determine if the input was zero, and also move it to a temp reg. 2915332Sgblack@eecs.umich.edu and t1, t1, t1, flags=(ZF,) 2925332Sgblack@eecs.umich.edu bri t0, label("end"), flags=(CZF,) 2935332Sgblack@eecs.umich.edu 2945332Sgblack@eecs.umich.edu # Zero out the result register 2955332Sgblack@eecs.umich.edu mov reg, reg, t0 2965332Sgblack@eecs.umich.edu 2975333Sgblack@eecs.umich.edu subi t2, t1, 1 2985333Sgblack@eecs.umich.edu xor t1, t2, t1 2995333Sgblack@eecs.umich.edu 3005332Sgblack@eecs.umich.edu # Bit 6 3015333Sgblack@eecs.umich.edu srli t3, t1, 32, dataSize=8 3025333Sgblack@eecs.umich.edu andi t3, t3, 32 3035333Sgblack@eecs.umich.edu or reg, reg, t3 3045332Sgblack@eecs.umich.edu 3055332Sgblack@eecs.umich.edu # Bit 5 3065333Sgblack@eecs.umich.edu srli t3, t1, 16, dataSize=8 3075333Sgblack@eecs.umich.edu andi t3, t3, 16 3085333Sgblack@eecs.umich.edu or reg, reg, t3 3095332Sgblack@eecs.umich.edu 3105332Sgblack@eecs.umich.edu # Bit 4 3115333Sgblack@eecs.umich.edu srli t3, t1, 8, dataSize=8 3125333Sgblack@eecs.umich.edu andi t3, t3, 8 3135333Sgblack@eecs.umich.edu or reg, reg, t3 3145332Sgblack@eecs.umich.edu 3155332Sgblack@eecs.umich.edu # Bit 3 3165333Sgblack@eecs.umich.edu srli t3, t1, 4, dataSize=8 3175333Sgblack@eecs.umich.edu andi t3, t3, 4 3185333Sgblack@eecs.umich.edu or reg, reg, t3 3195332Sgblack@eecs.umich.edu 3205332Sgblack@eecs.umich.edu # Bit 2 3215333Sgblack@eecs.umich.edu srli t3, t1, 2, dataSize=8 3225333Sgblack@eecs.umich.edu andi t3, t3, 2 3235333Sgblack@eecs.umich.edu or reg, reg, t3 3245332Sgblack@eecs.umich.edu 3255332Sgblack@eecs.umich.edu # Bit 1 3265333Sgblack@eecs.umich.edu srli t3, t1, 1, dataSize=8 3275333Sgblack@eecs.umich.edu andi t3, t3, 1 3285333Sgblack@eecs.umich.edu or reg, reg, t3 3295332Sgblack@eecs.umich.edu 3305332Sgblack@eecs.umich.eduend: 3315332Sgblack@eecs.umich.edu fault "NoFault" 3325332Sgblack@eecs.umich.edu}; 3335332Sgblack@eecs.umich.edu 3345414Sgblack@eecs.umich.edudef macroop BSF_R_P { 3355332Sgblack@eecs.umich.edu 3365332Sgblack@eecs.umich.edu rdip t7 3375333Sgblack@eecs.umich.edu mov t1, t1, t0, dataSize=8 3385332Sgblack@eecs.umich.edu ld t1, seg, riprel, disp 3395332Sgblack@eecs.umich.edu 3405332Sgblack@eecs.umich.edu # Determine if the input was zero, and also move it to a temp reg. 3415332Sgblack@eecs.umich.edu and t1, t1, t1, flags=(ZF,) 3425332Sgblack@eecs.umich.edu bri t0, label("end"), flags=(CZF,) 3435332Sgblack@eecs.umich.edu 3445332Sgblack@eecs.umich.edu # Zero out the result register 3455332Sgblack@eecs.umich.edu mov reg, reg, t0 3465332Sgblack@eecs.umich.edu 3475333Sgblack@eecs.umich.edu subi t2, t1, 1 3485333Sgblack@eecs.umich.edu xor t1, t2, t1 3495333Sgblack@eecs.umich.edu 3505332Sgblack@eecs.umich.edu # Bit 6 3515333Sgblack@eecs.umich.edu srli t3, t1, 32, dataSize=8 3525333Sgblack@eecs.umich.edu andi t3, t3, 32 3535333Sgblack@eecs.umich.edu or reg, reg, t3 3545332Sgblack@eecs.umich.edu 3555332Sgblack@eecs.umich.edu # Bit 5 3565333Sgblack@eecs.umich.edu srli t3, t1, 16, dataSize=8 3575333Sgblack@eecs.umich.edu andi t3, t3, 16 3585333Sgblack@eecs.umich.edu or reg, reg, t3 3595332Sgblack@eecs.umich.edu 3605332Sgblack@eecs.umich.edu # Bit 4 3615333Sgblack@eecs.umich.edu srli t3, t1, 8, dataSize=8 3625333Sgblack@eecs.umich.edu andi t3, t3, 8 3635333Sgblack@eecs.umich.edu or reg, reg, t3 3645332Sgblack@eecs.umich.edu 3655332Sgblack@eecs.umich.edu # Bit 3 3665333Sgblack@eecs.umich.edu srli t3, t1, 4, dataSize=8 3675333Sgblack@eecs.umich.edu andi t3, t3, 4 3685333Sgblack@eecs.umich.edu or reg, reg, t3 3695332Sgblack@eecs.umich.edu 3705332Sgblack@eecs.umich.edu # Bit 2 3715333Sgblack@eecs.umich.edu srli t3, t1, 2, dataSize=8 3725333Sgblack@eecs.umich.edu andi t3, t3, 2 3735333Sgblack@eecs.umich.edu or reg, reg, t3 3745332Sgblack@eecs.umich.edu 3755332Sgblack@eecs.umich.edu # Bit 1 3765333Sgblack@eecs.umich.edu srli t3, t1, 1, dataSize=8 3775333Sgblack@eecs.umich.edu andi t3, t3, 1 3785333Sgblack@eecs.umich.edu or reg, reg, t3 3795332Sgblack@eecs.umich.edu 3805332Sgblack@eecs.umich.eduend: 3815332Sgblack@eecs.umich.edu fault "NoFault" 3825332Sgblack@eecs.umich.edu}; 3835332Sgblack@eecs.umich.edu''' 384