interrupts.hh revision 9554:406fbcf60223 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007 The Hewlett-Packard Development Company
15 * All rights reserved.
16 *
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder.  You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
25 *
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions are
28 * met: redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer;
30 * redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in the
32 * documentation and/or other materials provided with the distribution;
33 * neither the name of the copyright holders nor the names of its
34 * contributors may be used to endorse or promote products derived from
35 * this software without specific prior written permission.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 *
49 * Authors: Gabe Black
50 *          Andreas Hansson
51 */
52
53#ifndef __ARCH_X86_INTERRUPTS_HH__
54#define __ARCH_X86_INTERRUPTS_HH__
55
56#include "arch/x86/regs/apic.hh"
57#include "arch/x86/faults.hh"
58#include "arch/x86/intmessage.hh"
59#include "base/bitfield.hh"
60#include "cpu/thread_context.hh"
61#include "dev/x86/intdev.hh"
62#include "dev/io_device.hh"
63#include "params/X86LocalApic.hh"
64#include "sim/eventq.hh"
65
66class ThreadContext;
67class BaseCPU;
68
69int divideFromConf(uint32_t conf);
70
71namespace X86ISA {
72
73ApicRegIndex decodeAddr(Addr paddr);
74
75class Interrupts : public BasicPioDevice, IntDev
76{
77  protected:
78    // Storage for the APIC registers
79    uint32_t regs[NUM_APIC_REGS];
80
81    BitUnion32(LVTEntry)
82        Bitfield<7, 0> vector;
83        Bitfield<10, 8> deliveryMode;
84        Bitfield<12> status;
85        Bitfield<13> polarity;
86        Bitfield<14> remoteIRR;
87        Bitfield<15> trigger;
88        Bitfield<16> masked;
89        Bitfield<17> periodic;
90    EndBitUnion(LVTEntry)
91
92    /*
93     * Timing related stuff.
94     */
95    Tick latency;
96
97    class ApicTimerEvent : public Event
98    {
99      private:
100        Interrupts *localApic;
101      public:
102        ApicTimerEvent(Interrupts *_localApic) :
103            Event(), localApic(_localApic)
104        {}
105
106        void process()
107        {
108            assert(localApic);
109            if (localApic->triggerTimerInterrupt()) {
110                localApic->setReg(APIC_INITIAL_COUNT,
111                        localApic->readReg(APIC_INITIAL_COUNT));
112            }
113        }
114    };
115
116    ApicTimerEvent apicTimerEvent;
117
118    /*
119     * A set of variables to keep track of interrupts that don't go through
120     * the IRR.
121     */
122    bool pendingSmi;
123    uint8_t smiVector;
124    bool pendingNmi;
125    uint8_t nmiVector;
126    bool pendingExtInt;
127    uint8_t extIntVector;
128    bool pendingInit;
129    uint8_t initVector;
130    bool pendingStartup;
131    uint8_t startupVector;
132    bool startedUp;
133
134    // This is a quick check whether any of the above (except ExtInt) are set.
135    bool pendingUnmaskableInt;
136
137    // A count of how many IPIs are in flight.
138    int pendingIPIs;
139
140    /*
141     * IRR and ISR maintenance.
142     */
143    uint8_t IRRV;
144    uint8_t ISRV;
145
146    int
147    findRegArrayMSB(ApicRegIndex base)
148    {
149        int offset = 7;
150        do {
151            if (regs[base + offset] != 0) {
152                return offset * 32 + findMsbSet(regs[base + offset]);
153            }
154        } while (offset--);
155        return 0;
156    }
157
158    void
159    updateIRRV()
160    {
161        IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
162    }
163
164    void
165    updateISRV()
166    {
167        ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
168    }
169
170    void
171    setRegArrayBit(ApicRegIndex base, uint8_t vector)
172    {
173        regs[base + (vector / 32)] |= (1 << (vector % 32));
174    }
175
176    void
177    clearRegArrayBit(ApicRegIndex base, uint8_t vector)
178    {
179        regs[base + (vector / 32)] &= ~(1 << (vector % 32));
180    }
181
182    bool
183    getRegArrayBit(ApicRegIndex base, uint8_t vector)
184    {
185        return bits(regs[base + (vector / 32)], vector % 5);
186    }
187
188    void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
189
190    BaseCPU *cpu;
191
192    int initialApicId;
193
194    // Port for receiving interrupts
195    IntSlavePort intSlavePort;
196
197  public:
198
199    int getInitialApicId() { return initialApicId; }
200
201    /*
202     * Params stuff.
203     */
204    typedef X86LocalApicParams Params;
205
206    void setCPU(BaseCPU * newCPU);
207
208    const Params *
209    params() const
210    {
211        return dynamic_cast<const Params *>(_params);
212    }
213
214    /*
215     * Initialize this object by registering it with the IO APIC.
216     */
217    void init();
218
219    /*
220     * Functions to interact with the interrupt port from IntDev.
221     */
222    Tick read(PacketPtr pkt);
223    Tick write(PacketPtr pkt);
224    Tick recvMessage(PacketPtr pkt);
225    Tick recvResponse(PacketPtr pkt);
226
227    bool
228    triggerTimerInterrupt()
229    {
230        LVTEntry entry = regs[APIC_LVT_TIMER];
231        if (!entry.masked)
232            requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
233        return entry.periodic;
234    }
235
236    AddrRangeList getAddrRanges() const;
237    AddrRangeList getIntAddrRange() const;
238
239    BaseMasterPort &getMasterPort(const std::string &if_name,
240                                  PortID idx = InvalidPortID)
241    {
242        if (if_name == "int_master") {
243            return intMasterPort;
244        }
245        return BasicPioDevice::getMasterPort(if_name, idx);
246    }
247
248    BaseSlavePort &getSlavePort(const std::string &if_name,
249                                PortID idx = InvalidPortID)
250    {
251        if (if_name == "int_slave") {
252            return intSlavePort;
253        }
254        return BasicPioDevice::getSlavePort(if_name, idx);
255    }
256
257    /*
258     * Functions to access and manipulate the APIC's registers.
259     */
260
261    uint32_t readReg(ApicRegIndex miscReg);
262    void setReg(ApicRegIndex reg, uint32_t val);
263    void
264    setRegNoEffect(ApicRegIndex reg, uint32_t val)
265    {
266        regs[reg] = val;
267    }
268
269    /*
270     * Constructor.
271     */
272
273    Interrupts(Params * p);
274
275    /*
276     * Functions for retrieving interrupts for the CPU to handle.
277     */
278
279    bool checkInterrupts(ThreadContext *tc) const;
280    Fault getInterrupt(ThreadContext *tc);
281    void updateIntrInfo(ThreadContext *tc);
282
283    /*
284     * Serialization.
285     */
286
287    virtual void serialize(std::ostream &os);
288    virtual void unserialize(Checkpoint *cp, const std::string &section);
289
290    /*
291     * Old functions needed for compatability but which will be phased out
292     * eventually.
293     */
294    void
295    post(int int_num, int index)
296    {
297        panic("Interrupts::post unimplemented!\n");
298    }
299
300    void
301    clear(int int_num, int index)
302    {
303        panic("Interrupts::clear unimplemented!\n");
304    }
305
306    void
307    clearAll()
308    {
309        panic("Interrupts::clearAll unimplemented!\n");
310    }
311};
312
313} // namespace X86ISA
314
315#endif // __ARCH_X86_INTERRUPTS_HH__
316