interrupts.hh revision 9294 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007 The Hewlett-Packard Development Company
15 * All rights reserved.
16 *
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder.  You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
25 *
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions are
28 * met: redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer;
30 * redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in the
32 * documentation and/or other materials provided with the distribution;
33 * neither the name of the copyright holders nor the names of its
34 * contributors may be used to endorse or promote products derived from
35 * this software without specific prior written permission.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 *
49 * Authors: Gabe Black
50 *          Andreas Hansson
51 */
52
53#ifndef __ARCH_X86_INTERRUPTS_HH__
54#define __ARCH_X86_INTERRUPTS_HH__
55
56#include "arch/x86/regs/apic.hh"
57#include "arch/x86/faults.hh"
58#include "arch/x86/intmessage.hh"
59#include "base/bitfield.hh"
60#include "cpu/thread_context.hh"
61#include "dev/x86/intdev.hh"
62#include "dev/io_device.hh"
63#include "params/X86LocalApic.hh"
64#include "sim/eventq.hh"
65
66class ThreadContext;
67class BaseCPU;
68
69namespace X86ISA {
70
71class Interrupts : public BasicPioDevice, IntDev
72{
73  protected:
74    // Storage for the APIC registers
75    uint32_t regs[NUM_APIC_REGS];
76
77    BitUnion32(LVTEntry)
78        Bitfield<7, 0> vector;
79        Bitfield<10, 8> deliveryMode;
80        Bitfield<12> status;
81        Bitfield<13> polarity;
82        Bitfield<14> remoteIRR;
83        Bitfield<15> trigger;
84        Bitfield<16> masked;
85        Bitfield<17> periodic;
86    EndBitUnion(LVTEntry)
87
88    /*
89     * Timing related stuff.
90     */
91    Tick latency;
92
93    class ApicTimerEvent : public Event
94    {
95      private:
96        Interrupts *localApic;
97      public:
98        ApicTimerEvent(Interrupts *_localApic) :
99            Event(), localApic(_localApic)
100        {}
101
102        void process()
103        {
104            assert(localApic);
105            if (localApic->triggerTimerInterrupt()) {
106                localApic->setReg(APIC_INITIAL_COUNT,
107                        localApic->readReg(APIC_INITIAL_COUNT));
108            }
109        }
110    };
111
112    ApicTimerEvent apicTimerEvent;
113
114    /*
115     * A set of variables to keep track of interrupts that don't go through
116     * the IRR.
117     */
118    bool pendingSmi;
119    uint8_t smiVector;
120    bool pendingNmi;
121    uint8_t nmiVector;
122    bool pendingExtInt;
123    uint8_t extIntVector;
124    bool pendingInit;
125    uint8_t initVector;
126    bool pendingStartup;
127    uint8_t startupVector;
128    bool startedUp;
129
130    // This is a quick check whether any of the above (except ExtInt) are set.
131    bool pendingUnmaskableInt;
132
133    // A count of how many IPIs are in flight.
134    int pendingIPIs;
135
136    /*
137     * IRR and ISR maintenance.
138     */
139    uint8_t IRRV;
140    uint8_t ISRV;
141
142    int
143    findRegArrayMSB(ApicRegIndex base)
144    {
145        int offset = 7;
146        do {
147            if (regs[base + offset] != 0) {
148                return offset * 32 + findMsbSet(regs[base + offset]);
149            }
150        } while (offset--);
151        return 0;
152    }
153
154    void
155    updateIRRV()
156    {
157        IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
158    }
159
160    void
161    updateISRV()
162    {
163        ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
164    }
165
166    void
167    setRegArrayBit(ApicRegIndex base, uint8_t vector)
168    {
169        regs[base + (vector / 32)] |= (1 << (vector % 32));
170    }
171
172    void
173    clearRegArrayBit(ApicRegIndex base, uint8_t vector)
174    {
175        regs[base + (vector / 32)] &= ~(1 << (vector % 32));
176    }
177
178    bool
179    getRegArrayBit(ApicRegIndex base, uint8_t vector)
180    {
181        return bits(regs[base + (vector / 32)], vector % 5);
182    }
183
184    void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
185
186    BaseCPU *cpu;
187
188    int initialApicId;
189
190    // Port for receiving interrupts
191    IntSlavePort intSlavePort;
192
193  public:
194
195    int getInitialApicId() { return initialApicId; }
196
197    /*
198     * Params stuff.
199     */
200    typedef X86LocalApicParams Params;
201
202    void setCPU(BaseCPU * newCPU);
203
204    void
205    setClock(Tick newClock)
206    {
207        clock = newClock;
208    }
209
210    const Params *
211    params() const
212    {
213        return dynamic_cast<const Params *>(_params);
214    }
215
216    /*
217     * Initialize this object by registering it with the IO APIC.
218     */
219    void init();
220
221    /*
222     * Functions to interact with the interrupt port from IntDev.
223     */
224    Tick read(PacketPtr pkt);
225    Tick write(PacketPtr pkt);
226    Tick recvMessage(PacketPtr pkt);
227    Tick recvResponse(PacketPtr pkt);
228
229    bool
230    triggerTimerInterrupt()
231    {
232        LVTEntry entry = regs[APIC_LVT_TIMER];
233        if (!entry.masked)
234            requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
235        return entry.periodic;
236    }
237
238    AddrRangeList getAddrRanges() const;
239    AddrRangeList getIntAddrRange() const;
240
241    BaseMasterPort &getMasterPort(const std::string &if_name,
242                                  PortID idx = InvalidPortID)
243    {
244        if (if_name == "int_master") {
245            return intMasterPort;
246        }
247        return BasicPioDevice::getMasterPort(if_name, idx);
248    }
249
250    BaseSlavePort &getSlavePort(const std::string &if_name,
251                                PortID idx = InvalidPortID)
252    {
253        if (if_name == "int_slave") {
254            return intSlavePort;
255        }
256        return BasicPioDevice::getSlavePort(if_name, idx);
257    }
258
259    /*
260     * Functions to access and manipulate the APIC's registers.
261     */
262
263    uint32_t readReg(ApicRegIndex miscReg);
264    void setReg(ApicRegIndex reg, uint32_t val);
265    void
266    setRegNoEffect(ApicRegIndex reg, uint32_t val)
267    {
268        regs[reg] = val;
269    }
270
271    /*
272     * Constructor.
273     */
274
275    Interrupts(Params * p);
276
277    /*
278     * Functions for retrieving interrupts for the CPU to handle.
279     */
280
281    bool checkInterrupts(ThreadContext *tc) const;
282    Fault getInterrupt(ThreadContext *tc);
283    void updateIntrInfo(ThreadContext *tc);
284
285    /*
286     * Serialization.
287     */
288
289    virtual void serialize(std::ostream &os);
290    virtual void unserialize(Checkpoint *cp, const std::string &section);
291
292    /*
293     * Old functions needed for compatability but which will be phased out
294     * eventually.
295     */
296    void
297    post(int int_num, int index)
298    {
299        panic("Interrupts::post unimplemented!\n");
300    }
301
302    void
303    clear(int int_num, int index)
304    {
305        panic("Interrupts::clear unimplemented!\n");
306    }
307
308    void
309    clearAll()
310    {
311        panic("Interrupts::clearAll unimplemented!\n");
312    }
313};
314
315} // namespace X86ISA
316
317#endif // __ARCH_X86_INTERRUPTS_HH__
318