interrupts.hh revision 8799:dac1e33e07b0 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_X86_INTERRUPTS_HH__
41#define __ARCH_X86_INTERRUPTS_HH__
42
43#include "arch/x86/regs/apic.hh"
44#include "arch/x86/faults.hh"
45#include "arch/x86/intmessage.hh"
46#include "base/bitfield.hh"
47#include "cpu/thread_context.hh"
48#include "dev/x86/intdev.hh"
49#include "dev/io_device.hh"
50#include "params/X86LocalApic.hh"
51#include "sim/eventq.hh"
52
53class ThreadContext;
54class BaseCPU;
55
56namespace X86ISA {
57
58class Interrupts : public BasicPioDevice, IntDev
59{
60  protected:
61    // Storage for the APIC registers
62    uint32_t regs[NUM_APIC_REGS];
63
64    BitUnion32(LVTEntry)
65        Bitfield<7, 0> vector;
66        Bitfield<10, 8> deliveryMode;
67        Bitfield<12> status;
68        Bitfield<13> polarity;
69        Bitfield<14> remoteIRR;
70        Bitfield<15> trigger;
71        Bitfield<16> masked;
72        Bitfield<17> periodic;
73    EndBitUnion(LVTEntry)
74
75    /*
76     * Timing related stuff.
77     */
78    Tick latency;
79    Tick clock;
80
81    class ApicTimerEvent : public Event
82    {
83      private:
84        Interrupts *localApic;
85      public:
86        ApicTimerEvent(Interrupts *_localApic) :
87            Event(), localApic(_localApic)
88        {}
89
90        void process()
91        {
92            assert(localApic);
93            if (localApic->triggerTimerInterrupt()) {
94                localApic->setReg(APIC_INITIAL_COUNT,
95                        localApic->readReg(APIC_INITIAL_COUNT));
96            }
97        }
98    };
99
100    ApicTimerEvent apicTimerEvent;
101
102    /*
103     * A set of variables to keep track of interrupts that don't go through
104     * the IRR.
105     */
106    bool pendingSmi;
107    uint8_t smiVector;
108    bool pendingNmi;
109    uint8_t nmiVector;
110    bool pendingExtInt;
111    uint8_t extIntVector;
112    bool pendingInit;
113    uint8_t initVector;
114    bool pendingStartup;
115    uint8_t startupVector;
116    bool startedUp;
117
118    // This is a quick check whether any of the above (except ExtInt) are set.
119    bool pendingUnmaskableInt;
120
121    // A count of how many IPIs are in flight.
122    int pendingIPIs;
123
124    /*
125     * IRR and ISR maintenance.
126     */
127    uint8_t IRRV;
128    uint8_t ISRV;
129
130    int
131    findRegArrayMSB(ApicRegIndex base)
132    {
133        int offset = 7;
134        do {
135            if (regs[base + offset] != 0) {
136                return offset * 32 + findMsbSet(regs[base + offset]);
137            }
138        } while (offset--);
139        return 0;
140    }
141
142    void
143    updateIRRV()
144    {
145        IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
146    }
147
148    void
149    updateISRV()
150    {
151        ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
152    }
153
154    void
155    setRegArrayBit(ApicRegIndex base, uint8_t vector)
156    {
157        regs[base + (vector / 32)] |= (1 << (vector % 32));
158    }
159
160    void
161    clearRegArrayBit(ApicRegIndex base, uint8_t vector)
162    {
163        regs[base + (vector / 32)] &= ~(1 << (vector % 32));
164    }
165
166    bool
167    getRegArrayBit(ApicRegIndex base, uint8_t vector)
168    {
169        return bits(regs[base + (vector / 32)], vector % 5);
170    }
171
172    void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
173
174    BaseCPU *cpu;
175
176    int initialApicId;
177
178  public:
179
180    int getInitialApicId() { return initialApicId; }
181
182    /*
183     * Params stuff.
184     */
185    typedef X86LocalApicParams Params;
186
187    void setCPU(BaseCPU * newCPU);
188
189    void
190    setClock(Tick newClock)
191    {
192        clock = newClock;
193    }
194
195    const Params *
196    params() const
197    {
198        return dynamic_cast<const Params *>(_params);
199    }
200
201    /*
202     * Initialize this object by registering it with the IO APIC.
203     */
204    void init();
205
206    /*
207     * Functions to interact with the interrupt port from IntDev.
208     */
209    Tick read(PacketPtr pkt);
210    Tick write(PacketPtr pkt);
211    Tick recvMessage(PacketPtr pkt);
212    Tick recvResponse(PacketPtr pkt);
213
214    bool
215    triggerTimerInterrupt()
216    {
217        LVTEntry entry = regs[APIC_LVT_TIMER];
218        if (!entry.masked)
219            requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
220        return entry.periodic;
221    }
222
223    AddrRangeList getAddrRanges();
224    AddrRangeList getIntAddrRange();
225
226    Port *getPort(const std::string &if_name, int idx = -1)
227    {
228        if (if_name == "int_port")
229            return intPort;
230        return BasicPioDevice::getPort(if_name, idx);
231    }
232
233    /*
234     * Functions to access and manipulate the APIC's registers.
235     */
236
237    uint32_t readReg(ApicRegIndex miscReg);
238    void setReg(ApicRegIndex reg, uint32_t val);
239    void
240    setRegNoEffect(ApicRegIndex reg, uint32_t val)
241    {
242        regs[reg] = val;
243    }
244
245    /*
246     * Constructor.
247     */
248
249    Interrupts(Params * p);
250
251    /*
252     * Functions for retrieving interrupts for the CPU to handle.
253     */
254
255    bool checkInterrupts(ThreadContext *tc) const;
256    Fault getInterrupt(ThreadContext *tc);
257    void updateIntrInfo(ThreadContext *tc);
258
259    /*
260     * Serialization.
261     */
262
263    virtual void serialize(std::ostream &os);
264    virtual void unserialize(Checkpoint *cp, const std::string &section);
265
266    /*
267     * Old functions needed for compatability but which will be phased out
268     * eventually.
269     */
270    void
271    post(int int_num, int index)
272    {
273        panic("Interrupts::post unimplemented!\n");
274    }
275
276    void
277    clear(int int_num, int index)
278    {
279        panic("Interrupts::clear unimplemented!\n");
280    }
281
282    void
283    clearAll()
284    {
285        panic("Interrupts::clearAll unimplemented!\n");
286    }
287};
288
289} // namespace X86ISA
290
291#endif // __ARCH_X86_INTERRUPTS_HH__
292