interrupts.hh revision 5704 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
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39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_INTERRUPTS_HH__
59#define __ARCH_X86_INTERRUPTS_HH__
60
61#include "arch/x86/apicregs.hh"
62#include "arch/x86/faults.hh"
63#include "arch/x86/intmessage.hh"
64#include "base/bitfield.hh"
65#include "cpu/thread_context.hh"
66#include "dev/io_device.hh"
67#include "dev/x86/intdev.hh"
68#include "params/X86LocalApic.hh"
69#include "sim/eventq.hh"
70
71class ThreadContext;
72
73namespace X86ISA {
74
75class Interrupts : public BasicPioDevice, IntDev
76{
77  protected:
78    // Storage for the APIC registers
79    uint32_t regs[NUM_APIC_REGS];
80
81    BitUnion32(LVTEntry)
82        Bitfield<7, 0> vector;
83        Bitfield<10, 8> deliveryMode;
84        Bitfield<12> status;
85        Bitfield<13> polarity;
86        Bitfield<14> remoteIRR;
87        Bitfield<15> trigger;
88        Bitfield<16> masked;
89        Bitfield<17> periodic;
90    EndBitUnion(LVTEntry)
91
92    /*
93     * Timing related stuff.
94     */
95    Tick latency;
96    Tick clock;
97
98    class ApicTimerEvent : public Event
99    {
100      private:
101        Interrupts *localApic;
102      public:
103        ApicTimerEvent(Interrupts *_localApic) :
104            Event(), localApic(_localApic)
105        {}
106
107        void process()
108        {
109            assert(localApic);
110            if (localApic->triggerTimerInterrupt()) {
111                localApic->setReg(APIC_INITIAL_COUNT,
112                        localApic->readReg(APIC_INITIAL_COUNT));
113            }
114        }
115    };
116
117    ApicTimerEvent apicTimerEvent;
118
119    /*
120     * A set of variables to keep track of interrupts that don't go through
121     * the IRR.
122     */
123    bool pendingSmi;
124    uint8_t smiVector;
125    bool pendingNmi;
126    uint8_t nmiVector;
127    bool pendingExtInt;
128    uint8_t extIntVector;
129    bool pendingInit;
130    uint8_t initVector;
131
132    // This is a quick check whether any of the above (except ExtInt) are set.
133    bool pendingUnmaskableInt;
134
135    /*
136     * IRR and ISR maintenance.
137     */
138    uint8_t IRRV;
139    uint8_t ISRV;
140
141    int
142    findRegArrayMSB(ApicRegIndex base)
143    {
144        int offset = 7;
145        do {
146            if (regs[base + offset] != 0) {
147                return offset * 32 + findMsbSet(regs[base + offset]);
148            }
149        } while (offset--);
150        return 0;
151    }
152
153    void
154    updateIRRV()
155    {
156        IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
157    }
158
159    void
160    updateISRV()
161    {
162        ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
163    }
164
165    void
166    setRegArrayBit(ApicRegIndex base, uint8_t vector)
167    {
168        regs[base + (vector % 32)] |= (1 << (vector >> 5));
169    }
170
171    void
172    clearRegArrayBit(ApicRegIndex base, uint8_t vector)
173    {
174        regs[base + (vector % 32)] &= ~(1 << (vector >> 5));
175    }
176
177    bool
178    getRegArrayBit(ApicRegIndex base, uint8_t vector)
179    {
180        return bits(regs[base + (vector % 32)], vector >> 5);
181    }
182
183    void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
184
185  public:
186    /*
187     * Params stuff.
188     */
189    typedef X86LocalApicParams Params;
190
191    void
192    setClock(Tick newClock)
193    {
194        clock = newClock;
195    }
196
197    const Params *
198    params() const
199    {
200        return dynamic_cast<const Params *>(_params);
201    }
202
203    /*
204     * Functions to interact with the interrupt port from IntDev.
205     */
206    Tick read(PacketPtr pkt);
207    Tick write(PacketPtr pkt);
208    Tick recvMessage(PacketPtr pkt);
209
210    bool
211    triggerTimerInterrupt()
212    {
213        LVTEntry entry = regs[APIC_LVT_TIMER];
214        if (!entry.masked)
215            requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
216        return entry.periodic;
217    }
218
219    void addressRanges(AddrRangeList &range_list)
220    {
221        range_list.clear();
222        range_list.push_back(RangeEx(x86LocalAPICAddress(0, 0),
223                                     x86LocalAPICAddress(0, 0) + PageBytes));
224    }
225
226    void getIntAddrRange(AddrRangeList &range_list)
227    {
228        range_list.clear();
229        range_list.push_back(RangeEx(x86InterruptAddress(0, 0),
230                    x86InterruptAddress(0, 0) + PhysAddrAPICRangeSize));
231    }
232
233    Port *getPort(const std::string &if_name, int idx = -1)
234    {
235        if (if_name == "int_port")
236            return intPort;
237        return BasicPioDevice::getPort(if_name, idx);
238    }
239
240    /*
241     * Functions to access and manipulate the APIC's registers.
242     */
243
244    uint32_t readReg(ApicRegIndex miscReg);
245    void setReg(ApicRegIndex reg, uint32_t val);
246    void
247    setRegNoEffect(ApicRegIndex reg, uint32_t val)
248    {
249        regs[reg] = val;
250    }
251
252    /*
253     * Constructor.
254     */
255
256    Interrupts(Params * p)
257        : BasicPioDevice(p), IntDev(this), latency(p->pio_latency), clock(0),
258          apicTimerEvent(this),
259          pendingSmi(false), smiVector(0),
260          pendingNmi(false), nmiVector(0),
261          pendingExtInt(false), extIntVector(0),
262          pendingInit(false), initVector(0),
263          pendingUnmaskableInt(false)
264    {
265        pioSize = PageBytes;
266        memset(regs, 0, sizeof(regs));
267        //Set the local apic DFR to the flat model.
268        regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
269        ISRV = 0;
270        IRRV = 0;
271    }
272
273    /*
274     * Functions for retrieving interrupts for the CPU to handle.
275     */
276
277    bool checkInterrupts(ThreadContext *tc) const;
278    Fault getInterrupt(ThreadContext *tc);
279    void updateIntrInfo(ThreadContext *tc);
280
281    /*
282     * Serialization.
283     */
284
285    void
286    serialize(std::ostream &os)
287    {
288        panic("Interrupts::serialize unimplemented!\n");
289    }
290
291    void
292    unserialize(Checkpoint *cp, const std::string &section)
293    {
294        panic("Interrupts::unserialize unimplemented!\n");
295    }
296
297    /*
298     * Old functions needed for compatability but which will be phased out
299     * eventually.
300     */
301    void
302    post(int int_num, int index)
303    {
304        panic("Interrupts::post unimplemented!\n");
305    }
306
307    void
308    clear(int int_num, int index)
309    {
310        panic("Interrupts::clear unimplemented!\n");
311    }
312
313    void
314    clearAll()
315    {
316        panic("Interrupts::clearAll unimplemented!\n");
317    }
318};
319
320} // namespace X86ISA
321
322#endif // __ARCH_X86_INTERRUPTS_HH__
323