interrupts.hh revision 12124:6edbfe40f4e8 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007 The Hewlett-Packard Development Company
15 * All rights reserved.
16 *
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder.  You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
25 *
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions are
28 * met: redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer;
30 * redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in the
32 * documentation and/or other materials provided with the distribution;
33 * neither the name of the copyright holders nor the names of its
34 * contributors may be used to endorse or promote products derived from
35 * this software without specific prior written permission.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 *
49 * Authors: Gabe Black
50 *          Andreas Hansson
51 */
52
53#ifndef __ARCH_X86_INTERRUPTS_HH__
54#define __ARCH_X86_INTERRUPTS_HH__
55
56#include "arch/x86/regs/apic.hh"
57#include "arch/x86/faults.hh"
58#include "arch/x86/intmessage.hh"
59#include "base/bitfield.hh"
60#include "cpu/thread_context.hh"
61#include "dev/x86/intdev.hh"
62#include "dev/io_device.hh"
63#include "params/X86LocalApic.hh"
64#include "sim/eventq.hh"
65
66class ThreadContext;
67class BaseCPU;
68
69int divideFromConf(uint32_t conf);
70
71namespace X86ISA {
72
73ApicRegIndex decodeAddr(Addr paddr);
74
75class Interrupts : public BasicPioDevice, IntDevice
76{
77  protected:
78    // Storage for the APIC registers
79    uint32_t regs[NUM_APIC_REGS];
80
81    BitUnion32(LVTEntry)
82        Bitfield<7, 0> vector;
83        Bitfield<10, 8> deliveryMode;
84        Bitfield<12> status;
85        Bitfield<13> polarity;
86        Bitfield<14> remoteIRR;
87        Bitfield<15> trigger;
88        Bitfield<16> masked;
89        Bitfield<17> periodic;
90    EndBitUnion(LVTEntry)
91
92    /*
93     * Timing related stuff.
94     */
95    EventFunctionWrapper apicTimerEvent;
96    void processApicTimerEvent();
97
98    /*
99     * A set of variables to keep track of interrupts that don't go through
100     * the IRR.
101     */
102    bool pendingSmi;
103    uint8_t smiVector;
104    bool pendingNmi;
105    uint8_t nmiVector;
106    bool pendingExtInt;
107    uint8_t extIntVector;
108    bool pendingInit;
109    uint8_t initVector;
110    bool pendingStartup;
111    uint8_t startupVector;
112    bool startedUp;
113
114    // This is a quick check whether any of the above (except ExtInt) are set.
115    bool pendingUnmaskableInt;
116
117    // A count of how many IPIs are in flight.
118    int pendingIPIs;
119
120    /*
121     * IRR and ISR maintenance.
122     */
123    uint8_t IRRV;
124    uint8_t ISRV;
125
126    int
127    findRegArrayMSB(ApicRegIndex base)
128    {
129        int offset = 7;
130        do {
131            if (regs[base + offset] != 0) {
132                return offset * 32 + findMsbSet(regs[base + offset]);
133            }
134        } while (offset--);
135        return 0;
136    }
137
138    void
139    updateIRRV()
140    {
141        IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
142    }
143
144    void
145    updateISRV()
146    {
147        ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
148    }
149
150    void
151    setRegArrayBit(ApicRegIndex base, uint8_t vector)
152    {
153        regs[base + (vector / 32)] |= (1 << (vector % 32));
154    }
155
156    void
157    clearRegArrayBit(ApicRegIndex base, uint8_t vector)
158    {
159        regs[base + (vector / 32)] &= ~(1 << (vector % 32));
160    }
161
162    bool
163    getRegArrayBit(ApicRegIndex base, uint8_t vector)
164    {
165        return bits(regs[base + (vector / 32)], vector % 32);
166    }
167
168    void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
169
170    BaseCPU *cpu;
171
172    int initialApicId;
173
174    // Port for receiving interrupts
175    IntSlavePort intSlavePort;
176
177  public:
178
179    int getInitialApicId() { return initialApicId; }
180
181    /*
182     * Params stuff.
183     */
184    typedef X86LocalApicParams Params;
185
186    void setCPU(BaseCPU * newCPU);
187
188    const Params *
189    params() const
190    {
191        return dynamic_cast<const Params *>(_params);
192    }
193
194    /*
195     * Initialize this object by registering it with the IO APIC.
196     */
197    void init() override;
198
199    /*
200     * Functions to interact with the interrupt port from IntDevice.
201     */
202    Tick read(PacketPtr pkt) override;
203    Tick write(PacketPtr pkt) override;
204    Tick recvMessage(PacketPtr pkt) override;
205    Tick recvResponse(PacketPtr pkt) override;
206
207    bool
208    triggerTimerInterrupt()
209    {
210        LVTEntry entry = regs[APIC_LVT_TIMER];
211        if (!entry.masked)
212            requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
213        return entry.periodic;
214    }
215
216    AddrRangeList getIntAddrRange() const override;
217
218    BaseMasterPort &getMasterPort(const std::string &if_name,
219                                  PortID idx = InvalidPortID) override
220    {
221        if (if_name == "int_master") {
222            return intMasterPort;
223        }
224        return BasicPioDevice::getMasterPort(if_name, idx);
225    }
226
227    BaseSlavePort &getSlavePort(const std::string &if_name,
228                                PortID idx = InvalidPortID) override
229    {
230        if (if_name == "int_slave") {
231            return intSlavePort;
232        }
233        return BasicPioDevice::getSlavePort(if_name, idx);
234    }
235
236    /*
237     * Functions to access and manipulate the APIC's registers.
238     */
239
240    uint32_t readReg(ApicRegIndex miscReg);
241    void setReg(ApicRegIndex reg, uint32_t val);
242    void
243    setRegNoEffect(ApicRegIndex reg, uint32_t val)
244    {
245        regs[reg] = val;
246    }
247
248    /*
249     * Constructor.
250     */
251
252    Interrupts(Params * p);
253
254    /*
255     * Functions for retrieving interrupts for the CPU to handle.
256     */
257
258    bool checkInterrupts(ThreadContext *tc) const;
259    /**
260     * Check if there are pending interrupts without ignoring the
261     * interrupts disabled flag.
262     *
263     * @return true if there are interrupts pending.
264     */
265    bool checkInterruptsRaw() const;
266    /**
267     * Check if there are pending unmaskable interrupts.
268     *
269     * @return true there are unmaskable interrupts pending.
270     */
271    bool hasPendingUnmaskable() const { return pendingUnmaskableInt; }
272    Fault getInterrupt(ThreadContext *tc);
273    void updateIntrInfo(ThreadContext *tc);
274
275    /*
276     * Serialization.
277     */
278    void serialize(CheckpointOut &cp) const override;
279    void unserialize(CheckpointIn &cp) override;
280
281    /*
282     * Old functions needed for compatability but which will be phased out
283     * eventually.
284     */
285    void
286    post(int int_num, int index)
287    {
288        panic("Interrupts::post unimplemented!\n");
289    }
290
291    void
292    clear(int int_num, int index)
293    {
294        panic("Interrupts::clear unimplemented!\n");
295    }
296
297    void
298    clearAll()
299    {
300        panic("Interrupts::clearAll unimplemented!\n");
301    }
302};
303
304} // namespace X86ISA
305
306#endif // __ARCH_X86_INTERRUPTS_HH__
307