interrupts.cc revision 9808:13ffc0066b76 
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2008 The Hewlett-Packard Development Company
15 * All rights reserved.
16 *
17 * The license below extends only to copyright in the software and shall
18 * not be construed as granting a license to any other intellectual
19 * property including but not limited to intellectual property relating
20 * to a hardware implementation of the functionality of the software
21 * licensed hereunder.  You may use the software subject to the license
22 * terms below provided that you ensure that this notice is replicated
23 * unmodified and in its entirety in all distributions of the software,
24 * modified or unmodified, in source code or in binary form.
25 *
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions are
28 * met: redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer;
30 * redistributions in binary form must reproduce the above copyright
31 * notice, this list of conditions and the following disclaimer in the
32 * documentation and/or other materials provided with the distribution;
33 * neither the name of the copyright holders nor the names of its
34 * contributors may be used to endorse or promote products derived from
35 * this software without specific prior written permission.
36 *
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 *
49 * Authors: Gabe Black
50 */
51
52#include "arch/x86/regs/apic.hh"
53#include "arch/x86/interrupts.hh"
54#include "arch/x86/intmessage.hh"
55#include "cpu/base.hh"
56#include "debug/LocalApic.hh"
57#include "dev/x86/i82094aa.hh"
58#include "dev/x86/pc.hh"
59#include "dev/x86/south_bridge.hh"
60#include "mem/packet_access.hh"
61#include "sim/system.hh"
62#include "sim/full_system.hh"
63
64int
65divideFromConf(uint32_t conf)
66{
67    // This figures out what division we want from the division configuration
68    // register in the local APIC. The encoding is a little odd but it can
69    // be deciphered fairly easily.
70    int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
71    shift = (shift + 1) % 8;
72    return 1 << shift;
73}
74
75namespace X86ISA
76{
77
78ApicRegIndex
79decodeAddr(Addr paddr)
80{
81    ApicRegIndex regNum;
82    paddr &= ~mask(3);
83    switch (paddr)
84    {
85      case 0x20:
86        regNum = APIC_ID;
87        break;
88      case 0x30:
89        regNum = APIC_VERSION;
90        break;
91      case 0x80:
92        regNum = APIC_TASK_PRIORITY;
93        break;
94      case 0x90:
95        regNum = APIC_ARBITRATION_PRIORITY;
96        break;
97      case 0xA0:
98        regNum = APIC_PROCESSOR_PRIORITY;
99        break;
100      case 0xB0:
101        regNum = APIC_EOI;
102        break;
103      case 0xD0:
104        regNum = APIC_LOGICAL_DESTINATION;
105        break;
106      case 0xE0:
107        regNum = APIC_DESTINATION_FORMAT;
108        break;
109      case 0xF0:
110        regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
111        break;
112      case 0x100:
113      case 0x108:
114      case 0x110:
115      case 0x118:
116      case 0x120:
117      case 0x128:
118      case 0x130:
119      case 0x138:
120      case 0x140:
121      case 0x148:
122      case 0x150:
123      case 0x158:
124      case 0x160:
125      case 0x168:
126      case 0x170:
127      case 0x178:
128        regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
129        break;
130      case 0x180:
131      case 0x188:
132      case 0x190:
133      case 0x198:
134      case 0x1A0:
135      case 0x1A8:
136      case 0x1B0:
137      case 0x1B8:
138      case 0x1C0:
139      case 0x1C8:
140      case 0x1D0:
141      case 0x1D8:
142      case 0x1E0:
143      case 0x1E8:
144      case 0x1F0:
145      case 0x1F8:
146        regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
147        break;
148      case 0x200:
149      case 0x208:
150      case 0x210:
151      case 0x218:
152      case 0x220:
153      case 0x228:
154      case 0x230:
155      case 0x238:
156      case 0x240:
157      case 0x248:
158      case 0x250:
159      case 0x258:
160      case 0x260:
161      case 0x268:
162      case 0x270:
163      case 0x278:
164        regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
165        break;
166      case 0x280:
167        regNum = APIC_ERROR_STATUS;
168        break;
169      case 0x300:
170        regNum = APIC_INTERRUPT_COMMAND_LOW;
171        break;
172      case 0x310:
173        regNum = APIC_INTERRUPT_COMMAND_HIGH;
174        break;
175      case 0x320:
176        regNum = APIC_LVT_TIMER;
177        break;
178      case 0x330:
179        regNum = APIC_LVT_THERMAL_SENSOR;
180        break;
181      case 0x340:
182        regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
183        break;
184      case 0x350:
185        regNum = APIC_LVT_LINT0;
186        break;
187      case 0x360:
188        regNum = APIC_LVT_LINT1;
189        break;
190      case 0x370:
191        regNum = APIC_LVT_ERROR;
192        break;
193      case 0x380:
194        regNum = APIC_INITIAL_COUNT;
195        break;
196      case 0x390:
197        regNum = APIC_CURRENT_COUNT;
198        break;
199      case 0x3E0:
200        regNum = APIC_DIVIDE_CONFIGURATION;
201        break;
202      default:
203        // A reserved register field.
204        panic("Accessed reserved register field %#x.\n", paddr);
205        break;
206    }
207    return regNum;
208}
209}
210
211Tick
212X86ISA::Interrupts::read(PacketPtr pkt)
213{
214    Addr offset = pkt->getAddr() - pioAddr;
215    //Make sure we're at least only accessing one register.
216    if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
217        panic("Accessed more than one register at a time in the APIC!\n");
218    ApicRegIndex reg = decodeAddr(offset);
219    uint32_t val = htog(readReg(reg));
220    DPRINTF(LocalApic,
221            "Reading Local APIC register %d at offset %#x as %#x.\n",
222            reg, offset, val);
223    pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
224    pkt->makeAtomicResponse();
225    return pioDelay;
226}
227
228Tick
229X86ISA::Interrupts::write(PacketPtr pkt)
230{
231    Addr offset = pkt->getAddr() - pioAddr;
232    //Make sure we're at least only accessing one register.
233    if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
234        panic("Accessed more than one register at a time in the APIC!\n");
235    ApicRegIndex reg = decodeAddr(offset);
236    uint32_t val = regs[reg];
237    pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
238    DPRINTF(LocalApic,
239            "Writing Local APIC register %d at offset %#x as %#x.\n",
240            reg, offset, gtoh(val));
241    setReg(reg, gtoh(val));
242    pkt->makeAtomicResponse();
243    return pioDelay;
244}
245void
246X86ISA::Interrupts::requestInterrupt(uint8_t vector,
247        uint8_t deliveryMode, bool level)
248{
249    /*
250     * Fixed and lowest-priority delivery mode interrupts are handled
251     * using the IRR/ISR registers, checking against the TPR, etc.
252     * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
253     */
254    if (deliveryMode == DeliveryMode::Fixed ||
255            deliveryMode == DeliveryMode::LowestPriority) {
256        DPRINTF(LocalApic, "Interrupt is an %s.\n",
257                DeliveryMode::names[deliveryMode]);
258        // Queue up the interrupt in the IRR.
259        if (vector > IRRV)
260            IRRV = vector;
261        if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
262            setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
263            if (level) {
264                setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
265            } else {
266                clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
267            }
268        }
269    } else if (!DeliveryMode::isReserved(deliveryMode)) {
270        DPRINTF(LocalApic, "Interrupt is an %s.\n",
271                DeliveryMode::names[deliveryMode]);
272        if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
273            pendingUnmaskableInt = pendingSmi = true;
274            smiVector = vector;
275        } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
276            pendingUnmaskableInt = pendingNmi = true;
277            nmiVector = vector;
278        } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
279            pendingExtInt = true;
280            extIntVector = vector;
281        } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
282            pendingUnmaskableInt = pendingInit = true;
283            initVector = vector;
284        } else if (deliveryMode == DeliveryMode::SIPI &&
285                !pendingStartup && !startedUp) {
286            pendingUnmaskableInt = pendingStartup = true;
287            startupVector = vector;
288        }
289    }
290    if (FullSystem)
291        cpu->wakeup();
292}
293
294
295void
296X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
297{
298    assert(newCPU);
299    if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) {
300        panic("Local APICs can't be moved between CPUs"
301                " with different IDs.\n");
302    }
303    cpu = newCPU;
304    initialApicId = cpu->cpuId();
305    regs[APIC_ID] = (initialApicId << 24);
306    pioAddr = x86LocalAPICAddress(initialApicId, 0);
307}
308
309
310void
311X86ISA::Interrupts::init()
312{
313    //
314    // The local apic must register its address ranges on both its pio
315    // port via the basicpiodevice(piodevice) init() function and its
316    // int port that it inherited from IntDevice.  Note IntDevice is
317    // not a SimObject itself.
318    //
319    BasicPioDevice::init();
320    IntDevice::init();
321
322    // the slave port has a range so inform the connected master
323    intSlavePort.sendRangeChange();
324}
325
326
327Tick
328X86ISA::Interrupts::recvMessage(PacketPtr pkt)
329{
330    Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0);
331    assert(pkt->cmd == MemCmd::MessageReq);
332    switch(offset)
333    {
334      case 0:
335        {
336            TriggerIntMessage message = pkt->get<TriggerIntMessage>();
337            DPRINTF(LocalApic,
338                    "Got Trigger Interrupt message with vector %#x.\n",
339                    message.vector);
340
341            requestInterrupt(message.vector,
342                    message.deliveryMode, message.trigger);
343        }
344        break;
345      default:
346        panic("Local apic got unknown interrupt message at offset %#x.\n",
347                offset);
348        break;
349    }
350    pkt->makeAtomicResponse();
351    return pioDelay;
352}
353
354
355Tick
356X86ISA::Interrupts::recvResponse(PacketPtr pkt)
357{
358    assert(!pkt->isError());
359    assert(pkt->cmd == MemCmd::MessageResp);
360    if (--pendingIPIs == 0) {
361        InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
362        // Record that the ICR is now idle.
363        low.deliveryStatus = 0;
364        regs[APIC_INTERRUPT_COMMAND_LOW] = low;
365    }
366    DPRINTF(LocalApic, "ICR is now idle.\n");
367    return 0;
368}
369
370
371AddrRangeList
372X86ISA::Interrupts::getIntAddrRange() const
373{
374    AddrRangeList ranges;
375    ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
376                             x86InterruptAddress(initialApicId, 0) +
377                             PhysAddrAPICRangeSize));
378    return ranges;
379}
380
381
382uint32_t
383X86ISA::Interrupts::readReg(ApicRegIndex reg)
384{
385    if (reg >= APIC_TRIGGER_MODE(0) &&
386            reg <= APIC_TRIGGER_MODE(15)) {
387        panic("Local APIC Trigger Mode registers are unimplemented.\n");
388    }
389    switch (reg) {
390      case APIC_ARBITRATION_PRIORITY:
391        panic("Local APIC Arbitration Priority register unimplemented.\n");
392        break;
393      case APIC_PROCESSOR_PRIORITY:
394        panic("Local APIC Processor Priority register unimplemented.\n");
395        break;
396      case APIC_ERROR_STATUS:
397        regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
398        break;
399      case APIC_CURRENT_COUNT:
400        {
401            if (apicTimerEvent.scheduled()) {
402                // Compute how many m5 ticks happen per count.
403                uint64_t ticksPerCount = clockPeriod() *
404                    divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
405                // Compute how many m5 ticks are left.
406                uint64_t val = apicTimerEvent.when() - curTick();
407                // Turn that into a count.
408                val = (val + ticksPerCount - 1) / ticksPerCount;
409                return val;
410            } else {
411                return 0;
412            }
413        }
414      default:
415        break;
416    }
417    return regs[reg];
418}
419
420void
421X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
422{
423    uint32_t newVal = val;
424    if (reg >= APIC_IN_SERVICE(0) &&
425            reg <= APIC_IN_SERVICE(15)) {
426        panic("Local APIC In-Service registers are unimplemented.\n");
427    }
428    if (reg >= APIC_TRIGGER_MODE(0) &&
429            reg <= APIC_TRIGGER_MODE(15)) {
430        panic("Local APIC Trigger Mode registers are unimplemented.\n");
431    }
432    if (reg >= APIC_INTERRUPT_REQUEST(0) &&
433            reg <= APIC_INTERRUPT_REQUEST(15)) {
434        panic("Local APIC Interrupt Request registers "
435                "are unimplemented.\n");
436    }
437    switch (reg) {
438      case APIC_ID:
439        newVal = val & 0xFF;
440        break;
441      case APIC_VERSION:
442        // The Local APIC Version register is read only.
443        return;
444      case APIC_TASK_PRIORITY:
445        newVal = val & 0xFF;
446        break;
447      case APIC_ARBITRATION_PRIORITY:
448        panic("Local APIC Arbitration Priority register unimplemented.\n");
449        break;
450      case APIC_PROCESSOR_PRIORITY:
451        panic("Local APIC Processor Priority register unimplemented.\n");
452        break;
453      case APIC_EOI:
454        // Remove the interrupt that just completed from the local apic state.
455        clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
456        updateISRV();
457        return;
458      case APIC_LOGICAL_DESTINATION:
459        newVal = val & 0xFF000000;
460        break;
461      case APIC_DESTINATION_FORMAT:
462        newVal = val | 0x0FFFFFFF;
463        break;
464      case APIC_SPURIOUS_INTERRUPT_VECTOR:
465        regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
466        regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
467        if (val & (1 << 9))
468            warn("Focus processor checking not implemented.\n");
469        break;
470      case APIC_ERROR_STATUS:
471        {
472            if (regs[APIC_INTERNAL_STATE] & 0x1) {
473                regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
474                newVal = 0;
475            } else {
476                regs[APIC_INTERNAL_STATE] |= ULL(0x1);
477                return;
478            }
479
480        }
481        break;
482      case APIC_INTERRUPT_COMMAND_LOW:
483        {
484            InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW];
485            // Check if we're already sending an IPI.
486            if (low.deliveryStatus) {
487                newVal = low;
488                break;
489            }
490            low = val;
491            InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH];
492            // Record that an IPI is being sent.
493            low.deliveryStatus = 1;
494            TriggerIntMessage message = 0;
495            message.destination = high.destination;
496            message.vector = low.vector;
497            message.deliveryMode = low.deliveryMode;
498            message.destMode = low.destMode;
499            message.level = low.level;
500            message.trigger = low.trigger;
501            bool timing(sys->isTimingMode());
502            // Be careful no updates of the delivery status bit get lost.
503            regs[APIC_INTERRUPT_COMMAND_LOW] = low;
504            ApicList apics;
505            int numContexts = sys->numContexts();
506            switch (low.destShorthand) {
507              case 0:
508                if (message.deliveryMode == DeliveryMode::LowestPriority) {
509                    panic("Lowest priority delivery mode "
510                            "IPIs aren't implemented.\n");
511                }
512                if (message.destMode == 1) {
513                    int dest = message.destination;
514                    hack_once("Assuming logical destinations are 1 << id.\n");
515                    for (int i = 0; i < numContexts; i++) {
516                        if (dest & 0x1)
517                            apics.push_back(i);
518                        dest = dest >> 1;
519                    }
520                } else {
521                    if (message.destination == 0xFF) {
522                        for (int i = 0; i < numContexts; i++) {
523                            if (i == initialApicId) {
524                                requestInterrupt(message.vector,
525                                        message.deliveryMode, message.trigger);
526                            } else {
527                                apics.push_back(i);
528                            }
529                        }
530                    } else {
531                        if (message.destination == initialApicId) {
532                            requestInterrupt(message.vector,
533                                    message.deliveryMode, message.trigger);
534                        } else {
535                            apics.push_back(message.destination);
536                        }
537                    }
538                }
539                break;
540              case 1:
541                newVal = val;
542                requestInterrupt(message.vector,
543                        message.deliveryMode, message.trigger);
544                break;
545              case 2:
546                requestInterrupt(message.vector,
547                        message.deliveryMode, message.trigger);
548                // Fall through
549              case 3:
550                {
551                    for (int i = 0; i < numContexts; i++) {
552                        if (i != initialApicId) {
553                            apics.push_back(i);
554                        }
555                    }
556                }
557                break;
558            }
559            pendingIPIs += apics.size();
560            intMasterPort.sendMessage(apics, message, timing);
561            newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
562        }
563        break;
564      case APIC_LVT_TIMER:
565      case APIC_LVT_THERMAL_SENSOR:
566      case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
567      case APIC_LVT_LINT0:
568      case APIC_LVT_LINT1:
569      case APIC_LVT_ERROR:
570        {
571            uint64_t readOnlyMask = (1 << 12) | (1 << 14);
572            newVal = (val & ~readOnlyMask) |
573                     (regs[reg] & readOnlyMask);
574        }
575        break;
576      case APIC_INITIAL_COUNT:
577        {
578            newVal = bits(val, 31, 0);
579            // Compute how many timer ticks we're being programmed for.
580            uint64_t newCount = newVal *
581                (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
582            // Schedule on the edge of the next tick plus the new count.
583            Tick offset = curTick() % clockPeriod();
584            if (offset) {
585                reschedule(apicTimerEvent,
586                           curTick() + (newCount + 1) *
587                           clockPeriod() - offset, true);
588            } else {
589                if (newCount)
590                    reschedule(apicTimerEvent,
591                               curTick() + newCount *
592                               clockPeriod(), true);
593            }
594        }
595        break;
596      case APIC_CURRENT_COUNT:
597        //Local APIC Current Count register is read only.
598        return;
599      case APIC_DIVIDE_CONFIGURATION:
600        newVal = val & 0xB;
601        break;
602      default:
603        break;
604    }
605    regs[reg] = newVal;
606    return;
607}
608
609
610X86ISA::Interrupts::Interrupts(Params * p)
611    : BasicPioDevice(p, PageBytes), IntDevice(this, p->int_latency),
612      apicTimerEvent(this),
613      pendingSmi(false), smiVector(0),
614      pendingNmi(false), nmiVector(0),
615      pendingExtInt(false), extIntVector(0),
616      pendingInit(false), initVector(0),
617      pendingStartup(false), startupVector(0),
618      startedUp(false), pendingUnmaskableInt(false),
619      pendingIPIs(0), cpu(NULL),
620      intSlavePort(name() + ".int_slave", this, this)
621{
622    memset(regs, 0, sizeof(regs));
623    //Set the local apic DFR to the flat model.
624    regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
625    ISRV = 0;
626    IRRV = 0;
627}
628
629
630bool
631X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
632{
633    RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
634    if (pendingUnmaskableInt) {
635        DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
636        return true;
637    }
638    if (rflags.intf) {
639        if (pendingExtInt) {
640            DPRINTF(LocalApic, "Reported pending external interrupt.\n");
641            return true;
642        }
643        if (IRRV > ISRV && bits(IRRV, 7, 4) >
644               bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
645            DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
646            return true;
647        }
648    }
649    return false;
650}
651
652Fault
653X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
654{
655    assert(checkInterrupts(tc));
656    // These are all probably fairly uncommon, so we'll make them easier to
657    // check for.
658    if (pendingUnmaskableInt) {
659        if (pendingSmi) {
660            DPRINTF(LocalApic, "Generated SMI fault object.\n");
661            return new SystemManagementInterrupt();
662        } else if (pendingNmi) {
663            DPRINTF(LocalApic, "Generated NMI fault object.\n");
664            return new NonMaskableInterrupt(nmiVector);
665        } else if (pendingInit) {
666            DPRINTF(LocalApic, "Generated INIT fault object.\n");
667            return new InitInterrupt(initVector);
668        } else if (pendingStartup) {
669            DPRINTF(LocalApic, "Generating SIPI fault object.\n");
670            return new StartupInterrupt(startupVector);
671        } else {
672            panic("pendingUnmaskableInt set, but no unmaskable "
673                    "ints were pending.\n");
674            return NoFault;
675        }
676    } else if (pendingExtInt) {
677        DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
678        return new ExternalInterrupt(extIntVector);
679    } else {
680        DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
681        // The only thing left are fixed and lowest priority interrupts.
682        return new ExternalInterrupt(IRRV);
683    }
684}
685
686void
687X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
688{
689    assert(checkInterrupts(tc));
690    if (pendingUnmaskableInt) {
691        if (pendingSmi) {
692            DPRINTF(LocalApic, "SMI sent to core.\n");
693            pendingSmi = false;
694        } else if (pendingNmi) {
695            DPRINTF(LocalApic, "NMI sent to core.\n");
696            pendingNmi = false;
697        } else if (pendingInit) {
698            DPRINTF(LocalApic, "Init sent to core.\n");
699            pendingInit = false;
700            startedUp = false;
701        } else if (pendingStartup) {
702            DPRINTF(LocalApic, "SIPI sent to core.\n");
703            pendingStartup = false;
704            startedUp = true;
705        }
706        if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup))
707            pendingUnmaskableInt = false;
708    } else if (pendingExtInt) {
709        pendingExtInt = false;
710    } else {
711        DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
712        // Mark the interrupt as "in service".
713        ISRV = IRRV;
714        setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
715        // Clear it out of the IRR.
716        clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
717        updateIRRV();
718    }
719}
720
721void
722X86ISA::Interrupts::serialize(std::ostream &os)
723{
724    SERIALIZE_ARRAY(regs, NUM_APIC_REGS);
725    SERIALIZE_SCALAR(pendingSmi);
726    SERIALIZE_SCALAR(smiVector);
727    SERIALIZE_SCALAR(pendingNmi);
728    SERIALIZE_SCALAR(nmiVector);
729    SERIALIZE_SCALAR(pendingExtInt);
730    SERIALIZE_SCALAR(extIntVector);
731    SERIALIZE_SCALAR(pendingInit);
732    SERIALIZE_SCALAR(initVector);
733    SERIALIZE_SCALAR(pendingStartup);
734    SERIALIZE_SCALAR(startupVector);
735    SERIALIZE_SCALAR(startedUp);
736    SERIALIZE_SCALAR(pendingUnmaskableInt);
737    SERIALIZE_SCALAR(pendingIPIs);
738    SERIALIZE_SCALAR(IRRV);
739    SERIALIZE_SCALAR(ISRV);
740    bool apicTimerEventScheduled = apicTimerEvent.scheduled();
741    SERIALIZE_SCALAR(apicTimerEventScheduled);
742    Tick apicTimerEventTick = apicTimerEvent.when();
743    SERIALIZE_SCALAR(apicTimerEventTick);
744}
745
746void
747X86ISA::Interrupts::unserialize(Checkpoint *cp, const std::string &section)
748{
749    UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS);
750    UNSERIALIZE_SCALAR(pendingSmi);
751    UNSERIALIZE_SCALAR(smiVector);
752    UNSERIALIZE_SCALAR(pendingNmi);
753    UNSERIALIZE_SCALAR(nmiVector);
754    UNSERIALIZE_SCALAR(pendingExtInt);
755    UNSERIALIZE_SCALAR(extIntVector);
756    UNSERIALIZE_SCALAR(pendingInit);
757    UNSERIALIZE_SCALAR(initVector);
758    UNSERIALIZE_SCALAR(pendingStartup);
759    UNSERIALIZE_SCALAR(startupVector);
760    UNSERIALIZE_SCALAR(startedUp);
761    UNSERIALIZE_SCALAR(pendingUnmaskableInt);
762    UNSERIALIZE_SCALAR(pendingIPIs);
763    UNSERIALIZE_SCALAR(IRRV);
764    UNSERIALIZE_SCALAR(ISRV);
765    bool apicTimerEventScheduled;
766    UNSERIALIZE_SCALAR(apicTimerEventScheduled);
767    if (apicTimerEventScheduled) {
768        Tick apicTimerEventTick;
769        UNSERIALIZE_SCALAR(apicTimerEventTick);
770        if (apicTimerEvent.scheduled()) {
771            reschedule(apicTimerEvent, apicTimerEventTick, true);
772        } else {
773            schedule(apicTimerEvent, apicTimerEventTick);
774        }
775    }
776}
777
778X86ISA::Interrupts *
779X86LocalApicParams::create()
780{
781    return new X86ISA::Interrupts(this);
782}
783