interrupts.cc revision 6041 
1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use.  Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 *     Director of Intellectual Property Licensing
21 *     Office of Strategy and Technology
22 *     Hewlett-Packard Company
23 *     1501 Page Mill Road
24 *     Palo Alto, California  94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer.  Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution.  Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission.  No right of
34 * sublicense is granted herewith.  Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses.  Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/apicregs.hh"
59#include "arch/x86/interrupts.hh"
60#include "arch/x86/intmessage.hh"
61#include "cpu/base.hh"
62#include "mem/packet_access.hh"
63
64int
65divideFromConf(uint32_t conf)
66{
67    // This figures out what division we want from the division configuration
68    // register in the local APIC. The encoding is a little odd but it can
69    // be deciphered fairly easily.
70    int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
71    shift = (shift + 1) % 8;
72    return 1 << shift;
73}
74
75namespace X86ISA
76{
77
78ApicRegIndex
79decodeAddr(Addr paddr)
80{
81    ApicRegIndex regNum;
82    paddr &= ~mask(3);
83    switch (paddr)
84    {
85      case 0x20:
86        regNum = APIC_ID;
87        break;
88      case 0x30:
89        regNum = APIC_VERSION;
90        break;
91      case 0x80:
92        regNum = APIC_TASK_PRIORITY;
93        break;
94      case 0x90:
95        regNum = APIC_ARBITRATION_PRIORITY;
96        break;
97      case 0xA0:
98        regNum = APIC_PROCESSOR_PRIORITY;
99        break;
100      case 0xB0:
101        regNum = APIC_EOI;
102        break;
103      case 0xD0:
104        regNum = APIC_LOGICAL_DESTINATION;
105        break;
106      case 0xE0:
107        regNum = APIC_DESTINATION_FORMAT;
108        break;
109      case 0xF0:
110        regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
111        break;
112      case 0x100:
113      case 0x108:
114      case 0x110:
115      case 0x118:
116      case 0x120:
117      case 0x128:
118      case 0x130:
119      case 0x138:
120      case 0x140:
121      case 0x148:
122      case 0x150:
123      case 0x158:
124      case 0x160:
125      case 0x168:
126      case 0x170:
127      case 0x178:
128        regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
129        break;
130      case 0x180:
131      case 0x188:
132      case 0x190:
133      case 0x198:
134      case 0x1A0:
135      case 0x1A8:
136      case 0x1B0:
137      case 0x1B8:
138      case 0x1C0:
139      case 0x1C8:
140      case 0x1D0:
141      case 0x1D8:
142      case 0x1E0:
143      case 0x1E8:
144      case 0x1F0:
145      case 0x1F8:
146        regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
147        break;
148      case 0x200:
149      case 0x208:
150      case 0x210:
151      case 0x218:
152      case 0x220:
153      case 0x228:
154      case 0x230:
155      case 0x238:
156      case 0x240:
157      case 0x248:
158      case 0x250:
159      case 0x258:
160      case 0x260:
161      case 0x268:
162      case 0x270:
163      case 0x278:
164        regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
165        break;
166      case 0x280:
167        regNum = APIC_ERROR_STATUS;
168        break;
169      case 0x300:
170        regNum = APIC_INTERRUPT_COMMAND_LOW;
171        break;
172      case 0x310:
173        regNum = APIC_INTERRUPT_COMMAND_HIGH;
174        break;
175      case 0x320:
176        regNum = APIC_LVT_TIMER;
177        break;
178      case 0x330:
179        regNum = APIC_LVT_THERMAL_SENSOR;
180        break;
181      case 0x340:
182        regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
183        break;
184      case 0x350:
185        regNum = APIC_LVT_LINT0;
186        break;
187      case 0x360:
188        regNum = APIC_LVT_LINT1;
189        break;
190      case 0x370:
191        regNum = APIC_LVT_ERROR;
192        break;
193      case 0x380:
194        regNum = APIC_INITIAL_COUNT;
195        break;
196      case 0x390:
197        regNum = APIC_CURRENT_COUNT;
198        break;
199      case 0x3E0:
200        regNum = APIC_DIVIDE_CONFIGURATION;
201        break;
202      default:
203        // A reserved register field.
204        panic("Accessed reserved register field %#x.\n", paddr);
205        break;
206    }
207    return regNum;
208}
209}
210
211Tick
212X86ISA::Interrupts::read(PacketPtr pkt)
213{
214    Addr offset = pkt->getAddr() - pioAddr;
215    //Make sure we're at least only accessing one register.
216    if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
217        panic("Accessed more than one register at a time in the APIC!\n");
218    ApicRegIndex reg = decodeAddr(offset);
219    uint32_t val = htog(readReg(reg));
220    DPRINTF(LocalApic,
221            "Reading Local APIC register %d at offset %#x as %#x.\n",
222            reg, offset, val);
223    pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
224    pkt->makeAtomicResponse();
225    return latency;
226}
227
228Tick
229X86ISA::Interrupts::write(PacketPtr pkt)
230{
231    Addr offset = pkt->getAddr() - pioAddr;
232    //Make sure we're at least only accessing one register.
233    if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
234        panic("Accessed more than one register at a time in the APIC!\n");
235    ApicRegIndex reg = decodeAddr(offset);
236    uint32_t val = regs[reg];
237    pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
238    DPRINTF(LocalApic,
239            "Writing Local APIC register %d at offset %#x as %#x.\n",
240            reg, offset, gtoh(val));
241    setReg(reg, gtoh(val));
242    pkt->makeAtomicResponse();
243    return latency;
244}
245void
246X86ISA::Interrupts::requestInterrupt(uint8_t vector,
247        uint8_t deliveryMode, bool level)
248{
249    /*
250     * Fixed and lowest-priority delivery mode interrupts are handled
251     * using the IRR/ISR registers, checking against the TPR, etc.
252     * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
253     */
254    if (deliveryMode == DeliveryMode::Fixed ||
255            deliveryMode == DeliveryMode::LowestPriority) {
256        DPRINTF(LocalApic, "Interrupt is an %s.\n",
257                DeliveryMode::names[deliveryMode]);
258        // Queue up the interrupt in the IRR.
259        if (vector > IRRV)
260            IRRV = vector;
261        if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
262            setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
263            if (level) {
264                setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
265            } else {
266                clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
267            }
268        }
269    } else if (!DeliveryMode::isReserved(deliveryMode)) {
270        DPRINTF(LocalApic, "Interrupt is an %s.\n",
271                DeliveryMode::names[deliveryMode]);
272        if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
273            pendingUnmaskableInt = pendingSmi = true;
274            smiVector = vector;
275        } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
276            pendingUnmaskableInt = pendingNmi = true;
277            nmiVector = vector;
278        } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
279            pendingExtInt = true;
280            extIntVector = vector;
281        } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
282            pendingUnmaskableInt = pendingInit = true;
283            initVector = vector;
284        }
285    }
286    cpu->wakeup();
287}
288
289
290void
291X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
292{
293    cpu = newCPU;
294    assert(cpu);
295    regs[APIC_ID] = (cpu->cpuId() << 24);
296}
297
298
299Tick
300X86ISA::Interrupts::recvMessage(PacketPtr pkt)
301{
302    uint8_t id = (regs[APIC_ID] >> 24);
303    Addr offset = pkt->getAddr() - x86InterruptAddress(id, 0);
304    assert(pkt->cmd == MemCmd::MessageReq);
305    switch(offset)
306    {
307      case 0:
308        {
309            TriggerIntMessage message = pkt->get<TriggerIntMessage>();
310            DPRINTF(LocalApic,
311                    "Got Trigger Interrupt message with vector %#x.\n",
312                    message.vector);
313            // Make sure we're really supposed to get this.
314            assert((message.destMode == 0 && message.destination == id) ||
315                   (bits((int)message.destination, id)));
316
317            requestInterrupt(message.vector,
318                    message.deliveryMode, message.trigger);
319        }
320        break;
321      default:
322        panic("Local apic got unknown interrupt message at offset %#x.\n",
323                offset);
324        break;
325    }
326    delete pkt->req;
327    delete pkt;
328    return latency;
329}
330
331
332void
333X86ISA::Interrupts::addressRanges(AddrRangeList &range_list)
334{
335    uint8_t id = (regs[APIC_ID] >> 24);
336    range_list.clear();
337    range_list.push_back(RangeEx(x86LocalAPICAddress(id, 0),
338                                 x86LocalAPICAddress(id, 0) + PageBytes));
339}
340
341
342void
343X86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list)
344{
345    uint8_t id = (regs[APIC_ID] >> 24);
346    range_list.clear();
347    range_list.push_back(RangeEx(x86InterruptAddress(id, 0),
348                x86InterruptAddress(id, 0) + PhysAddrAPICRangeSize));
349}
350
351
352uint32_t
353X86ISA::Interrupts::readReg(ApicRegIndex reg)
354{
355    if (reg >= APIC_TRIGGER_MODE(0) &&
356            reg <= APIC_TRIGGER_MODE(15)) {
357        panic("Local APIC Trigger Mode registers are unimplemented.\n");
358    }
359    switch (reg) {
360      case APIC_ARBITRATION_PRIORITY:
361        panic("Local APIC Arbitration Priority register unimplemented.\n");
362        break;
363      case APIC_PROCESSOR_PRIORITY:
364        panic("Local APIC Processor Priority register unimplemented.\n");
365        break;
366      case APIC_ERROR_STATUS:
367        regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
368        break;
369      case APIC_INTERRUPT_COMMAND_LOW:
370        panic("Local APIC Interrupt Command low"
371                " register unimplemented.\n");
372        break;
373      case APIC_INTERRUPT_COMMAND_HIGH:
374        panic("Local APIC Interrupt Command high"
375                " register unimplemented.\n");
376        break;
377      case APIC_CURRENT_COUNT:
378        {
379            if (apicTimerEvent.scheduled()) {
380                assert(clock);
381                // Compute how many m5 ticks happen per count.
382                uint64_t ticksPerCount = clock *
383                    divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
384                // Compute how many m5 ticks are left.
385                uint64_t val = apicTimerEvent.when() - curTick;
386                // Turn that into a count.
387                val = (val + ticksPerCount - 1) / ticksPerCount;
388                return val;
389            } else {
390                return 0;
391            }
392        }
393      default:
394        break;
395    }
396    return regs[reg];
397}
398
399void
400X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
401{
402    uint32_t newVal = val;
403    if (reg >= APIC_IN_SERVICE(0) &&
404            reg <= APIC_IN_SERVICE(15)) {
405        panic("Local APIC In-Service registers are unimplemented.\n");
406    }
407    if (reg >= APIC_TRIGGER_MODE(0) &&
408            reg <= APIC_TRIGGER_MODE(15)) {
409        panic("Local APIC Trigger Mode registers are unimplemented.\n");
410    }
411    if (reg >= APIC_INTERRUPT_REQUEST(0) &&
412            reg <= APIC_INTERRUPT_REQUEST(15)) {
413        panic("Local APIC Interrupt Request registers "
414                "are unimplemented.\n");
415    }
416    switch (reg) {
417      case APIC_ID:
418        newVal = val & 0xFF;
419        break;
420      case APIC_VERSION:
421        // The Local APIC Version register is read only.
422        return;
423      case APIC_TASK_PRIORITY:
424        newVal = val & 0xFF;
425        break;
426      case APIC_ARBITRATION_PRIORITY:
427        panic("Local APIC Arbitration Priority register unimplemented.\n");
428        break;
429      case APIC_PROCESSOR_PRIORITY:
430        panic("Local APIC Processor Priority register unimplemented.\n");
431        break;
432      case APIC_EOI:
433        // Remove the interrupt that just completed from the local apic state.
434        clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
435        updateISRV();
436        return;
437      case APIC_LOGICAL_DESTINATION:
438        newVal = val & 0xFF000000;
439        break;
440      case APIC_DESTINATION_FORMAT:
441        newVal = val | 0x0FFFFFFF;
442        break;
443      case APIC_SPURIOUS_INTERRUPT_VECTOR:
444        regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
445        regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
446        if (val & (1 << 9))
447            warn("Focus processor checking not implemented.\n");
448        break;
449      case APIC_ERROR_STATUS:
450        {
451            if (regs[APIC_INTERNAL_STATE] & 0x1) {
452                regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
453                newVal = 0;
454            } else {
455                regs[APIC_INTERNAL_STATE] |= ULL(0x1);
456                return;
457            }
458
459        }
460        break;
461      case APIC_INTERRUPT_COMMAND_LOW:
462        panic("Local APIC Interrupt Command low"
463                " register unimplemented.\n");
464        break;
465      case APIC_INTERRUPT_COMMAND_HIGH:
466        panic("Local APIC Interrupt Command high"
467                " register unimplemented.\n");
468        break;
469      case APIC_LVT_TIMER:
470      case APIC_LVT_THERMAL_SENSOR:
471      case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
472      case APIC_LVT_LINT0:
473      case APIC_LVT_LINT1:
474      case APIC_LVT_ERROR:
475        {
476            uint64_t readOnlyMask = (1 << 12) | (1 << 14);
477            newVal = (val & ~readOnlyMask) |
478                     (regs[reg] & readOnlyMask);
479        }
480        break;
481      case APIC_INITIAL_COUNT:
482        {
483            assert(clock);
484            newVal = bits(val, 31, 0);
485            // Compute how many timer ticks we're being programmed for.
486            uint64_t newCount = newVal *
487                (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
488            // Schedule on the edge of the next tick plus the new count.
489            Tick offset = curTick % clock;
490            if (offset) {
491                reschedule(apicTimerEvent,
492                        curTick + (newCount + 1) * clock - offset, true);
493            } else {
494                reschedule(apicTimerEvent,
495                        curTick + newCount * clock, true);
496            }
497        }
498        break;
499      case APIC_CURRENT_COUNT:
500        //Local APIC Current Count register is read only.
501        return;
502      case APIC_DIVIDE_CONFIGURATION:
503        newVal = val & 0xB;
504        break;
505      default:
506        break;
507    }
508    regs[reg] = newVal;
509    return;
510}
511
512
513X86ISA::Interrupts::Interrupts(Params * p) :
514    BasicPioDevice(p), IntDev(this), latency(p->pio_latency), clock(0),
515    apicTimerEvent(this),
516    pendingSmi(false), smiVector(0),
517    pendingNmi(false), nmiVector(0),
518    pendingExtInt(false), extIntVector(0),
519    pendingInit(false), initVector(0),
520    pendingUnmaskableInt(false)
521{
522    pioSize = PageBytes;
523    memset(regs, 0, sizeof(regs));
524    //Set the local apic DFR to the flat model.
525    regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1);
526    ISRV = 0;
527    IRRV = 0;
528}
529
530
531bool
532X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
533{
534    RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
535    if (pendingUnmaskableInt) {
536        DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
537        return true;
538    }
539    if (rflags.intf) {
540        if (pendingExtInt) {
541            DPRINTF(LocalApic, "Reported pending external interrupt.\n");
542            return true;
543        }
544        if (IRRV > ISRV && bits(IRRV, 7, 4) >
545               bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
546            DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
547            return true;
548        }
549    }
550    return false;
551}
552
553Fault
554X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
555{
556    assert(checkInterrupts(tc));
557    // These are all probably fairly uncommon, so we'll make them easier to
558    // check for.
559    if (pendingUnmaskableInt) {
560        if (pendingSmi) {
561            DPRINTF(LocalApic, "Generated SMI fault object.\n");
562            return new SystemManagementInterrupt();
563        } else if (pendingNmi) {
564            DPRINTF(LocalApic, "Generated NMI fault object.\n");
565            return new NonMaskableInterrupt(nmiVector);
566        } else if (pendingInit) {
567            DPRINTF(LocalApic, "Generated INIT fault object.\n");
568            return new InitInterrupt(initVector);
569        } else {
570            panic("pendingUnmaskableInt set, but no unmaskable "
571                    "ints were pending.\n");
572            return NoFault;
573        }
574    } else if (pendingExtInt) {
575        DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
576        return new ExternalInterrupt(extIntVector);
577    } else {
578        DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
579        // The only thing left are fixed and lowest priority interrupts.
580        return new ExternalInterrupt(IRRV);
581    }
582}
583
584void
585X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
586{
587    assert(checkInterrupts(tc));
588    if (pendingUnmaskableInt) {
589        if (pendingSmi) {
590            DPRINTF(LocalApic, "SMI sent to core.\n");
591            pendingSmi = false;
592        } else if (pendingNmi) {
593            DPRINTF(LocalApic, "NMI sent to core.\n");
594            pendingNmi = false;
595        } else if (pendingInit) {
596            DPRINTF(LocalApic, "Init sent to core.\n");
597            pendingInit = false;
598        }
599        if (!(pendingSmi || pendingNmi || pendingInit))
600            pendingUnmaskableInt = false;
601    } else if (pendingExtInt) {
602        pendingExtInt = false;
603    } else {
604        DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
605        // Mark the interrupt as "in service".
606        ISRV = IRRV;
607        setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
608        // Clear it out of the IRR.
609        clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
610        updateIRRV();
611    }
612}
613
614X86ISA::Interrupts *
615X86LocalApicParams::create()
616{
617    return new X86ISA::Interrupts(this);
618}
619