interrupts.cc revision 5898:541097c69e22 
1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use.  Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
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17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 *     Director of Intellectual Property Licensing
21 *     Office of Strategy and Technology
22 *     Hewlett-Packard Company
23 *     1501 Page Mill Road
24 *     Palo Alto, California  94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer.  Redistributions
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31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
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33 * this software without specific prior written permission.  No right of
34 * sublicense is granted herewith.  Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses.  Derivatives of the software may be shared with
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38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/apicregs.hh"
59#include "arch/x86/interrupts.hh"
60#include "arch/x86/intmessage.hh"
61#include "cpu/base.hh"
62#include "mem/packet_access.hh"
63
64int
65divideFromConf(uint32_t conf)
66{
67    // This figures out what division we want from the division configuration
68    // register in the local APIC. The encoding is a little odd but it can
69    // be deciphered fairly easily.
70    int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
71    shift = (shift + 1) % 8;
72    return 1 << shift;
73}
74
75namespace X86ISA
76{
77
78ApicRegIndex
79decodeAddr(Addr paddr)
80{
81    ApicRegIndex regNum;
82    paddr &= ~mask(3);
83    switch (paddr)
84    {
85      case 0x20:
86        regNum = APIC_ID;
87        break;
88      case 0x30:
89        regNum = APIC_VERSION;
90        break;
91      case 0x80:
92        regNum = APIC_TASK_PRIORITY;
93        break;
94      case 0x90:
95        regNum = APIC_ARBITRATION_PRIORITY;
96        break;
97      case 0xA0:
98        regNum = APIC_PROCESSOR_PRIORITY;
99        break;
100      case 0xB0:
101        regNum = APIC_EOI;
102        break;
103      case 0xD0:
104        regNum = APIC_LOGICAL_DESTINATION;
105        break;
106      case 0xE0:
107        regNum = APIC_DESTINATION_FORMAT;
108        break;
109      case 0xF0:
110        regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
111        break;
112      case 0x100:
113      case 0x108:
114      case 0x110:
115      case 0x118:
116      case 0x120:
117      case 0x128:
118      case 0x130:
119      case 0x138:
120      case 0x140:
121      case 0x148:
122      case 0x150:
123      case 0x158:
124      case 0x160:
125      case 0x168:
126      case 0x170:
127      case 0x178:
128        regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
129        break;
130      case 0x180:
131      case 0x188:
132      case 0x190:
133      case 0x198:
134      case 0x1A0:
135      case 0x1A8:
136      case 0x1B0:
137      case 0x1B8:
138      case 0x1C0:
139      case 0x1C8:
140      case 0x1D0:
141      case 0x1D8:
142      case 0x1E0:
143      case 0x1E8:
144      case 0x1F0:
145      case 0x1F8:
146        regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
147        break;
148      case 0x200:
149      case 0x208:
150      case 0x210:
151      case 0x218:
152      case 0x220:
153      case 0x228:
154      case 0x230:
155      case 0x238:
156      case 0x240:
157      case 0x248:
158      case 0x250:
159      case 0x258:
160      case 0x260:
161      case 0x268:
162      case 0x270:
163      case 0x278:
164        regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
165        break;
166      case 0x280:
167        regNum = APIC_ERROR_STATUS;
168        break;
169      case 0x300:
170        regNum = APIC_INTERRUPT_COMMAND_LOW;
171        break;
172      case 0x310:
173        regNum = APIC_INTERRUPT_COMMAND_HIGH;
174        break;
175      case 0x320:
176        regNum = APIC_LVT_TIMER;
177        break;
178      case 0x330:
179        regNum = APIC_LVT_THERMAL_SENSOR;
180        break;
181      case 0x340:
182        regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
183        break;
184      case 0x350:
185        regNum = APIC_LVT_LINT0;
186        break;
187      case 0x360:
188        regNum = APIC_LVT_LINT1;
189        break;
190      case 0x370:
191        regNum = APIC_LVT_ERROR;
192        break;
193      case 0x380:
194        regNum = APIC_INITIAL_COUNT;
195        break;
196      case 0x390:
197        regNum = APIC_CURRENT_COUNT;
198        break;
199      case 0x3E0:
200        regNum = APIC_DIVIDE_CONFIGURATION;
201        break;
202      default:
203        // A reserved register field.
204        panic("Accessed reserved register field %#x.\n", paddr);
205        break;
206    }
207    return regNum;
208}
209}
210
211Tick
212X86ISA::Interrupts::read(PacketPtr pkt)
213{
214    Addr offset = pkt->getAddr() - pioAddr;
215    //Make sure we're at least only accessing one register.
216    if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
217        panic("Accessed more than one register at a time in the APIC!\n");
218    ApicRegIndex reg = decodeAddr(offset);
219    uint32_t val = htog(readReg(reg));
220    DPRINTF(LocalApic,
221            "Reading Local APIC register %d at offset %#x as %#x.\n",
222            reg, offset, val);
223    pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
224    pkt->makeAtomicResponse();
225    return latency;
226}
227
228Tick
229X86ISA::Interrupts::write(PacketPtr pkt)
230{
231    Addr offset = pkt->getAddr() - pioAddr;
232    //Make sure we're at least only accessing one register.
233    if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
234        panic("Accessed more than one register at a time in the APIC!\n");
235    ApicRegIndex reg = decodeAddr(offset);
236    uint32_t val = regs[reg];
237    pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
238    DPRINTF(LocalApic,
239            "Writing Local APIC register %d at offset %#x as %#x.\n",
240            reg, offset, gtoh(val));
241    setReg(reg, gtoh(val));
242    pkt->makeAtomicResponse();
243    return latency;
244}
245void
246X86ISA::Interrupts::requestInterrupt(uint8_t vector,
247        uint8_t deliveryMode, bool level)
248{
249    /*
250     * Fixed and lowest-priority delivery mode interrupts are handled
251     * using the IRR/ISR registers, checking against the TPR, etc.
252     * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
253     */
254    if (deliveryMode == DeliveryMode::Fixed ||
255            deliveryMode == DeliveryMode::LowestPriority) {
256        DPRINTF(LocalApic, "Interrupt is an %s.\n",
257                DeliveryMode::names[deliveryMode]);
258        // Queue up the interrupt in the IRR.
259        if (vector > IRRV)
260            IRRV = vector;
261        if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
262            setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
263            if (level) {
264                setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
265            } else {
266                clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
267            }
268        }
269    } else if (!DeliveryMode::isReserved(deliveryMode)) {
270        DPRINTF(LocalApic, "Interrupt is an %s.\n",
271                DeliveryMode::names[deliveryMode]);
272        if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
273            pendingUnmaskableInt = pendingSmi = true;
274            smiVector = vector;
275        } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
276            pendingUnmaskableInt = pendingNmi = true;
277            nmiVector = vector;
278        } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
279            pendingExtInt = true;
280            extIntVector = vector;
281        } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
282            pendingUnmaskableInt = pendingInit = true;
283            initVector = vector;
284        }
285    }
286    cpu->wakeup();
287}
288
289Tick
290X86ISA::Interrupts::recvMessage(PacketPtr pkt)
291{
292    uint8_t id = 0;
293    Addr offset = pkt->getAddr() - x86InterruptAddress(id, 0);
294    assert(pkt->cmd == MemCmd::MessageReq);
295    switch(offset)
296    {
297      case 0:
298        {
299            TriggerIntMessage message = pkt->get<TriggerIntMessage>();
300            DPRINTF(LocalApic,
301                    "Got Trigger Interrupt message with vector %#x.\n",
302                    message.vector);
303            // Make sure we're really supposed to get this.
304            assert((message.destMode == 0 && message.destination == id) ||
305                   (bits((int)message.destination, id)));
306
307            requestInterrupt(message.vector,
308                    message.deliveryMode, message.trigger);
309        }
310        break;
311      default:
312        panic("Local apic got unknown interrupt message at offset %#x.\n",
313                offset);
314        break;
315    }
316    delete pkt->req;
317    delete pkt;
318    return latency;
319}
320
321
322uint32_t
323X86ISA::Interrupts::readReg(ApicRegIndex reg)
324{
325    if (reg >= APIC_TRIGGER_MODE(0) &&
326            reg <= APIC_TRIGGER_MODE(15)) {
327        panic("Local APIC Trigger Mode registers are unimplemented.\n");
328    }
329    switch (reg) {
330      case APIC_ARBITRATION_PRIORITY:
331        panic("Local APIC Arbitration Priority register unimplemented.\n");
332        break;
333      case APIC_PROCESSOR_PRIORITY:
334        panic("Local APIC Processor Priority register unimplemented.\n");
335        break;
336      case APIC_ERROR_STATUS:
337        regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
338        break;
339      case APIC_INTERRUPT_COMMAND_LOW:
340        panic("Local APIC Interrupt Command low"
341                " register unimplemented.\n");
342        break;
343      case APIC_INTERRUPT_COMMAND_HIGH:
344        panic("Local APIC Interrupt Command high"
345                " register unimplemented.\n");
346        break;
347      case APIC_CURRENT_COUNT:
348        {
349            if (apicTimerEvent.scheduled()) {
350                assert(clock);
351                // Compute how many m5 ticks happen per count.
352                uint64_t ticksPerCount = clock *
353                    divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
354                // Compute how many m5 ticks are left.
355                uint64_t val = apicTimerEvent.when() - curTick;
356                // Turn that into a count.
357                val = (val + ticksPerCount - 1) / ticksPerCount;
358                return val;
359            } else {
360                return 0;
361            }
362        }
363      default:
364        break;
365    }
366    return regs[reg];
367}
368
369void
370X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
371{
372    uint32_t newVal = val;
373    if (reg >= APIC_IN_SERVICE(0) &&
374            reg <= APIC_IN_SERVICE(15)) {
375        panic("Local APIC In-Service registers are unimplemented.\n");
376    }
377    if (reg >= APIC_TRIGGER_MODE(0) &&
378            reg <= APIC_TRIGGER_MODE(15)) {
379        panic("Local APIC Trigger Mode registers are unimplemented.\n");
380    }
381    if (reg >= APIC_INTERRUPT_REQUEST(0) &&
382            reg <= APIC_INTERRUPT_REQUEST(15)) {
383        panic("Local APIC Interrupt Request registers "
384                "are unimplemented.\n");
385    }
386    switch (reg) {
387      case APIC_ID:
388        newVal = val & 0xFF;
389        break;
390      case APIC_VERSION:
391        // The Local APIC Version register is read only.
392        return;
393      case APIC_TASK_PRIORITY:
394        newVal = val & 0xFF;
395        break;
396      case APIC_ARBITRATION_PRIORITY:
397        panic("Local APIC Arbitration Priority register unimplemented.\n");
398        break;
399      case APIC_PROCESSOR_PRIORITY:
400        panic("Local APIC Processor Priority register unimplemented.\n");
401        break;
402      case APIC_EOI:
403        // Remove the interrupt that just completed from the local apic state.
404        clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
405        updateISRV();
406        return;
407      case APIC_LOGICAL_DESTINATION:
408        newVal = val & 0xFF000000;
409        break;
410      case APIC_DESTINATION_FORMAT:
411        newVal = val | 0x0FFFFFFF;
412        break;
413      case APIC_SPURIOUS_INTERRUPT_VECTOR:
414        regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
415        regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
416        if (val & (1 << 9))
417            warn("Focus processor checking not implemented.\n");
418        break;
419      case APIC_ERROR_STATUS:
420        {
421            if (regs[APIC_INTERNAL_STATE] & 0x1) {
422                regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
423                newVal = 0;
424            } else {
425                regs[APIC_INTERNAL_STATE] |= ULL(0x1);
426                return;
427            }
428
429        }
430        break;
431      case APIC_INTERRUPT_COMMAND_LOW:
432        panic("Local APIC Interrupt Command low"
433                " register unimplemented.\n");
434        break;
435      case APIC_INTERRUPT_COMMAND_HIGH:
436        panic("Local APIC Interrupt Command high"
437                " register unimplemented.\n");
438        break;
439      case APIC_LVT_TIMER:
440      case APIC_LVT_THERMAL_SENSOR:
441      case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
442      case APIC_LVT_LINT0:
443      case APIC_LVT_LINT1:
444      case APIC_LVT_ERROR:
445        {
446            uint64_t readOnlyMask = (1 << 12) | (1 << 14);
447            newVal = (val & ~readOnlyMask) |
448                     (regs[reg] & readOnlyMask);
449        }
450        break;
451      case APIC_INITIAL_COUNT:
452        {
453            assert(clock);
454            newVal = bits(val, 31, 0);
455            // Compute how many timer ticks we're being programmed for.
456            uint64_t newCount = newVal *
457                (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
458            // Schedule on the edge of the next tick plus the new count.
459            Tick offset = curTick % clock;
460            if (offset) {
461                reschedule(apicTimerEvent,
462                        curTick + (newCount + 1) * clock - offset, true);
463            } else {
464                reschedule(apicTimerEvent,
465                        curTick + newCount * clock, true);
466            }
467        }
468        break;
469      case APIC_CURRENT_COUNT:
470        //Local APIC Current Count register is read only.
471        return;
472      case APIC_DIVIDE_CONFIGURATION:
473        newVal = val & 0xB;
474        break;
475      default:
476        break;
477    }
478    regs[reg] = newVal;
479    return;
480}
481
482bool
483X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
484{
485    RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
486    if (pendingUnmaskableInt) {
487        DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
488        return true;
489    }
490    if (rflags.intf) {
491        if (pendingExtInt) {
492            DPRINTF(LocalApic, "Reported pending external interrupt.\n");
493            return true;
494        }
495        if (IRRV > ISRV && bits(IRRV, 7, 4) >
496               bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
497            DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
498            return true;
499        }
500    }
501    return false;
502}
503
504Fault
505X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
506{
507    assert(checkInterrupts(tc));
508    // These are all probably fairly uncommon, so we'll make them easier to
509    // check for.
510    if (pendingUnmaskableInt) {
511        if (pendingSmi) {
512            DPRINTF(LocalApic, "Generated SMI fault object.\n");
513            return new SystemManagementInterrupt();
514        } else if (pendingNmi) {
515            DPRINTF(LocalApic, "Generated NMI fault object.\n");
516            return new NonMaskableInterrupt(nmiVector);
517        } else if (pendingInit) {
518            DPRINTF(LocalApic, "Generated INIT fault object.\n");
519            return new InitInterrupt(initVector);
520        } else {
521            panic("pendingUnmaskableInt set, but no unmaskable "
522                    "ints were pending.\n");
523            return NoFault;
524        }
525    } else if (pendingExtInt) {
526        DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
527        return new ExternalInterrupt(extIntVector);
528    } else {
529        DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
530        // The only thing left are fixed and lowest priority interrupts.
531        return new ExternalInterrupt(IRRV);
532    }
533}
534
535void
536X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
537{
538    assert(checkInterrupts(tc));
539    if (pendingUnmaskableInt) {
540        if (pendingSmi) {
541            DPRINTF(LocalApic, "SMI sent to core.\n");
542            pendingSmi = false;
543        } else if (pendingNmi) {
544            DPRINTF(LocalApic, "NMI sent to core.\n");
545            pendingNmi = false;
546        } else if (pendingInit) {
547            DPRINTF(LocalApic, "Init sent to core.\n");
548            pendingInit = false;
549        }
550        if (!(pendingSmi || pendingNmi || pendingInit))
551            pendingUnmaskableInt = false;
552    } else if (pendingExtInt) {
553        pendingExtInt = false;
554    } else {
555        DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
556        // Mark the interrupt as "in service".
557        ISRV = IRRV;
558        setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
559        // Clear it out of the IRR.
560        clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
561        updateIRRV();
562    }
563}
564
565X86ISA::Interrupts *
566X86LocalApicParams::create()
567{
568    return new X86ISA::Interrupts(this);
569}
570