interrupts.cc revision 5848 
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544151Sgblack@eecs.umich.edu *
554151Sgblack@eecs.umich.edu * Authors: Gabe Black
564120Sgblack@eecs.umich.edu */
574120Sgblack@eecs.umich.edu
584120Sgblack@eecs.umich.edu#include "arch/x86/apicregs.hh"
59#include "arch/x86/interrupts.hh"
60#include "arch/x86/intmessage.hh"
61#include "cpu/base.hh"
62#include "mem/packet_access.hh"
63
64int
65divideFromConf(uint32_t conf)
66{
67    // This figures out what division we want from the division configuration
68    // register in the local APIC. The encoding is a little odd but it can
69    // be deciphered fairly easily.
70    int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
71    shift = (shift + 1) % 8;
72    return 1 << shift;
73}
74
75namespace X86ISA
76{
77
78ApicRegIndex
79decodeAddr(Addr paddr)
80{
81    ApicRegIndex regNum;
82    paddr &= ~mask(3);
83    switch (paddr)
84    {
85      case 0x20:
86        regNum = APIC_ID;
87        break;
88      case 0x30:
89        regNum = APIC_VERSION;
90        break;
91      case 0x80:
92        regNum = APIC_TASK_PRIORITY;
93        break;
94      case 0x90:
95        regNum = APIC_ARBITRATION_PRIORITY;
96        break;
97      case 0xA0:
98        regNum = APIC_PROCESSOR_PRIORITY;
99        break;
100      case 0xB0:
101        regNum = APIC_EOI;
102        break;
103      case 0xD0:
104        regNum = APIC_LOGICAL_DESTINATION;
105        break;
106      case 0xE0:
107        regNum = APIC_DESTINATION_FORMAT;
108        break;
109      case 0xF0:
110        regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
111        break;
112      case 0x100:
113      case 0x108:
114      case 0x110:
115      case 0x118:
116      case 0x120:
117      case 0x128:
118      case 0x130:
119      case 0x138:
120      case 0x140:
121      case 0x148:
122      case 0x150:
123      case 0x158:
124      case 0x160:
125      case 0x168:
126      case 0x170:
127      case 0x178:
128        regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
129        break;
130      case 0x180:
131      case 0x188:
132      case 0x190:
133      case 0x198:
134      case 0x1A0:
135      case 0x1A8:
136      case 0x1B0:
137      case 0x1B8:
138      case 0x1C0:
139      case 0x1C8:
140      case 0x1D0:
141      case 0x1D8:
142      case 0x1E0:
143      case 0x1E8:
144      case 0x1F0:
145      case 0x1F8:
146        regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
147        break;
148      case 0x200:
149      case 0x208:
150      case 0x210:
151      case 0x218:
152      case 0x220:
153      case 0x228:
154      case 0x230:
155      case 0x238:
156      case 0x240:
157      case 0x248:
158      case 0x250:
159      case 0x258:
160      case 0x260:
161      case 0x268:
162      case 0x270:
163      case 0x278:
164        regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
165        break;
166      case 0x280:
167        regNum = APIC_ERROR_STATUS;
168        break;
169      case 0x300:
170        regNum = APIC_INTERRUPT_COMMAND_LOW;
171        break;
172      case 0x310:
173        regNum = APIC_INTERRUPT_COMMAND_HIGH;
174        break;
175      case 0x320:
176        regNum = APIC_LVT_TIMER;
177        break;
178      case 0x330:
179        regNum = APIC_LVT_THERMAL_SENSOR;
180        break;
181      case 0x340:
182        regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
183        break;
184      case 0x350:
185        regNum = APIC_LVT_LINT0;
186        break;
187      case 0x360:
188        regNum = APIC_LVT_LINT1;
189        break;
190      case 0x370:
191        regNum = APIC_LVT_ERROR;
192        break;
193      case 0x380:
194        regNum = APIC_INITIAL_COUNT;
195        break;
196      case 0x390:
197        regNum = APIC_CURRENT_COUNT;
198        break;
199      case 0x3E0:
200        regNum = APIC_DIVIDE_CONFIGURATION;
201        break;
202      default:
203        // A reserved register field.
204        panic("Accessed reserved register field %#x.\n", paddr);
205        break;
206    }
207    return regNum;
208}
209}
210
211Tick
212X86ISA::Interrupts::read(PacketPtr pkt)
213{
214    Addr offset = pkt->getAddr() - pioAddr;
215    //Make sure we're at least only accessing one register.
216    if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
217        panic("Accessed more than one register at a time in the APIC!\n");
218    ApicRegIndex reg = decodeAddr(offset);
219    uint32_t val = htog(readReg(reg));
220    DPRINTF(LocalApic,
221            "Reading Local APIC register %d at offset %#x as %#x.\n",
222            reg, offset, val);
223    pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
224    return latency;
225}
226
227Tick
228X86ISA::Interrupts::write(PacketPtr pkt)
229{
230    Addr offset = pkt->getAddr() - pioAddr;
231    //Make sure we're at least only accessing one register.
232    if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
233        panic("Accessed more than one register at a time in the APIC!\n");
234    ApicRegIndex reg = decodeAddr(offset);
235    uint32_t val = regs[reg];
236    pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
237    DPRINTF(LocalApic,
238            "Writing Local APIC register %d at offset %#x as %#x.\n",
239            reg, offset, gtoh(val));
240    setReg(reg, gtoh(val));
241    return latency;
242}
243void
244X86ISA::Interrupts::requestInterrupt(uint8_t vector,
245        uint8_t deliveryMode, bool level)
246{
247    /*
248     * Fixed and lowest-priority delivery mode interrupts are handled
249     * using the IRR/ISR registers, checking against the TPR, etc.
250     * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
251     */
252    if (deliveryMode == DeliveryMode::Fixed ||
253            deliveryMode == DeliveryMode::LowestPriority) {
254        DPRINTF(LocalApic, "Interrupt is an %s.\n",
255                DeliveryMode::names[deliveryMode]);
256        // Queue up the interrupt in the IRR.
257        if (vector > IRRV)
258            IRRV = vector;
259        if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
260            setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
261            if (level) {
262                setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
263            } else {
264                clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
265            }
266        }
267    } else if (!DeliveryMode::isReserved(deliveryMode)) {
268        DPRINTF(LocalApic, "Interrupt is an %s.\n",
269                DeliveryMode::names[deliveryMode]);
270        if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
271            pendingUnmaskableInt = pendingSmi = true;
272            smiVector = vector;
273        } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
274            pendingUnmaskableInt = pendingNmi = true;
275            nmiVector = vector;
276        } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
277            pendingExtInt = true;
278            extIntVector = vector;
279        } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
280            pendingUnmaskableInt = pendingInit = true;
281            initVector = vector;
282        }
283    }
284    cpu->wakeup();
285}
286
287Tick
288X86ISA::Interrupts::recvMessage(PacketPtr pkt)
289{
290    uint8_t id = 0;
291    Addr offset = pkt->getAddr() - x86InterruptAddress(id, 0);
292    assert(pkt->cmd == MemCmd::MessageReq);
293    switch(offset)
294    {
295      case 0:
296        {
297            TriggerIntMessage message = pkt->get<TriggerIntMessage>();
298            DPRINTF(LocalApic,
299                    "Got Trigger Interrupt message with vector %#x.\n",
300                    message.vector);
301            // Make sure we're really supposed to get this.
302            assert((message.destMode == 0 && message.destination == id) ||
303                   (bits((int)message.destination, id)));
304
305            requestInterrupt(message.vector,
306                    message.deliveryMode, message.trigger);
307        }
308        break;
309      default:
310        panic("Local apic got unknown interrupt message at offset %#x.\n",
311                offset);
312        break;
313    }
314    delete pkt->req;
315    delete pkt;
316    return latency;
317}
318
319
320uint32_t
321X86ISA::Interrupts::readReg(ApicRegIndex reg)
322{
323    if (reg >= APIC_TRIGGER_MODE(0) &&
324            reg <= APIC_TRIGGER_MODE(15)) {
325        panic("Local APIC Trigger Mode registers are unimplemented.\n");
326    }
327    switch (reg) {
328      case APIC_ARBITRATION_PRIORITY:
329        panic("Local APIC Arbitration Priority register unimplemented.\n");
330        break;
331      case APIC_PROCESSOR_PRIORITY:
332        panic("Local APIC Processor Priority register unimplemented.\n");
333        break;
334      case APIC_ERROR_STATUS:
335        regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
336        break;
337      case APIC_INTERRUPT_COMMAND_LOW:
338        panic("Local APIC Interrupt Command low"
339                " register unimplemented.\n");
340        break;
341      case APIC_INTERRUPT_COMMAND_HIGH:
342        panic("Local APIC Interrupt Command high"
343                " register unimplemented.\n");
344        break;
345      case APIC_CURRENT_COUNT:
346        {
347            if (apicTimerEvent.scheduled()) {
348                assert(clock);
349                // Compute how many m5 ticks happen per count.
350                uint64_t ticksPerCount = clock *
351                    divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]);
352                // Compute how many m5 ticks are left.
353                uint64_t val = apicTimerEvent.when() - curTick;
354                // Turn that into a count.
355                val = (val + ticksPerCount - 1) / ticksPerCount;
356                return val;
357            } else {
358                return 0;
359            }
360        }
361      default:
362        break;
363    }
364    return regs[reg];
365}
366
367void
368X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
369{
370    uint32_t newVal = val;
371    if (reg >= APIC_IN_SERVICE(0) &&
372            reg <= APIC_IN_SERVICE(15)) {
373        panic("Local APIC In-Service registers are unimplemented.\n");
374    }
375    if (reg >= APIC_TRIGGER_MODE(0) &&
376            reg <= APIC_TRIGGER_MODE(15)) {
377        panic("Local APIC Trigger Mode registers are unimplemented.\n");
378    }
379    if (reg >= APIC_INTERRUPT_REQUEST(0) &&
380            reg <= APIC_INTERRUPT_REQUEST(15)) {
381        panic("Local APIC Interrupt Request registers "
382                "are unimplemented.\n");
383    }
384    switch (reg) {
385      case APIC_ID:
386        newVal = val & 0xFF;
387        break;
388      case APIC_VERSION:
389        // The Local APIC Version register is read only.
390        return;
391      case APIC_TASK_PRIORITY:
392        newVal = val & 0xFF;
393        break;
394      case APIC_ARBITRATION_PRIORITY:
395        panic("Local APIC Arbitration Priority register unimplemented.\n");
396        break;
397      case APIC_PROCESSOR_PRIORITY:
398        panic("Local APIC Processor Priority register unimplemented.\n");
399        break;
400      case APIC_EOI:
401        // Remove the interrupt that just completed from the local apic state.
402        clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
403        updateISRV();
404        return;
405      case APIC_LOGICAL_DESTINATION:
406        newVal = val & 0xFF000000;
407        break;
408      case APIC_DESTINATION_FORMAT:
409        newVal = val | 0x0FFFFFFF;
410        break;
411      case APIC_SPURIOUS_INTERRUPT_VECTOR:
412        regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
413        regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
414        if (val & (1 << 9))
415            warn("Focus processor checking not implemented.\n");
416        break;
417      case APIC_ERROR_STATUS:
418        {
419            if (regs[APIC_INTERNAL_STATE] & 0x1) {
420                regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
421                newVal = 0;
422            } else {
423                regs[APIC_INTERNAL_STATE] |= ULL(0x1);
424                return;
425            }
426
427        }
428        break;
429      case APIC_INTERRUPT_COMMAND_LOW:
430        panic("Local APIC Interrupt Command low"
431                " register unimplemented.\n");
432        break;
433      case APIC_INTERRUPT_COMMAND_HIGH:
434        panic("Local APIC Interrupt Command high"
435                " register unimplemented.\n");
436        break;
437      case APIC_LVT_TIMER:
438      case APIC_LVT_THERMAL_SENSOR:
439      case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
440      case APIC_LVT_LINT0:
441      case APIC_LVT_LINT1:
442      case APIC_LVT_ERROR:
443        {
444            uint64_t readOnlyMask = (1 << 12) | (1 << 14);
445            newVal = (val & ~readOnlyMask) |
446                     (regs[reg] & readOnlyMask);
447        }
448        break;
449      case APIC_INITIAL_COUNT:
450        {
451            assert(clock);
452            newVal = bits(val, 31, 0);
453            // Compute how many timer ticks we're being programmed for.
454            uint64_t newCount = newVal *
455                (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
456            // Schedule on the edge of the next tick plus the new count.
457            Tick offset = curTick % clock;
458            if (offset) {
459                reschedule(apicTimerEvent,
460                        curTick + (newCount + 1) * clock - offset, true);
461            } else {
462                reschedule(apicTimerEvent,
463                        curTick + newCount * clock, true);
464            }
465        }
466        break;
467      case APIC_CURRENT_COUNT:
468        //Local APIC Current Count register is read only.
469        return;
470      case APIC_DIVIDE_CONFIGURATION:
471        newVal = val & 0xB;
472        break;
473      default:
474        break;
475    }
476    regs[reg] = newVal;
477    return;
478}
479
480bool
481X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
482{
483    RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
484    if (pendingUnmaskableInt) {
485        DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
486        return true;
487    }
488    if (rflags.intf) {
489        if (pendingExtInt) {
490            DPRINTF(LocalApic, "Reported pending external interrupt.\n");
491            return true;
492        }
493        if (IRRV > ISRV && bits(IRRV, 7, 4) >
494               bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
495            DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
496            return true;
497        }
498    }
499    return false;
500}
501
502Fault
503X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
504{
505    assert(checkInterrupts(tc));
506    // These are all probably fairly uncommon, so we'll make them easier to
507    // check for.
508    if (pendingUnmaskableInt) {
509        if (pendingSmi) {
510            DPRINTF(LocalApic, "Generated SMI fault object.\n");
511            return new SystemManagementInterrupt();
512        } else if (pendingNmi) {
513            DPRINTF(LocalApic, "Generated NMI fault object.\n");
514            return new NonMaskableInterrupt(nmiVector);
515        } else if (pendingInit) {
516            DPRINTF(LocalApic, "Generated INIT fault object.\n");
517            return new InitInterrupt(initVector);
518        } else {
519            panic("pendingUnmaskableInt set, but no unmaskable "
520                    "ints were pending.\n");
521            return NoFault;
522        }
523    } else if (pendingExtInt) {
524        DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
525        return new ExternalInterrupt(extIntVector);
526    } else {
527        DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
528        // The only thing left are fixed and lowest priority interrupts.
529        return new ExternalInterrupt(IRRV);
530    }
531}
532
533void
534X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
535{
536    assert(checkInterrupts(tc));
537    if (pendingUnmaskableInt) {
538        if (pendingSmi) {
539            DPRINTF(LocalApic, "SMI sent to core.\n");
540            pendingSmi = false;
541        } else if (pendingNmi) {
542            DPRINTF(LocalApic, "NMI sent to core.\n");
543            pendingNmi = false;
544        } else if (pendingInit) {
545            DPRINTF(LocalApic, "Init sent to core.\n");
546            pendingInit = false;
547        }
548        if (!(pendingSmi || pendingNmi || pendingInit))
549            pendingUnmaskableInt = false;
550    } else if (pendingExtInt) {
551        pendingExtInt = false;
552    } else {
553        DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
554        // Mark the interrupt as "in service".
555        ISRV = IRRV;
556        setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
557        // Clear it out of the IRR.
558        clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
559        updateIRRV();
560    }
561}
562
563X86ISA::Interrupts *
564X86LocalApicParams::create()
565{
566    return new X86ISA::Interrupts(this);
567}
568