interrupts.cc revision 5704:98224505352a 
1/*
2 * Copyright (c) 2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use.  Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
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17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 *     Director of Intellectual Property Licensing
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23 *     1501 Page Mill Road
24 *     Palo Alto, California  94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer.  Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
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31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission.  No right of
34 * sublicense is granted herewith.  Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses.  Derivatives of the software may be shared with
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38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/apicregs.hh"
59#include "arch/x86/interrupts.hh"
60#include "arch/x86/intmessage.hh"
61#include "cpu/base.hh"
62#include "mem/packet_access.hh"
63
64int
65divideFromConf(uint32_t conf)
66{
67    // This figures out what division we want from the division configuration
68    // register in the local APIC. The encoding is a little odd but it can
69    // be deciphered fairly easily.
70    int shift = ((conf & 0x8) >> 1) | (conf & 0x3);
71    shift = (shift + 1) % 8;
72    return 1 << shift;
73}
74
75namespace X86ISA
76{
77
78ApicRegIndex
79decodeAddr(Addr paddr)
80{
81    ApicRegIndex regNum;
82    paddr &= ~mask(3);
83    switch (paddr)
84    {
85      case 0x20:
86        regNum = APIC_ID;
87        break;
88      case 0x30:
89        regNum = APIC_VERSION;
90        break;
91      case 0x80:
92        regNum = APIC_TASK_PRIORITY;
93        break;
94      case 0x90:
95        regNum = APIC_ARBITRATION_PRIORITY;
96        break;
97      case 0xA0:
98        regNum = APIC_PROCESSOR_PRIORITY;
99        break;
100      case 0xB0:
101        regNum = APIC_EOI;
102        break;
103      case 0xD0:
104        regNum = APIC_LOGICAL_DESTINATION;
105        break;
106      case 0xE0:
107        regNum = APIC_DESTINATION_FORMAT;
108        break;
109      case 0xF0:
110        regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
111        break;
112      case 0x100:
113      case 0x108:
114      case 0x110:
115      case 0x118:
116      case 0x120:
117      case 0x128:
118      case 0x130:
119      case 0x138:
120      case 0x140:
121      case 0x148:
122      case 0x150:
123      case 0x158:
124      case 0x160:
125      case 0x168:
126      case 0x170:
127      case 0x178:
128        regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8);
129        break;
130      case 0x180:
131      case 0x188:
132      case 0x190:
133      case 0x198:
134      case 0x1A0:
135      case 0x1A8:
136      case 0x1B0:
137      case 0x1B8:
138      case 0x1C0:
139      case 0x1C8:
140      case 0x1D0:
141      case 0x1D8:
142      case 0x1E0:
143      case 0x1E8:
144      case 0x1F0:
145      case 0x1F8:
146        regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8);
147        break;
148      case 0x200:
149      case 0x208:
150      case 0x210:
151      case 0x218:
152      case 0x220:
153      case 0x228:
154      case 0x230:
155      case 0x238:
156      case 0x240:
157      case 0x248:
158      case 0x250:
159      case 0x258:
160      case 0x260:
161      case 0x268:
162      case 0x270:
163      case 0x278:
164        regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8);
165        break;
166      case 0x280:
167        regNum = APIC_ERROR_STATUS;
168        break;
169      case 0x300:
170        regNum = APIC_INTERRUPT_COMMAND_LOW;
171        break;
172      case 0x310:
173        regNum = APIC_INTERRUPT_COMMAND_HIGH;
174        break;
175      case 0x320:
176        regNum = APIC_LVT_TIMER;
177        break;
178      case 0x330:
179        regNum = APIC_LVT_THERMAL_SENSOR;
180        break;
181      case 0x340:
182        regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
183        break;
184      case 0x350:
185        regNum = APIC_LVT_LINT0;
186        break;
187      case 0x360:
188        regNum = APIC_LVT_LINT1;
189        break;
190      case 0x370:
191        regNum = APIC_LVT_ERROR;
192        break;
193      case 0x380:
194        regNum = APIC_INITIAL_COUNT;
195        break;
196      case 0x390:
197        regNum = APIC_CURRENT_COUNT;
198        break;
199      case 0x3E0:
200        regNum = APIC_DIVIDE_CONFIGURATION;
201        break;
202      default:
203        // A reserved register field.
204        panic("Accessed reserved register field %#x.\n", paddr);
205        break;
206    }
207    return regNum;
208}
209}
210
211Tick
212X86ISA::Interrupts::read(PacketPtr pkt)
213{
214    Addr offset = pkt->getAddr() - pioAddr;
215    //Make sure we're at least only accessing one register.
216    if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
217        panic("Accessed more than one register at a time in the APIC!\n");
218    ApicRegIndex reg = decodeAddr(offset);
219    uint32_t val = htog(readReg(reg));
220    DPRINTF(LocalApic,
221            "Reading Local APIC register %d at offset %#x as %#x.\n",
222            reg, offset, val);
223    pkt->setData(((uint8_t *)&val) + (offset & mask(3)));
224    return latency;
225}
226
227Tick
228X86ISA::Interrupts::write(PacketPtr pkt)
229{
230    Addr offset = pkt->getAddr() - pioAddr;
231    //Make sure we're at least only accessing one register.
232    if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3)))
233        panic("Accessed more than one register at a time in the APIC!\n");
234    ApicRegIndex reg = decodeAddr(offset);
235    uint32_t val = regs[reg];
236    pkt->writeData(((uint8_t *)&val) + (offset & mask(3)));
237    DPRINTF(LocalApic,
238            "Writing Local APIC register %d at offset %#x as %#x.\n",
239            reg, offset, gtoh(val));
240    setReg(reg, gtoh(val));
241    return latency;
242}
243void
244X86ISA::Interrupts::requestInterrupt(uint8_t vector,
245        uint8_t deliveryMode, bool level)
246{
247    /*
248     * Fixed and lowest-priority delivery mode interrupts are handled
249     * using the IRR/ISR registers, checking against the TPR, etc.
250     * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through.
251     */
252    if (deliveryMode == DeliveryMode::Fixed ||
253            deliveryMode == DeliveryMode::LowestPriority) {
254        DPRINTF(LocalApic, "Interrupt is an %s.\n",
255                DeliveryMode::names[deliveryMode]);
256        // Queue up the interrupt in the IRR.
257        if (vector > IRRV)
258            IRRV = vector;
259        if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) {
260            setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector);
261            if (level) {
262                setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
263            } else {
264                clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector);
265            }
266        }
267    } else if (!DeliveryMode::isReserved(deliveryMode)) {
268        DPRINTF(LocalApic, "Interrupt is an %s.\n",
269                DeliveryMode::names[deliveryMode]);
270        if (deliveryMode == DeliveryMode::SMI && !pendingSmi) {
271            pendingUnmaskableInt = pendingSmi = true;
272            smiVector = vector;
273        } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) {
274            pendingUnmaskableInt = pendingNmi = true;
275            nmiVector = vector;
276        } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) {
277            pendingExtInt = true;
278            extIntVector = vector;
279        } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) {
280            pendingUnmaskableInt = pendingInit = true;
281            initVector = vector;
282        }
283    }
284}
285
286Tick
287X86ISA::Interrupts::recvMessage(PacketPtr pkt)
288{
289    uint8_t id = 0;
290    Addr offset = pkt->getAddr() - x86InterruptAddress(id, 0);
291    assert(pkt->cmd == MemCmd::MessageReq);
292    switch(offset)
293    {
294      case 0:
295        {
296            TriggerIntMessage message = pkt->get<TriggerIntMessage>();
297            DPRINTF(LocalApic,
298                    "Got Trigger Interrupt message with vector %#x.\n",
299                    message.vector);
300            // Make sure we're really supposed to get this.
301            assert((message.destMode == 0 && message.destination == id) ||
302                   (bits((int)message.destination, id)));
303
304            requestInterrupt(message.vector,
305                    message.deliveryMode, message.trigger);
306        }
307        break;
308      default:
309        panic("Local apic got unknown interrupt message at offset %#x.\n",
310                offset);
311        break;
312    }
313    delete pkt->req;
314    delete pkt;
315    return latency;
316}
317
318
319uint32_t
320X86ISA::Interrupts::readReg(ApicRegIndex reg)
321{
322    if (reg >= APIC_TRIGGER_MODE(0) &&
323            reg <= APIC_TRIGGER_MODE(15)) {
324        panic("Local APIC Trigger Mode registers are unimplemented.\n");
325    }
326    switch (reg) {
327      case APIC_ARBITRATION_PRIORITY:
328        panic("Local APIC Arbitration Priority register unimplemented.\n");
329        break;
330      case APIC_PROCESSOR_PRIORITY:
331        panic("Local APIC Processor Priority register unimplemented.\n");
332        break;
333      case APIC_ERROR_STATUS:
334        regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
335        break;
336      case APIC_INTERRUPT_COMMAND_LOW:
337        panic("Local APIC Interrupt Command low"
338                " register unimplemented.\n");
339        break;
340      case APIC_INTERRUPT_COMMAND_HIGH:
341        panic("Local APIC Interrupt Command high"
342                " register unimplemented.\n");
343        break;
344      case APIC_CURRENT_COUNT:
345        {
346            assert(clock);
347            uint32_t val = regs[reg] - curTick / clock;
348            val /= (16 * divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]));
349            return val;
350        }
351      default:
352        break;
353    }
354    return regs[reg];
355}
356
357void
358X86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val)
359{
360    uint32_t newVal = val;
361    if (reg >= APIC_IN_SERVICE(0) &&
362            reg <= APIC_IN_SERVICE(15)) {
363        panic("Local APIC In-Service registers are unimplemented.\n");
364    }
365    if (reg >= APIC_TRIGGER_MODE(0) &&
366            reg <= APIC_TRIGGER_MODE(15)) {
367        panic("Local APIC Trigger Mode registers are unimplemented.\n");
368    }
369    if (reg >= APIC_INTERRUPT_REQUEST(0) &&
370            reg <= APIC_INTERRUPT_REQUEST(15)) {
371        panic("Local APIC Interrupt Request registers "
372                "are unimplemented.\n");
373    }
374    switch (reg) {
375      case APIC_ID:
376        newVal = val & 0xFF;
377        break;
378      case APIC_VERSION:
379        // The Local APIC Version register is read only.
380        return;
381      case APIC_TASK_PRIORITY:
382        newVal = val & 0xFF;
383        break;
384      case APIC_ARBITRATION_PRIORITY:
385        panic("Local APIC Arbitration Priority register unimplemented.\n");
386        break;
387      case APIC_PROCESSOR_PRIORITY:
388        panic("Local APIC Processor Priority register unimplemented.\n");
389        break;
390      case APIC_EOI:
391        // Remove the interrupt that just completed from the local apic state.
392        clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
393        updateISRV();
394        return;
395      case APIC_LOGICAL_DESTINATION:
396        newVal = val & 0xFF000000;
397        break;
398      case APIC_DESTINATION_FORMAT:
399        newVal = val | 0x0FFFFFFF;
400        break;
401      case APIC_SPURIOUS_INTERRUPT_VECTOR:
402        regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1);
403        regs[APIC_INTERNAL_STATE] |= val & (1 << 8);
404        if (val & (1 << 9))
405            warn("Focus processor checking not implemented.\n");
406        break;
407      case APIC_ERROR_STATUS:
408        {
409            if (regs[APIC_INTERNAL_STATE] & 0x1) {
410                regs[APIC_INTERNAL_STATE] &= ~ULL(0x1);
411                newVal = 0;
412            } else {
413                regs[APIC_INTERNAL_STATE] |= ULL(0x1);
414                return;
415            }
416
417        }
418        break;
419      case APIC_INTERRUPT_COMMAND_LOW:
420        panic("Local APIC Interrupt Command low"
421                " register unimplemented.\n");
422        break;
423      case APIC_INTERRUPT_COMMAND_HIGH:
424        panic("Local APIC Interrupt Command high"
425                " register unimplemented.\n");
426        break;
427      case APIC_LVT_TIMER:
428      case APIC_LVT_THERMAL_SENSOR:
429      case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS:
430      case APIC_LVT_LINT0:
431      case APIC_LVT_LINT1:
432      case APIC_LVT_ERROR:
433        {
434            uint64_t readOnlyMask = (1 << 12) | (1 << 14);
435            newVal = (val & ~readOnlyMask) |
436                     (regs[reg] & readOnlyMask);
437        }
438        break;
439      case APIC_INITIAL_COUNT:
440        {
441            assert(clock);
442            newVal = bits(val, 31, 0);
443            uint32_t newCount = newVal *
444                (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]) * 16);
445            regs[APIC_CURRENT_COUNT] = newCount + curTick / clock;
446            // Find out how long a "tick" of the timer should take.
447            Tick timerTick = 16 * clock;
448            // Schedule on the edge of the next tick plus the new count.
449            Tick offset = curTick % timerTick;
450            if (offset) {
451                reschedule(apicTimerEvent,
452                        curTick + (newCount + 1) * timerTick - offset, true);
453            } else {
454                reschedule(apicTimerEvent,
455                        curTick + newCount * timerTick, true);
456            }
457        }
458        break;
459      case APIC_CURRENT_COUNT:
460        //Local APIC Current Count register is read only.
461        return;
462      case APIC_DIVIDE_CONFIGURATION:
463        newVal = val & 0xB;
464        break;
465      default:
466        break;
467    }
468    regs[reg] = newVal;
469    return;
470}
471
472bool
473X86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const
474{
475    RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
476    if (pendingUnmaskableInt) {
477        DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n");
478        return true;
479    }
480    if (rflags.intf) {
481        if (pendingExtInt) {
482            DPRINTF(LocalApic, "Reported pending external interrupt.\n");
483            return true;
484        }
485        if (IRRV > ISRV && bits(IRRV, 7, 4) >
486               bits(regs[APIC_TASK_PRIORITY], 7, 4)) {
487            DPRINTF(LocalApic, "Reported pending regular interrupt.\n");
488            return true;
489        }
490    }
491    return false;
492}
493
494Fault
495X86ISA::Interrupts::getInterrupt(ThreadContext *tc)
496{
497    assert(checkInterrupts(tc));
498    // These are all probably fairly uncommon, so we'll make them easier to
499    // check for.
500    if (pendingUnmaskableInt) {
501        if (pendingSmi) {
502            DPRINTF(LocalApic, "Generated SMI fault object.\n");
503            return new SystemManagementInterrupt();
504        } else if (pendingNmi) {
505            DPRINTF(LocalApic, "Generated NMI fault object.\n");
506            return new NonMaskableInterrupt(nmiVector);
507        } else if (pendingInit) {
508            DPRINTF(LocalApic, "Generated INIT fault object.\n");
509            return new InitInterrupt(initVector);
510        } else {
511            panic("pendingUnmaskableInt set, but no unmaskable "
512                    "ints were pending.\n");
513            return NoFault;
514        }
515    } else if (pendingExtInt) {
516        DPRINTF(LocalApic, "Generated external interrupt fault object.\n");
517        return new ExternalInterrupt(extIntVector);
518    } else {
519        DPRINTF(LocalApic, "Generated regular interrupt fault object.\n");
520        // The only thing left are fixed and lowest priority interrupts.
521        return new ExternalInterrupt(IRRV);
522    }
523}
524
525void
526X86ISA::Interrupts::updateIntrInfo(ThreadContext *tc)
527{
528    assert(checkInterrupts(tc));
529    if (pendingUnmaskableInt) {
530        if (pendingSmi) {
531            DPRINTF(LocalApic, "SMI sent to core.\n");
532            pendingSmi = false;
533        } else if (pendingNmi) {
534            DPRINTF(LocalApic, "NMI sent to core.\n");
535            pendingNmi = false;
536        } else if (pendingInit) {
537            DPRINTF(LocalApic, "Init sent to core.\n");
538            pendingInit = false;
539        }
540        if (!(pendingSmi || pendingNmi || pendingInit))
541            pendingUnmaskableInt = false;
542    } else if (pendingExtInt) {
543        pendingExtInt = false;
544    } else {
545        DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV);
546        // Mark the interrupt as "in service".
547        ISRV = IRRV;
548        setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV);
549        // Clear it out of the IRR.
550        clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV);
551        updateIRRV();
552    }
553}
554
555X86ISA::Interrupts *
556X86LocalApicParams::create()
557{
558    return new X86ISA::Interrupts(this);
559}
560