interrupts.cc revision 8781
15647Sgblack@eecs.umich.edu/* 25647Sgblack@eecs.umich.edu * Copyright (c) 2008 The Hewlett-Packard Development Company 35647Sgblack@eecs.umich.edu * All rights reserved. 45647Sgblack@eecs.umich.edu * 57087Snate@binkert.org * The license below extends only to copyright in the software and shall 67087Snate@binkert.org * not be construed as granting a license to any other intellectual 77087Snate@binkert.org * property including but not limited to intellectual property relating 87087Snate@binkert.org * to a hardware implementation of the functionality of the software 97087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 127087Snate@binkert.org * modified or unmodified, in source code or in binary form. 135647Sgblack@eecs.umich.edu * 147087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 157087Snate@binkert.org * modification, are permitted provided that the following conditions are 167087Snate@binkert.org * met: redistributions of source code must retain the above copyright 177087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 187087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 197087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 207087Snate@binkert.org * documentation and/or other materials provided with the distribution; 217087Snate@binkert.org * neither the name of the copyright holders nor the names of its 225647Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 237087Snate@binkert.org * this software without specific prior written permission. 245647Sgblack@eecs.umich.edu * 255647Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 265647Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 275647Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 285647Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 295647Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 305647Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 315647Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 325647Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 335647Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 345647Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 355647Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 365647Sgblack@eecs.umich.edu * 375647Sgblack@eecs.umich.edu * Authors: Gabe Black 385647Sgblack@eecs.umich.edu */ 395647Sgblack@eecs.umich.edu 408229Snate@binkert.org#include "arch/x86/regs/apic.hh" 415647Sgblack@eecs.umich.edu#include "arch/x86/interrupts.hh" 425654Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 435647Sgblack@eecs.umich.edu#include "cpu/base.hh" 448232Snate@binkert.org#include "debug/LocalApic.hh" 456137Sgblack@eecs.umich.edu#include "dev/x86/i82094aa.hh" 466137Sgblack@eecs.umich.edu#include "dev/x86/pc.hh" 476137Sgblack@eecs.umich.edu#include "dev/x86/south_bridge.hh" 485654Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 496046Sgblack@eecs.umich.edu#include "sim/system.hh" 508781Sgblack@eecs.umich.edu#include "sim/full_system.hh" 515647Sgblack@eecs.umich.edu 525648Sgblack@eecs.umich.eduint 535648Sgblack@eecs.umich.edudivideFromConf(uint32_t conf) 545647Sgblack@eecs.umich.edu{ 555647Sgblack@eecs.umich.edu // This figures out what division we want from the division configuration 565647Sgblack@eecs.umich.edu // register in the local APIC. The encoding is a little odd but it can 575647Sgblack@eecs.umich.edu // be deciphered fairly easily. 585647Sgblack@eecs.umich.edu int shift = ((conf & 0x8) >> 1) | (conf & 0x3); 595647Sgblack@eecs.umich.edu shift = (shift + 1) % 8; 605647Sgblack@eecs.umich.edu return 1 << shift; 615647Sgblack@eecs.umich.edu} 625647Sgblack@eecs.umich.edu 635648Sgblack@eecs.umich.edunamespace X86ISA 645647Sgblack@eecs.umich.edu{ 655648Sgblack@eecs.umich.edu 665648Sgblack@eecs.umich.eduApicRegIndex 675648Sgblack@eecs.umich.edudecodeAddr(Addr paddr) 685648Sgblack@eecs.umich.edu{ 695648Sgblack@eecs.umich.edu ApicRegIndex regNum; 705648Sgblack@eecs.umich.edu paddr &= ~mask(3); 715648Sgblack@eecs.umich.edu switch (paddr) 725648Sgblack@eecs.umich.edu { 735648Sgblack@eecs.umich.edu case 0x20: 745648Sgblack@eecs.umich.edu regNum = APIC_ID; 755648Sgblack@eecs.umich.edu break; 765648Sgblack@eecs.umich.edu case 0x30: 775648Sgblack@eecs.umich.edu regNum = APIC_VERSION; 785648Sgblack@eecs.umich.edu break; 795648Sgblack@eecs.umich.edu case 0x80: 805648Sgblack@eecs.umich.edu regNum = APIC_TASK_PRIORITY; 815648Sgblack@eecs.umich.edu break; 825648Sgblack@eecs.umich.edu case 0x90: 835648Sgblack@eecs.umich.edu regNum = APIC_ARBITRATION_PRIORITY; 845648Sgblack@eecs.umich.edu break; 855648Sgblack@eecs.umich.edu case 0xA0: 865648Sgblack@eecs.umich.edu regNum = APIC_PROCESSOR_PRIORITY; 875648Sgblack@eecs.umich.edu break; 885648Sgblack@eecs.umich.edu case 0xB0: 895648Sgblack@eecs.umich.edu regNum = APIC_EOI; 905648Sgblack@eecs.umich.edu break; 915648Sgblack@eecs.umich.edu case 0xD0: 925648Sgblack@eecs.umich.edu regNum = APIC_LOGICAL_DESTINATION; 935648Sgblack@eecs.umich.edu break; 945648Sgblack@eecs.umich.edu case 0xE0: 955648Sgblack@eecs.umich.edu regNum = APIC_DESTINATION_FORMAT; 965648Sgblack@eecs.umich.edu break; 975648Sgblack@eecs.umich.edu case 0xF0: 985648Sgblack@eecs.umich.edu regNum = APIC_SPURIOUS_INTERRUPT_VECTOR; 995648Sgblack@eecs.umich.edu break; 1005648Sgblack@eecs.umich.edu case 0x100: 1015648Sgblack@eecs.umich.edu case 0x108: 1025648Sgblack@eecs.umich.edu case 0x110: 1035648Sgblack@eecs.umich.edu case 0x118: 1045648Sgblack@eecs.umich.edu case 0x120: 1055648Sgblack@eecs.umich.edu case 0x128: 1065648Sgblack@eecs.umich.edu case 0x130: 1075648Sgblack@eecs.umich.edu case 0x138: 1085648Sgblack@eecs.umich.edu case 0x140: 1095648Sgblack@eecs.umich.edu case 0x148: 1105648Sgblack@eecs.umich.edu case 0x150: 1115648Sgblack@eecs.umich.edu case 0x158: 1125648Sgblack@eecs.umich.edu case 0x160: 1135648Sgblack@eecs.umich.edu case 0x168: 1145648Sgblack@eecs.umich.edu case 0x170: 1155648Sgblack@eecs.umich.edu case 0x178: 1165648Sgblack@eecs.umich.edu regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8); 1175648Sgblack@eecs.umich.edu break; 1185648Sgblack@eecs.umich.edu case 0x180: 1195648Sgblack@eecs.umich.edu case 0x188: 1205648Sgblack@eecs.umich.edu case 0x190: 1215648Sgblack@eecs.umich.edu case 0x198: 1225648Sgblack@eecs.umich.edu case 0x1A0: 1235648Sgblack@eecs.umich.edu case 0x1A8: 1245648Sgblack@eecs.umich.edu case 0x1B0: 1255648Sgblack@eecs.umich.edu case 0x1B8: 1265648Sgblack@eecs.umich.edu case 0x1C0: 1275648Sgblack@eecs.umich.edu case 0x1C8: 1285648Sgblack@eecs.umich.edu case 0x1D0: 1295648Sgblack@eecs.umich.edu case 0x1D8: 1305648Sgblack@eecs.umich.edu case 0x1E0: 1315648Sgblack@eecs.umich.edu case 0x1E8: 1325648Sgblack@eecs.umich.edu case 0x1F0: 1335648Sgblack@eecs.umich.edu case 0x1F8: 1345648Sgblack@eecs.umich.edu regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8); 1355648Sgblack@eecs.umich.edu break; 1365648Sgblack@eecs.umich.edu case 0x200: 1375648Sgblack@eecs.umich.edu case 0x208: 1385648Sgblack@eecs.umich.edu case 0x210: 1395648Sgblack@eecs.umich.edu case 0x218: 1405648Sgblack@eecs.umich.edu case 0x220: 1415648Sgblack@eecs.umich.edu case 0x228: 1425648Sgblack@eecs.umich.edu case 0x230: 1435648Sgblack@eecs.umich.edu case 0x238: 1445648Sgblack@eecs.umich.edu case 0x240: 1455648Sgblack@eecs.umich.edu case 0x248: 1465648Sgblack@eecs.umich.edu case 0x250: 1475648Sgblack@eecs.umich.edu case 0x258: 1485648Sgblack@eecs.umich.edu case 0x260: 1495648Sgblack@eecs.umich.edu case 0x268: 1505648Sgblack@eecs.umich.edu case 0x270: 1515648Sgblack@eecs.umich.edu case 0x278: 1525648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8); 1535648Sgblack@eecs.umich.edu break; 1545648Sgblack@eecs.umich.edu case 0x280: 1555648Sgblack@eecs.umich.edu regNum = APIC_ERROR_STATUS; 1565648Sgblack@eecs.umich.edu break; 1575648Sgblack@eecs.umich.edu case 0x300: 1585648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_LOW; 1595648Sgblack@eecs.umich.edu break; 1605648Sgblack@eecs.umich.edu case 0x310: 1615648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_HIGH; 1625648Sgblack@eecs.umich.edu break; 1635648Sgblack@eecs.umich.edu case 0x320: 1645648Sgblack@eecs.umich.edu regNum = APIC_LVT_TIMER; 1655648Sgblack@eecs.umich.edu break; 1665648Sgblack@eecs.umich.edu case 0x330: 1675648Sgblack@eecs.umich.edu regNum = APIC_LVT_THERMAL_SENSOR; 1685648Sgblack@eecs.umich.edu break; 1695648Sgblack@eecs.umich.edu case 0x340: 1705648Sgblack@eecs.umich.edu regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS; 1715648Sgblack@eecs.umich.edu break; 1725648Sgblack@eecs.umich.edu case 0x350: 1735648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT0; 1745648Sgblack@eecs.umich.edu break; 1755648Sgblack@eecs.umich.edu case 0x360: 1765648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT1; 1775648Sgblack@eecs.umich.edu break; 1785648Sgblack@eecs.umich.edu case 0x370: 1795648Sgblack@eecs.umich.edu regNum = APIC_LVT_ERROR; 1805648Sgblack@eecs.umich.edu break; 1815648Sgblack@eecs.umich.edu case 0x380: 1825648Sgblack@eecs.umich.edu regNum = APIC_INITIAL_COUNT; 1835648Sgblack@eecs.umich.edu break; 1845648Sgblack@eecs.umich.edu case 0x390: 1855648Sgblack@eecs.umich.edu regNum = APIC_CURRENT_COUNT; 1865648Sgblack@eecs.umich.edu break; 1875648Sgblack@eecs.umich.edu case 0x3E0: 1885648Sgblack@eecs.umich.edu regNum = APIC_DIVIDE_CONFIGURATION; 1895648Sgblack@eecs.umich.edu break; 1905648Sgblack@eecs.umich.edu default: 1915648Sgblack@eecs.umich.edu // A reserved register field. 1925648Sgblack@eecs.umich.edu panic("Accessed reserved register field %#x.\n", paddr); 1935648Sgblack@eecs.umich.edu break; 1945648Sgblack@eecs.umich.edu } 1955648Sgblack@eecs.umich.edu return regNum; 1965648Sgblack@eecs.umich.edu} 1975648Sgblack@eecs.umich.edu} 1985648Sgblack@eecs.umich.edu 1995648Sgblack@eecs.umich.eduTick 2005648Sgblack@eecs.umich.eduX86ISA::Interrupts::read(PacketPtr pkt) 2015648Sgblack@eecs.umich.edu{ 2025648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 2035648Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 2045648Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2055648Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 2065648Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 2075648Sgblack@eecs.umich.edu uint32_t val = htog(readReg(reg)); 2085649Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2095649Sgblack@eecs.umich.edu "Reading Local APIC register %d at offset %#x as %#x.\n", 2105649Sgblack@eecs.umich.edu reg, offset, val); 2115648Sgblack@eecs.umich.edu pkt->setData(((uint8_t *)&val) + (offset & mask(3))); 2125898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2135648Sgblack@eecs.umich.edu return latency; 2145648Sgblack@eecs.umich.edu} 2155648Sgblack@eecs.umich.edu 2165648Sgblack@eecs.umich.eduTick 2175648Sgblack@eecs.umich.eduX86ISA::Interrupts::write(PacketPtr pkt) 2185648Sgblack@eecs.umich.edu{ 2195648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 2205648Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 2215648Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2225648Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 2235648Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 2245648Sgblack@eecs.umich.edu uint32_t val = regs[reg]; 2255648Sgblack@eecs.umich.edu pkt->writeData(((uint8_t *)&val) + (offset & mask(3))); 2265649Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2275649Sgblack@eecs.umich.edu "Writing Local APIC register %d at offset %#x as %#x.\n", 2285649Sgblack@eecs.umich.edu reg, offset, gtoh(val)); 2295648Sgblack@eecs.umich.edu setReg(reg, gtoh(val)); 2305898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2315648Sgblack@eecs.umich.edu return latency; 2325647Sgblack@eecs.umich.edu} 2335691Sgblack@eecs.umich.eduvoid 2345691Sgblack@eecs.umich.eduX86ISA::Interrupts::requestInterrupt(uint8_t vector, 2355691Sgblack@eecs.umich.edu uint8_t deliveryMode, bool level) 2365691Sgblack@eecs.umich.edu{ 2375691Sgblack@eecs.umich.edu /* 2385691Sgblack@eecs.umich.edu * Fixed and lowest-priority delivery mode interrupts are handled 2395691Sgblack@eecs.umich.edu * using the IRR/ISR registers, checking against the TPR, etc. 2405691Sgblack@eecs.umich.edu * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through. 2415691Sgblack@eecs.umich.edu */ 2425691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::Fixed || 2435691Sgblack@eecs.umich.edu deliveryMode == DeliveryMode::LowestPriority) { 2445691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2455691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2465691Sgblack@eecs.umich.edu // Queue up the interrupt in the IRR. 2475691Sgblack@eecs.umich.edu if (vector > IRRV) 2485691Sgblack@eecs.umich.edu IRRV = vector; 2495691Sgblack@eecs.umich.edu if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) { 2505691Sgblack@eecs.umich.edu setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector); 2515691Sgblack@eecs.umich.edu if (level) { 2525691Sgblack@eecs.umich.edu setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2535691Sgblack@eecs.umich.edu } else { 2545691Sgblack@eecs.umich.edu clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2555691Sgblack@eecs.umich.edu } 2565691Sgblack@eecs.umich.edu } 2575691Sgblack@eecs.umich.edu } else if (!DeliveryMode::isReserved(deliveryMode)) { 2585691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2595691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2605691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::SMI && !pendingSmi) { 2615691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingSmi = true; 2625691Sgblack@eecs.umich.edu smiVector = vector; 2635691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) { 2645691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingNmi = true; 2655691Sgblack@eecs.umich.edu nmiVector = vector; 2665691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) { 2675691Sgblack@eecs.umich.edu pendingExtInt = true; 2685691Sgblack@eecs.umich.edu extIntVector = vector; 2695691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) { 2705691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingInit = true; 2715691Sgblack@eecs.umich.edu initVector = vector; 2726066Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::SIPI && 2736066Sgblack@eecs.umich.edu !pendingStartup && !startedUp) { 2746050Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingStartup = true; 2756050Sgblack@eecs.umich.edu startupVector = vector; 2765691Sgblack@eecs.umich.edu } 2778745Sgblack@eecs.umich.edu } 2788781Sgblack@eecs.umich.edu if (FullSystem) 2798781Sgblack@eecs.umich.edu cpu->wakeup(); 2805691Sgblack@eecs.umich.edu} 2815647Sgblack@eecs.umich.edu 2826041Sgblack@eecs.umich.edu 2836041Sgblack@eecs.umich.eduvoid 2846041Sgblack@eecs.umich.eduX86ISA::Interrupts::setCPU(BaseCPU * newCPU) 2856041Sgblack@eecs.umich.edu{ 2866136Sgblack@eecs.umich.edu assert(newCPU); 2876136Sgblack@eecs.umich.edu if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) { 2886136Sgblack@eecs.umich.edu panic("Local APICs can't be moved between CPUs" 2896136Sgblack@eecs.umich.edu " with different IDs.\n"); 2906136Sgblack@eecs.umich.edu } 2916041Sgblack@eecs.umich.edu cpu = newCPU; 2926136Sgblack@eecs.umich.edu initialApicId = cpu->cpuId(); 2936136Sgblack@eecs.umich.edu regs[APIC_ID] = (initialApicId << 24); 2946041Sgblack@eecs.umich.edu} 2956041Sgblack@eecs.umich.edu 2966041Sgblack@eecs.umich.edu 2976137Sgblack@eecs.umich.eduvoid 2986137Sgblack@eecs.umich.eduX86ISA::Interrupts::init() 2996137Sgblack@eecs.umich.edu{ 3007913SBrad.Beckmann@amd.com // 3017913SBrad.Beckmann@amd.com // The local apic must register its address ranges on both its pio port 3027913SBrad.Beckmann@amd.com // via the basicpiodevice(piodevice) init() function and its int port 3037913SBrad.Beckmann@amd.com // that it inherited from IntDev. Note IntDev is not a SimObject itself. 3047913SBrad.Beckmann@amd.com // 3056137Sgblack@eecs.umich.edu BasicPioDevice::init(); 3067913SBrad.Beckmann@amd.com IntDev::init(); 3076137Sgblack@eecs.umich.edu} 3086137Sgblack@eecs.umich.edu 3096137Sgblack@eecs.umich.edu 3105651Sgblack@eecs.umich.eduTick 3115651Sgblack@eecs.umich.eduX86ISA::Interrupts::recvMessage(PacketPtr pkt) 3125651Sgblack@eecs.umich.edu{ 3136136Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0); 3145651Sgblack@eecs.umich.edu assert(pkt->cmd == MemCmd::MessageReq); 3155651Sgblack@eecs.umich.edu switch(offset) 3165651Sgblack@eecs.umich.edu { 3175651Sgblack@eecs.umich.edu case 0: 3185654Sgblack@eecs.umich.edu { 3195654Sgblack@eecs.umich.edu TriggerIntMessage message = pkt->get<TriggerIntMessage>(); 3205654Sgblack@eecs.umich.edu DPRINTF(LocalApic, 3215654Sgblack@eecs.umich.edu "Got Trigger Interrupt message with vector %#x.\n", 3225697Snate@binkert.org message.vector); 3235655Sgblack@eecs.umich.edu 3245691Sgblack@eecs.umich.edu requestInterrupt(message.vector, 3255691Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 3265654Sgblack@eecs.umich.edu } 3275651Sgblack@eecs.umich.edu break; 3285651Sgblack@eecs.umich.edu default: 3295651Sgblack@eecs.umich.edu panic("Local apic got unknown interrupt message at offset %#x.\n", 3305651Sgblack@eecs.umich.edu offset); 3315651Sgblack@eecs.umich.edu break; 3325651Sgblack@eecs.umich.edu } 3336064Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 3345651Sgblack@eecs.umich.edu return latency; 3355651Sgblack@eecs.umich.edu} 3365651Sgblack@eecs.umich.edu 3375651Sgblack@eecs.umich.edu 3386065Sgblack@eecs.umich.eduTick 3396065Sgblack@eecs.umich.eduX86ISA::Interrupts::recvResponse(PacketPtr pkt) 3406065Sgblack@eecs.umich.edu{ 3416065Sgblack@eecs.umich.edu assert(!pkt->isError()); 3426065Sgblack@eecs.umich.edu assert(pkt->cmd == MemCmd::MessageResp); 3436069Sgblack@eecs.umich.edu if (--pendingIPIs == 0) { 3446069Sgblack@eecs.umich.edu InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 3456069Sgblack@eecs.umich.edu // Record that the ICR is now idle. 3466069Sgblack@eecs.umich.edu low.deliveryStatus = 0; 3476069Sgblack@eecs.umich.edu regs[APIC_INTERRUPT_COMMAND_LOW] = low; 3486069Sgblack@eecs.umich.edu } 3496065Sgblack@eecs.umich.edu DPRINTF(LocalApic, "ICR is now idle.\n"); 3506065Sgblack@eecs.umich.edu return 0; 3516065Sgblack@eecs.umich.edu} 3526065Sgblack@eecs.umich.edu 3536065Sgblack@eecs.umich.edu 3546041Sgblack@eecs.umich.eduvoid 3556041Sgblack@eecs.umich.eduX86ISA::Interrupts::addressRanges(AddrRangeList &range_list) 3566041Sgblack@eecs.umich.edu{ 3576041Sgblack@eecs.umich.edu range_list.clear(); 3586136Sgblack@eecs.umich.edu Range<Addr> range = RangeEx(x86LocalAPICAddress(initialApicId, 0), 3596136Sgblack@eecs.umich.edu x86LocalAPICAddress(initialApicId, 0) + 3606136Sgblack@eecs.umich.edu PageBytes); 3616061Sgblack@eecs.umich.edu range_list.push_back(range); 3626061Sgblack@eecs.umich.edu pioAddr = range.start; 3636041Sgblack@eecs.umich.edu} 3646041Sgblack@eecs.umich.edu 3656041Sgblack@eecs.umich.edu 3666041Sgblack@eecs.umich.eduvoid 3676041Sgblack@eecs.umich.eduX86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list) 3686041Sgblack@eecs.umich.edu{ 3696041Sgblack@eecs.umich.edu range_list.clear(); 3706136Sgblack@eecs.umich.edu range_list.push_back(RangeEx(x86InterruptAddress(initialApicId, 0), 3716136Sgblack@eecs.umich.edu x86InterruptAddress(initialApicId, 0) + 3726136Sgblack@eecs.umich.edu PhysAddrAPICRangeSize)); 3736041Sgblack@eecs.umich.edu} 3746041Sgblack@eecs.umich.edu 3756041Sgblack@eecs.umich.edu 3765647Sgblack@eecs.umich.eduuint32_t 3775648Sgblack@eecs.umich.eduX86ISA::Interrupts::readReg(ApicRegIndex reg) 3785647Sgblack@eecs.umich.edu{ 3795647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 3805647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 3815647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 3825647Sgblack@eecs.umich.edu } 3835647Sgblack@eecs.umich.edu switch (reg) { 3845647Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 3855647Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 3865647Sgblack@eecs.umich.edu break; 3875647Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 3885647Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 3895647Sgblack@eecs.umich.edu break; 3905647Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 3915647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 3925647Sgblack@eecs.umich.edu break; 3935647Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 3945647Sgblack@eecs.umich.edu { 3955848Sgblack@eecs.umich.edu if (apicTimerEvent.scheduled()) { 3965848Sgblack@eecs.umich.edu assert(clock); 3975848Sgblack@eecs.umich.edu // Compute how many m5 ticks happen per count. 3985848Sgblack@eecs.umich.edu uint64_t ticksPerCount = clock * 3995848Sgblack@eecs.umich.edu divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]); 4005848Sgblack@eecs.umich.edu // Compute how many m5 ticks are left. 4017823Ssteve.reinhardt@amd.com uint64_t val = apicTimerEvent.when() - curTick(); 4025848Sgblack@eecs.umich.edu // Turn that into a count. 4035848Sgblack@eecs.umich.edu val = (val + ticksPerCount - 1) / ticksPerCount; 4045848Sgblack@eecs.umich.edu return val; 4055848Sgblack@eecs.umich.edu } else { 4065848Sgblack@eecs.umich.edu return 0; 4075848Sgblack@eecs.umich.edu } 4085647Sgblack@eecs.umich.edu } 4095647Sgblack@eecs.umich.edu default: 4105647Sgblack@eecs.umich.edu break; 4115647Sgblack@eecs.umich.edu } 4125648Sgblack@eecs.umich.edu return regs[reg]; 4135647Sgblack@eecs.umich.edu} 4145647Sgblack@eecs.umich.edu 4155647Sgblack@eecs.umich.eduvoid 4165648Sgblack@eecs.umich.eduX86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) 4175647Sgblack@eecs.umich.edu{ 4185647Sgblack@eecs.umich.edu uint32_t newVal = val; 4195647Sgblack@eecs.umich.edu if (reg >= APIC_IN_SERVICE(0) && 4205647Sgblack@eecs.umich.edu reg <= APIC_IN_SERVICE(15)) { 4215647Sgblack@eecs.umich.edu panic("Local APIC In-Service registers are unimplemented.\n"); 4225647Sgblack@eecs.umich.edu } 4235647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 4245647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 4255647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 4265647Sgblack@eecs.umich.edu } 4275647Sgblack@eecs.umich.edu if (reg >= APIC_INTERRUPT_REQUEST(0) && 4285647Sgblack@eecs.umich.edu reg <= APIC_INTERRUPT_REQUEST(15)) { 4295647Sgblack@eecs.umich.edu panic("Local APIC Interrupt Request registers " 4305647Sgblack@eecs.umich.edu "are unimplemented.\n"); 4315647Sgblack@eecs.umich.edu } 4325647Sgblack@eecs.umich.edu switch (reg) { 4335647Sgblack@eecs.umich.edu case APIC_ID: 4345647Sgblack@eecs.umich.edu newVal = val & 0xFF; 4355647Sgblack@eecs.umich.edu break; 4365647Sgblack@eecs.umich.edu case APIC_VERSION: 4375647Sgblack@eecs.umich.edu // The Local APIC Version register is read only. 4385647Sgblack@eecs.umich.edu return; 4395647Sgblack@eecs.umich.edu case APIC_TASK_PRIORITY: 4405647Sgblack@eecs.umich.edu newVal = val & 0xFF; 4415647Sgblack@eecs.umich.edu break; 4425647Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 4435647Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 4445647Sgblack@eecs.umich.edu break; 4455647Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 4465647Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 4475647Sgblack@eecs.umich.edu break; 4485647Sgblack@eecs.umich.edu case APIC_EOI: 4495690Sgblack@eecs.umich.edu // Remove the interrupt that just completed from the local apic state. 4505690Sgblack@eecs.umich.edu clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 4515690Sgblack@eecs.umich.edu updateISRV(); 4525690Sgblack@eecs.umich.edu return; 4535647Sgblack@eecs.umich.edu case APIC_LOGICAL_DESTINATION: 4545647Sgblack@eecs.umich.edu newVal = val & 0xFF000000; 4555647Sgblack@eecs.umich.edu break; 4565647Sgblack@eecs.umich.edu case APIC_DESTINATION_FORMAT: 4575647Sgblack@eecs.umich.edu newVal = val | 0x0FFFFFFF; 4585647Sgblack@eecs.umich.edu break; 4595647Sgblack@eecs.umich.edu case APIC_SPURIOUS_INTERRUPT_VECTOR: 4605647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1); 4615647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= val & (1 << 8); 4625647Sgblack@eecs.umich.edu if (val & (1 << 9)) 4635647Sgblack@eecs.umich.edu warn("Focus processor checking not implemented.\n"); 4645647Sgblack@eecs.umich.edu break; 4655647Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 4665647Sgblack@eecs.umich.edu { 4675647Sgblack@eecs.umich.edu if (regs[APIC_INTERNAL_STATE] & 0x1) { 4685647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 4695647Sgblack@eecs.umich.edu newVal = 0; 4705647Sgblack@eecs.umich.edu } else { 4715647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= ULL(0x1); 4725647Sgblack@eecs.umich.edu return; 4735647Sgblack@eecs.umich.edu } 4745647Sgblack@eecs.umich.edu 4755647Sgblack@eecs.umich.edu } 4765647Sgblack@eecs.umich.edu break; 4775647Sgblack@eecs.umich.edu case APIC_INTERRUPT_COMMAND_LOW: 4786046Sgblack@eecs.umich.edu { 4796046Sgblack@eecs.umich.edu InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 4806046Sgblack@eecs.umich.edu // Check if we're already sending an IPI. 4816046Sgblack@eecs.umich.edu if (low.deliveryStatus) { 4826046Sgblack@eecs.umich.edu newVal = low; 4836046Sgblack@eecs.umich.edu break; 4846046Sgblack@eecs.umich.edu } 4856046Sgblack@eecs.umich.edu low = val; 4866046Sgblack@eecs.umich.edu InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH]; 4876046Sgblack@eecs.umich.edu // Record that an IPI is being sent. 4886046Sgblack@eecs.umich.edu low.deliveryStatus = 1; 4896712Snate@binkert.org TriggerIntMessage message = 0; 4906046Sgblack@eecs.umich.edu message.destination = high.destination; 4916046Sgblack@eecs.umich.edu message.vector = low.vector; 4926046Sgblack@eecs.umich.edu message.deliveryMode = low.deliveryMode; 4936046Sgblack@eecs.umich.edu message.destMode = low.destMode; 4946046Sgblack@eecs.umich.edu message.level = low.level; 4956046Sgblack@eecs.umich.edu message.trigger = low.trigger; 4966046Sgblack@eecs.umich.edu bool timing = sys->getMemoryMode() == Enums::timing; 4976065Sgblack@eecs.umich.edu // Be careful no updates of the delivery status bit get lost. 4986065Sgblack@eecs.umich.edu regs[APIC_INTERRUPT_COMMAND_LOW] = low; 4996138Sgblack@eecs.umich.edu ApicList apics; 5006138Sgblack@eecs.umich.edu int numContexts = sys->numContexts(); 5016046Sgblack@eecs.umich.edu switch (low.destShorthand) { 5026046Sgblack@eecs.umich.edu case 0: 5036138Sgblack@eecs.umich.edu if (message.deliveryMode == DeliveryMode::LowestPriority) { 5046138Sgblack@eecs.umich.edu panic("Lowest priority delivery mode " 5056138Sgblack@eecs.umich.edu "IPIs aren't implemented.\n"); 5066138Sgblack@eecs.umich.edu } 5076138Sgblack@eecs.umich.edu if (message.destMode == 1) { 5086138Sgblack@eecs.umich.edu int dest = message.destination; 5096138Sgblack@eecs.umich.edu hack_once("Assuming logical destinations are 1 << id.\n"); 5106138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 5116138Sgblack@eecs.umich.edu if (dest & 0x1) 5126138Sgblack@eecs.umich.edu apics.push_back(i); 5136138Sgblack@eecs.umich.edu dest = dest >> 1; 5146138Sgblack@eecs.umich.edu } 5156138Sgblack@eecs.umich.edu } else { 5166138Sgblack@eecs.umich.edu if (message.destination == 0xFF) { 5176138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 5186138Sgblack@eecs.umich.edu if (i == initialApicId) { 5196138Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5206138Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5216138Sgblack@eecs.umich.edu } else { 5226138Sgblack@eecs.umich.edu apics.push_back(i); 5236138Sgblack@eecs.umich.edu } 5246138Sgblack@eecs.umich.edu } 5256138Sgblack@eecs.umich.edu } else { 5266138Sgblack@eecs.umich.edu if (message.destination == initialApicId) { 5276138Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5286138Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5296138Sgblack@eecs.umich.edu } else { 5306138Sgblack@eecs.umich.edu apics.push_back(message.destination); 5316138Sgblack@eecs.umich.edu } 5326138Sgblack@eecs.umich.edu } 5336138Sgblack@eecs.umich.edu } 5346046Sgblack@eecs.umich.edu break; 5356046Sgblack@eecs.umich.edu case 1: 5366069Sgblack@eecs.umich.edu newVal = val; 5376069Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5386069Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5396046Sgblack@eecs.umich.edu break; 5406046Sgblack@eecs.umich.edu case 2: 5416069Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5426069Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5436069Sgblack@eecs.umich.edu // Fall through 5446046Sgblack@eecs.umich.edu case 3: 5456069Sgblack@eecs.umich.edu { 5466069Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 5476138Sgblack@eecs.umich.edu if (i != initialApicId) { 5486138Sgblack@eecs.umich.edu apics.push_back(i); 5496069Sgblack@eecs.umich.edu } 5506069Sgblack@eecs.umich.edu } 5516069Sgblack@eecs.umich.edu } 5526046Sgblack@eecs.umich.edu break; 5536046Sgblack@eecs.umich.edu } 5546138Sgblack@eecs.umich.edu pendingIPIs += apics.size(); 5556138Sgblack@eecs.umich.edu intPort->sendMessage(apics, message, timing); 5566138Sgblack@eecs.umich.edu newVal = regs[APIC_INTERRUPT_COMMAND_LOW]; 5576046Sgblack@eecs.umich.edu } 5585647Sgblack@eecs.umich.edu break; 5595647Sgblack@eecs.umich.edu case APIC_LVT_TIMER: 5605647Sgblack@eecs.umich.edu case APIC_LVT_THERMAL_SENSOR: 5615647Sgblack@eecs.umich.edu case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS: 5625647Sgblack@eecs.umich.edu case APIC_LVT_LINT0: 5635647Sgblack@eecs.umich.edu case APIC_LVT_LINT1: 5645647Sgblack@eecs.umich.edu case APIC_LVT_ERROR: 5655647Sgblack@eecs.umich.edu { 5665647Sgblack@eecs.umich.edu uint64_t readOnlyMask = (1 << 12) | (1 << 14); 5675647Sgblack@eecs.umich.edu newVal = (val & ~readOnlyMask) | 5685647Sgblack@eecs.umich.edu (regs[reg] & readOnlyMask); 5695647Sgblack@eecs.umich.edu } 5705647Sgblack@eecs.umich.edu break; 5715647Sgblack@eecs.umich.edu case APIC_INITIAL_COUNT: 5725648Sgblack@eecs.umich.edu { 5735648Sgblack@eecs.umich.edu assert(clock); 5745648Sgblack@eecs.umich.edu newVal = bits(val, 31, 0); 5755848Sgblack@eecs.umich.edu // Compute how many timer ticks we're being programmed for. 5765848Sgblack@eecs.umich.edu uint64_t newCount = newVal * 5775848Sgblack@eecs.umich.edu (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION])); 5785648Sgblack@eecs.umich.edu // Schedule on the edge of the next tick plus the new count. 5797823Ssteve.reinhardt@amd.com Tick offset = curTick() % clock; 5805648Sgblack@eecs.umich.edu if (offset) { 5815648Sgblack@eecs.umich.edu reschedule(apicTimerEvent, 5827823Ssteve.reinhardt@amd.com curTick() + (newCount + 1) * clock - offset, true); 5835648Sgblack@eecs.umich.edu } else { 5845648Sgblack@eecs.umich.edu reschedule(apicTimerEvent, 5857823Ssteve.reinhardt@amd.com curTick() + newCount * clock, true); 5865648Sgblack@eecs.umich.edu } 5875648Sgblack@eecs.umich.edu } 5885647Sgblack@eecs.umich.edu break; 5895647Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 5905647Sgblack@eecs.umich.edu //Local APIC Current Count register is read only. 5915647Sgblack@eecs.umich.edu return; 5925647Sgblack@eecs.umich.edu case APIC_DIVIDE_CONFIGURATION: 5935647Sgblack@eecs.umich.edu newVal = val & 0xB; 5945647Sgblack@eecs.umich.edu break; 5955647Sgblack@eecs.umich.edu default: 5965647Sgblack@eecs.umich.edu break; 5975647Sgblack@eecs.umich.edu } 5985648Sgblack@eecs.umich.edu regs[reg] = newVal; 5995647Sgblack@eecs.umich.edu return; 6005647Sgblack@eecs.umich.edu} 6015647Sgblack@eecs.umich.edu 6026041Sgblack@eecs.umich.edu 6036041Sgblack@eecs.umich.eduX86ISA::Interrupts::Interrupts(Params * p) : 6047900Shestness@cs.utexas.edu BasicPioDevice(p), IntDev(this, p->int_latency), latency(p->pio_latency), 6057900Shestness@cs.utexas.edu clock(0), 6066041Sgblack@eecs.umich.edu apicTimerEvent(this), 6076041Sgblack@eecs.umich.edu pendingSmi(false), smiVector(0), 6086041Sgblack@eecs.umich.edu pendingNmi(false), nmiVector(0), 6096041Sgblack@eecs.umich.edu pendingExtInt(false), extIntVector(0), 6106041Sgblack@eecs.umich.edu pendingInit(false), initVector(0), 6116050Sgblack@eecs.umich.edu pendingStartup(false), startupVector(0), 6126069Sgblack@eecs.umich.edu startedUp(false), pendingUnmaskableInt(false), 6136136Sgblack@eecs.umich.edu pendingIPIs(0), cpu(NULL) 6146041Sgblack@eecs.umich.edu{ 6156041Sgblack@eecs.umich.edu pioSize = PageBytes; 6166041Sgblack@eecs.umich.edu memset(regs, 0, sizeof(regs)); 6176041Sgblack@eecs.umich.edu //Set the local apic DFR to the flat model. 6186041Sgblack@eecs.umich.edu regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1); 6196041Sgblack@eecs.umich.edu ISRV = 0; 6206041Sgblack@eecs.umich.edu IRRV = 0; 6216041Sgblack@eecs.umich.edu} 6226041Sgblack@eecs.umich.edu 6236041Sgblack@eecs.umich.edu 6245654Sgblack@eecs.umich.edubool 6255704Snate@binkert.orgX86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const 6265654Sgblack@eecs.umich.edu{ 6275654Sgblack@eecs.umich.edu RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS); 6285689Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6295689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n"); 6305654Sgblack@eecs.umich.edu return true; 6315689Sgblack@eecs.umich.edu } 6325655Sgblack@eecs.umich.edu if (rflags.intf) { 6335689Sgblack@eecs.umich.edu if (pendingExtInt) { 6345689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending external interrupt.\n"); 6355655Sgblack@eecs.umich.edu return true; 6365689Sgblack@eecs.umich.edu } 6375655Sgblack@eecs.umich.edu if (IRRV > ISRV && bits(IRRV, 7, 4) > 6385689Sgblack@eecs.umich.edu bits(regs[APIC_TASK_PRIORITY], 7, 4)) { 6395689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending regular interrupt.\n"); 6405655Sgblack@eecs.umich.edu return true; 6415689Sgblack@eecs.umich.edu } 6425654Sgblack@eecs.umich.edu } 6435654Sgblack@eecs.umich.edu return false; 6445654Sgblack@eecs.umich.edu} 6455654Sgblack@eecs.umich.edu 6465654Sgblack@eecs.umich.eduFault 6475704Snate@binkert.orgX86ISA::Interrupts::getInterrupt(ThreadContext *tc) 6485654Sgblack@eecs.umich.edu{ 6495704Snate@binkert.org assert(checkInterrupts(tc)); 6505655Sgblack@eecs.umich.edu // These are all probably fairly uncommon, so we'll make them easier to 6515655Sgblack@eecs.umich.edu // check for. 6525655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6535655Sgblack@eecs.umich.edu if (pendingSmi) { 6545689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated SMI fault object.\n"); 6555655Sgblack@eecs.umich.edu return new SystemManagementInterrupt(); 6565655Sgblack@eecs.umich.edu } else if (pendingNmi) { 6575689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated NMI fault object.\n"); 6585691Sgblack@eecs.umich.edu return new NonMaskableInterrupt(nmiVector); 6595655Sgblack@eecs.umich.edu } else if (pendingInit) { 6605689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated INIT fault object.\n"); 6615691Sgblack@eecs.umich.edu return new InitInterrupt(initVector); 6626050Sgblack@eecs.umich.edu } else if (pendingStartup) { 6636050Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generating SIPI fault object.\n"); 6646050Sgblack@eecs.umich.edu return new StartupInterrupt(startupVector); 6655655Sgblack@eecs.umich.edu } else { 6665655Sgblack@eecs.umich.edu panic("pendingUnmaskableInt set, but no unmaskable " 6675655Sgblack@eecs.umich.edu "ints were pending.\n"); 6685655Sgblack@eecs.umich.edu return NoFault; 6695655Sgblack@eecs.umich.edu } 6705655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 6715689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated external interrupt fault object.\n"); 6725691Sgblack@eecs.umich.edu return new ExternalInterrupt(extIntVector); 6735655Sgblack@eecs.umich.edu } else { 6745689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated regular interrupt fault object.\n"); 6755655Sgblack@eecs.umich.edu // The only thing left are fixed and lowest priority interrupts. 6765655Sgblack@eecs.umich.edu return new ExternalInterrupt(IRRV); 6775655Sgblack@eecs.umich.edu } 6785654Sgblack@eecs.umich.edu} 6795654Sgblack@eecs.umich.edu 6805654Sgblack@eecs.umich.eduvoid 6815704Snate@binkert.orgX86ISA::Interrupts::updateIntrInfo(ThreadContext *tc) 6825654Sgblack@eecs.umich.edu{ 6835704Snate@binkert.org assert(checkInterrupts(tc)); 6845655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6855655Sgblack@eecs.umich.edu if (pendingSmi) { 6865689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "SMI sent to core.\n"); 6875655Sgblack@eecs.umich.edu pendingSmi = false; 6885655Sgblack@eecs.umich.edu } else if (pendingNmi) { 6895689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "NMI sent to core.\n"); 6905655Sgblack@eecs.umich.edu pendingNmi = false; 6915655Sgblack@eecs.umich.edu } else if (pendingInit) { 6925689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Init sent to core.\n"); 6935655Sgblack@eecs.umich.edu pendingInit = false; 6946066Sgblack@eecs.umich.edu startedUp = false; 6956050Sgblack@eecs.umich.edu } else if (pendingStartup) { 6966050Sgblack@eecs.umich.edu DPRINTF(LocalApic, "SIPI sent to core.\n"); 6976050Sgblack@eecs.umich.edu pendingStartup = false; 6986066Sgblack@eecs.umich.edu startedUp = true; 6995655Sgblack@eecs.umich.edu } 7006050Sgblack@eecs.umich.edu if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup)) 7015655Sgblack@eecs.umich.edu pendingUnmaskableInt = false; 7025655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 7035655Sgblack@eecs.umich.edu pendingExtInt = false; 7045655Sgblack@eecs.umich.edu } else { 7055689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV); 7065655Sgblack@eecs.umich.edu // Mark the interrupt as "in service". 7075655Sgblack@eecs.umich.edu ISRV = IRRV; 7085655Sgblack@eecs.umich.edu setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 7095655Sgblack@eecs.umich.edu // Clear it out of the IRR. 7105655Sgblack@eecs.umich.edu clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV); 7115655Sgblack@eecs.umich.edu updateIRRV(); 7125655Sgblack@eecs.umich.edu } 7135654Sgblack@eecs.umich.edu} 7145654Sgblack@eecs.umich.edu 7157902Shestness@cs.utexas.eduvoid 7167902Shestness@cs.utexas.eduX86ISA::Interrupts::serialize(std::ostream &os) 7177902Shestness@cs.utexas.edu{ 7187902Shestness@cs.utexas.edu SERIALIZE_ARRAY(regs, NUM_APIC_REGS); 7197902Shestness@cs.utexas.edu SERIALIZE_SCALAR(clock); 7207902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingSmi); 7217902Shestness@cs.utexas.edu SERIALIZE_SCALAR(smiVector); 7227902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingNmi); 7237902Shestness@cs.utexas.edu SERIALIZE_SCALAR(nmiVector); 7247902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingExtInt); 7257902Shestness@cs.utexas.edu SERIALIZE_SCALAR(extIntVector); 7267902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingInit); 7277902Shestness@cs.utexas.edu SERIALIZE_SCALAR(initVector); 7287902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingStartup); 7297902Shestness@cs.utexas.edu SERIALIZE_SCALAR(startupVector); 7307902Shestness@cs.utexas.edu SERIALIZE_SCALAR(startedUp); 7317902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingUnmaskableInt); 7327902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingIPIs); 7337902Shestness@cs.utexas.edu SERIALIZE_SCALAR(IRRV); 7347902Shestness@cs.utexas.edu SERIALIZE_SCALAR(ISRV); 7357902Shestness@cs.utexas.edu bool apicTimerEventScheduled = apicTimerEvent.scheduled(); 7367902Shestness@cs.utexas.edu SERIALIZE_SCALAR(apicTimerEventScheduled); 7377902Shestness@cs.utexas.edu Tick apicTimerEventTick = apicTimerEvent.when(); 7387902Shestness@cs.utexas.edu SERIALIZE_SCALAR(apicTimerEventTick); 7397902Shestness@cs.utexas.edu} 7407902Shestness@cs.utexas.edu 7417902Shestness@cs.utexas.eduvoid 7427902Shestness@cs.utexas.eduX86ISA::Interrupts::unserialize(Checkpoint *cp, const std::string §ion) 7437902Shestness@cs.utexas.edu{ 7447902Shestness@cs.utexas.edu UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS); 7457902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(clock); 7467902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingSmi); 7477902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(smiVector); 7487902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingNmi); 7497902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(nmiVector); 7507902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingExtInt); 7517902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(extIntVector); 7527902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingInit); 7537902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(initVector); 7547902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingStartup); 7557902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(startupVector); 7567902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(startedUp); 7577902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingUnmaskableInt); 7587902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingIPIs); 7597902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(IRRV); 7607902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(ISRV); 7617902Shestness@cs.utexas.edu bool apicTimerEventScheduled; 7627902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(apicTimerEventScheduled); 7637902Shestness@cs.utexas.edu if (apicTimerEventScheduled) { 7647902Shestness@cs.utexas.edu Tick apicTimerEventTick; 7657902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(apicTimerEventTick); 7667902Shestness@cs.utexas.edu if (apicTimerEvent.scheduled()) { 7677902Shestness@cs.utexas.edu reschedule(apicTimerEvent, apicTimerEventTick, true); 7687902Shestness@cs.utexas.edu } else { 7697902Shestness@cs.utexas.edu schedule(apicTimerEvent, apicTimerEventTick); 7707902Shestness@cs.utexas.edu } 7717902Shestness@cs.utexas.edu } 7727902Shestness@cs.utexas.edu} 7737902Shestness@cs.utexas.edu 7745647Sgblack@eecs.umich.eduX86ISA::Interrupts * 7755647Sgblack@eecs.umich.eduX86LocalApicParams::create() 7765647Sgblack@eecs.umich.edu{ 7775647Sgblack@eecs.umich.edu return new X86ISA::Interrupts(this); 7785647Sgblack@eecs.umich.edu} 779