interrupts.cc revision 7900
15647Sgblack@eecs.umich.edu/* 25647Sgblack@eecs.umich.edu * Copyright (c) 2008 The Hewlett-Packard Development Company 35647Sgblack@eecs.umich.edu * All rights reserved. 45647Sgblack@eecs.umich.edu * 57087Snate@binkert.org * The license below extends only to copyright in the software and shall 67087Snate@binkert.org * not be construed as granting a license to any other intellectual 77087Snate@binkert.org * property including but not limited to intellectual property relating 87087Snate@binkert.org * to a hardware implementation of the functionality of the software 97087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 127087Snate@binkert.org * modified or unmodified, in source code or in binary form. 135647Sgblack@eecs.umich.edu * 147087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 157087Snate@binkert.org * modification, are permitted provided that the following conditions are 167087Snate@binkert.org * met: redistributions of source code must retain the above copyright 177087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 187087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 197087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 207087Snate@binkert.org * documentation and/or other materials provided with the distribution; 217087Snate@binkert.org * neither the name of the copyright holders nor the names of its 225647Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 237087Snate@binkert.org * this software without specific prior written permission. 245647Sgblack@eecs.umich.edu * 255647Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 265647Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 275647Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 285647Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 295647Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 305647Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 315647Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 325647Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 335647Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 345647Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 355647Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 365647Sgblack@eecs.umich.edu * 375647Sgblack@eecs.umich.edu * Authors: Gabe Black 385647Sgblack@eecs.umich.edu */ 395647Sgblack@eecs.umich.edu 405647Sgblack@eecs.umich.edu#include "arch/x86/interrupts.hh" 415654Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 427629Sgblack@eecs.umich.edu#include "arch/x86/regs/apic.hh" 435647Sgblack@eecs.umich.edu#include "cpu/base.hh" 446137Sgblack@eecs.umich.edu#include "dev/x86/i82094aa.hh" 456137Sgblack@eecs.umich.edu#include "dev/x86/pc.hh" 466137Sgblack@eecs.umich.edu#include "dev/x86/south_bridge.hh" 475654Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 486046Sgblack@eecs.umich.edu#include "sim/system.hh" 495647Sgblack@eecs.umich.edu 505648Sgblack@eecs.umich.eduint 515648Sgblack@eecs.umich.edudivideFromConf(uint32_t conf) 525647Sgblack@eecs.umich.edu{ 535647Sgblack@eecs.umich.edu // This figures out what division we want from the division configuration 545647Sgblack@eecs.umich.edu // register in the local APIC. The encoding is a little odd but it can 555647Sgblack@eecs.umich.edu // be deciphered fairly easily. 565647Sgblack@eecs.umich.edu int shift = ((conf & 0x8) >> 1) | (conf & 0x3); 575647Sgblack@eecs.umich.edu shift = (shift + 1) % 8; 585647Sgblack@eecs.umich.edu return 1 << shift; 595647Sgblack@eecs.umich.edu} 605647Sgblack@eecs.umich.edu 615648Sgblack@eecs.umich.edunamespace X86ISA 625647Sgblack@eecs.umich.edu{ 635648Sgblack@eecs.umich.edu 645648Sgblack@eecs.umich.eduApicRegIndex 655648Sgblack@eecs.umich.edudecodeAddr(Addr paddr) 665648Sgblack@eecs.umich.edu{ 675648Sgblack@eecs.umich.edu ApicRegIndex regNum; 685648Sgblack@eecs.umich.edu paddr &= ~mask(3); 695648Sgblack@eecs.umich.edu switch (paddr) 705648Sgblack@eecs.umich.edu { 715648Sgblack@eecs.umich.edu case 0x20: 725648Sgblack@eecs.umich.edu regNum = APIC_ID; 735648Sgblack@eecs.umich.edu break; 745648Sgblack@eecs.umich.edu case 0x30: 755648Sgblack@eecs.umich.edu regNum = APIC_VERSION; 765648Sgblack@eecs.umich.edu break; 775648Sgblack@eecs.umich.edu case 0x80: 785648Sgblack@eecs.umich.edu regNum = APIC_TASK_PRIORITY; 795648Sgblack@eecs.umich.edu break; 805648Sgblack@eecs.umich.edu case 0x90: 815648Sgblack@eecs.umich.edu regNum = APIC_ARBITRATION_PRIORITY; 825648Sgblack@eecs.umich.edu break; 835648Sgblack@eecs.umich.edu case 0xA0: 845648Sgblack@eecs.umich.edu regNum = APIC_PROCESSOR_PRIORITY; 855648Sgblack@eecs.umich.edu break; 865648Sgblack@eecs.umich.edu case 0xB0: 875648Sgblack@eecs.umich.edu regNum = APIC_EOI; 885648Sgblack@eecs.umich.edu break; 895648Sgblack@eecs.umich.edu case 0xD0: 905648Sgblack@eecs.umich.edu regNum = APIC_LOGICAL_DESTINATION; 915648Sgblack@eecs.umich.edu break; 925648Sgblack@eecs.umich.edu case 0xE0: 935648Sgblack@eecs.umich.edu regNum = APIC_DESTINATION_FORMAT; 945648Sgblack@eecs.umich.edu break; 955648Sgblack@eecs.umich.edu case 0xF0: 965648Sgblack@eecs.umich.edu regNum = APIC_SPURIOUS_INTERRUPT_VECTOR; 975648Sgblack@eecs.umich.edu break; 985648Sgblack@eecs.umich.edu case 0x100: 995648Sgblack@eecs.umich.edu case 0x108: 1005648Sgblack@eecs.umich.edu case 0x110: 1015648Sgblack@eecs.umich.edu case 0x118: 1025648Sgblack@eecs.umich.edu case 0x120: 1035648Sgblack@eecs.umich.edu case 0x128: 1045648Sgblack@eecs.umich.edu case 0x130: 1055648Sgblack@eecs.umich.edu case 0x138: 1065648Sgblack@eecs.umich.edu case 0x140: 1075648Sgblack@eecs.umich.edu case 0x148: 1085648Sgblack@eecs.umich.edu case 0x150: 1095648Sgblack@eecs.umich.edu case 0x158: 1105648Sgblack@eecs.umich.edu case 0x160: 1115648Sgblack@eecs.umich.edu case 0x168: 1125648Sgblack@eecs.umich.edu case 0x170: 1135648Sgblack@eecs.umich.edu case 0x178: 1145648Sgblack@eecs.umich.edu regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8); 1155648Sgblack@eecs.umich.edu break; 1165648Sgblack@eecs.umich.edu case 0x180: 1175648Sgblack@eecs.umich.edu case 0x188: 1185648Sgblack@eecs.umich.edu case 0x190: 1195648Sgblack@eecs.umich.edu case 0x198: 1205648Sgblack@eecs.umich.edu case 0x1A0: 1215648Sgblack@eecs.umich.edu case 0x1A8: 1225648Sgblack@eecs.umich.edu case 0x1B0: 1235648Sgblack@eecs.umich.edu case 0x1B8: 1245648Sgblack@eecs.umich.edu case 0x1C0: 1255648Sgblack@eecs.umich.edu case 0x1C8: 1265648Sgblack@eecs.umich.edu case 0x1D0: 1275648Sgblack@eecs.umich.edu case 0x1D8: 1285648Sgblack@eecs.umich.edu case 0x1E0: 1295648Sgblack@eecs.umich.edu case 0x1E8: 1305648Sgblack@eecs.umich.edu case 0x1F0: 1315648Sgblack@eecs.umich.edu case 0x1F8: 1325648Sgblack@eecs.umich.edu regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8); 1335648Sgblack@eecs.umich.edu break; 1345648Sgblack@eecs.umich.edu case 0x200: 1355648Sgblack@eecs.umich.edu case 0x208: 1365648Sgblack@eecs.umich.edu case 0x210: 1375648Sgblack@eecs.umich.edu case 0x218: 1385648Sgblack@eecs.umich.edu case 0x220: 1395648Sgblack@eecs.umich.edu case 0x228: 1405648Sgblack@eecs.umich.edu case 0x230: 1415648Sgblack@eecs.umich.edu case 0x238: 1425648Sgblack@eecs.umich.edu case 0x240: 1435648Sgblack@eecs.umich.edu case 0x248: 1445648Sgblack@eecs.umich.edu case 0x250: 1455648Sgblack@eecs.umich.edu case 0x258: 1465648Sgblack@eecs.umich.edu case 0x260: 1475648Sgblack@eecs.umich.edu case 0x268: 1485648Sgblack@eecs.umich.edu case 0x270: 1495648Sgblack@eecs.umich.edu case 0x278: 1505648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8); 1515648Sgblack@eecs.umich.edu break; 1525648Sgblack@eecs.umich.edu case 0x280: 1535648Sgblack@eecs.umich.edu regNum = APIC_ERROR_STATUS; 1545648Sgblack@eecs.umich.edu break; 1555648Sgblack@eecs.umich.edu case 0x300: 1565648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_LOW; 1575648Sgblack@eecs.umich.edu break; 1585648Sgblack@eecs.umich.edu case 0x310: 1595648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_HIGH; 1605648Sgblack@eecs.umich.edu break; 1615648Sgblack@eecs.umich.edu case 0x320: 1625648Sgblack@eecs.umich.edu regNum = APIC_LVT_TIMER; 1635648Sgblack@eecs.umich.edu break; 1645648Sgblack@eecs.umich.edu case 0x330: 1655648Sgblack@eecs.umich.edu regNum = APIC_LVT_THERMAL_SENSOR; 1665648Sgblack@eecs.umich.edu break; 1675648Sgblack@eecs.umich.edu case 0x340: 1685648Sgblack@eecs.umich.edu regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS; 1695648Sgblack@eecs.umich.edu break; 1705648Sgblack@eecs.umich.edu case 0x350: 1715648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT0; 1725648Sgblack@eecs.umich.edu break; 1735648Sgblack@eecs.umich.edu case 0x360: 1745648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT1; 1755648Sgblack@eecs.umich.edu break; 1765648Sgblack@eecs.umich.edu case 0x370: 1775648Sgblack@eecs.umich.edu regNum = APIC_LVT_ERROR; 1785648Sgblack@eecs.umich.edu break; 1795648Sgblack@eecs.umich.edu case 0x380: 1805648Sgblack@eecs.umich.edu regNum = APIC_INITIAL_COUNT; 1815648Sgblack@eecs.umich.edu break; 1825648Sgblack@eecs.umich.edu case 0x390: 1835648Sgblack@eecs.umich.edu regNum = APIC_CURRENT_COUNT; 1845648Sgblack@eecs.umich.edu break; 1855648Sgblack@eecs.umich.edu case 0x3E0: 1865648Sgblack@eecs.umich.edu regNum = APIC_DIVIDE_CONFIGURATION; 1875648Sgblack@eecs.umich.edu break; 1885648Sgblack@eecs.umich.edu default: 1895648Sgblack@eecs.umich.edu // A reserved register field. 1905648Sgblack@eecs.umich.edu panic("Accessed reserved register field %#x.\n", paddr); 1915648Sgblack@eecs.umich.edu break; 1925648Sgblack@eecs.umich.edu } 1935648Sgblack@eecs.umich.edu return regNum; 1945648Sgblack@eecs.umich.edu} 1955648Sgblack@eecs.umich.edu} 1965648Sgblack@eecs.umich.edu 1975648Sgblack@eecs.umich.eduTick 1985648Sgblack@eecs.umich.eduX86ISA::Interrupts::read(PacketPtr pkt) 1995648Sgblack@eecs.umich.edu{ 2005648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 2015648Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 2025648Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2035648Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 2045648Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 2055648Sgblack@eecs.umich.edu uint32_t val = htog(readReg(reg)); 2065649Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2075649Sgblack@eecs.umich.edu "Reading Local APIC register %d at offset %#x as %#x.\n", 2085649Sgblack@eecs.umich.edu reg, offset, val); 2095648Sgblack@eecs.umich.edu pkt->setData(((uint8_t *)&val) + (offset & mask(3))); 2105898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2115648Sgblack@eecs.umich.edu return latency; 2125648Sgblack@eecs.umich.edu} 2135648Sgblack@eecs.umich.edu 2145648Sgblack@eecs.umich.eduTick 2155648Sgblack@eecs.umich.eduX86ISA::Interrupts::write(PacketPtr pkt) 2165648Sgblack@eecs.umich.edu{ 2175648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 2185648Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 2195648Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2205648Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 2215648Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 2225648Sgblack@eecs.umich.edu uint32_t val = regs[reg]; 2235648Sgblack@eecs.umich.edu pkt->writeData(((uint8_t *)&val) + (offset & mask(3))); 2245649Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2255649Sgblack@eecs.umich.edu "Writing Local APIC register %d at offset %#x as %#x.\n", 2265649Sgblack@eecs.umich.edu reg, offset, gtoh(val)); 2275648Sgblack@eecs.umich.edu setReg(reg, gtoh(val)); 2285898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2295648Sgblack@eecs.umich.edu return latency; 2305647Sgblack@eecs.umich.edu} 2315691Sgblack@eecs.umich.eduvoid 2325691Sgblack@eecs.umich.eduX86ISA::Interrupts::requestInterrupt(uint8_t vector, 2335691Sgblack@eecs.umich.edu uint8_t deliveryMode, bool level) 2345691Sgblack@eecs.umich.edu{ 2355691Sgblack@eecs.umich.edu /* 2365691Sgblack@eecs.umich.edu * Fixed and lowest-priority delivery mode interrupts are handled 2375691Sgblack@eecs.umich.edu * using the IRR/ISR registers, checking against the TPR, etc. 2385691Sgblack@eecs.umich.edu * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through. 2395691Sgblack@eecs.umich.edu */ 2405691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::Fixed || 2415691Sgblack@eecs.umich.edu deliveryMode == DeliveryMode::LowestPriority) { 2425691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2435691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2445691Sgblack@eecs.umich.edu // Queue up the interrupt in the IRR. 2455691Sgblack@eecs.umich.edu if (vector > IRRV) 2465691Sgblack@eecs.umich.edu IRRV = vector; 2475691Sgblack@eecs.umich.edu if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) { 2485691Sgblack@eecs.umich.edu setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector); 2495691Sgblack@eecs.umich.edu if (level) { 2505691Sgblack@eecs.umich.edu setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2515691Sgblack@eecs.umich.edu } else { 2525691Sgblack@eecs.umich.edu clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2535691Sgblack@eecs.umich.edu } 2545691Sgblack@eecs.umich.edu } 2555691Sgblack@eecs.umich.edu } else if (!DeliveryMode::isReserved(deliveryMode)) { 2565691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2575691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2585691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::SMI && !pendingSmi) { 2595691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingSmi = true; 2605691Sgblack@eecs.umich.edu smiVector = vector; 2615691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) { 2625691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingNmi = true; 2635691Sgblack@eecs.umich.edu nmiVector = vector; 2645691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) { 2655691Sgblack@eecs.umich.edu pendingExtInt = true; 2665691Sgblack@eecs.umich.edu extIntVector = vector; 2675691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) { 2685691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingInit = true; 2695691Sgblack@eecs.umich.edu initVector = vector; 2706066Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::SIPI && 2716066Sgblack@eecs.umich.edu !pendingStartup && !startedUp) { 2726050Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingStartup = true; 2736050Sgblack@eecs.umich.edu startupVector = vector; 2745691Sgblack@eecs.umich.edu } 2755691Sgblack@eecs.umich.edu } 2765811Sgblack@eecs.umich.edu cpu->wakeup(); 2775691Sgblack@eecs.umich.edu} 2785647Sgblack@eecs.umich.edu 2796041Sgblack@eecs.umich.edu 2806041Sgblack@eecs.umich.eduvoid 2816041Sgblack@eecs.umich.eduX86ISA::Interrupts::setCPU(BaseCPU * newCPU) 2826041Sgblack@eecs.umich.edu{ 2836136Sgblack@eecs.umich.edu assert(newCPU); 2846136Sgblack@eecs.umich.edu if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) { 2856136Sgblack@eecs.umich.edu panic("Local APICs can't be moved between CPUs" 2866136Sgblack@eecs.umich.edu " with different IDs.\n"); 2876136Sgblack@eecs.umich.edu } 2886041Sgblack@eecs.umich.edu cpu = newCPU; 2896136Sgblack@eecs.umich.edu initialApicId = cpu->cpuId(); 2906136Sgblack@eecs.umich.edu regs[APIC_ID] = (initialApicId << 24); 2916041Sgblack@eecs.umich.edu} 2926041Sgblack@eecs.umich.edu 2936041Sgblack@eecs.umich.edu 2946137Sgblack@eecs.umich.eduvoid 2956137Sgblack@eecs.umich.eduX86ISA::Interrupts::init() 2966137Sgblack@eecs.umich.edu{ 2976137Sgblack@eecs.umich.edu BasicPioDevice::init(); 2986137Sgblack@eecs.umich.edu Pc * pc = dynamic_cast<Pc *>(platform); 2996137Sgblack@eecs.umich.edu assert(pc); 3006137Sgblack@eecs.umich.edu pc->southBridge->ioApic->registerLocalApic(initialApicId, this); 3016137Sgblack@eecs.umich.edu} 3026137Sgblack@eecs.umich.edu 3036137Sgblack@eecs.umich.edu 3045651Sgblack@eecs.umich.eduTick 3055651Sgblack@eecs.umich.eduX86ISA::Interrupts::recvMessage(PacketPtr pkt) 3065651Sgblack@eecs.umich.edu{ 3076136Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0); 3085651Sgblack@eecs.umich.edu assert(pkt->cmd == MemCmd::MessageReq); 3095651Sgblack@eecs.umich.edu switch(offset) 3105651Sgblack@eecs.umich.edu { 3115651Sgblack@eecs.umich.edu case 0: 3125654Sgblack@eecs.umich.edu { 3135654Sgblack@eecs.umich.edu TriggerIntMessage message = pkt->get<TriggerIntMessage>(); 3145654Sgblack@eecs.umich.edu DPRINTF(LocalApic, 3155654Sgblack@eecs.umich.edu "Got Trigger Interrupt message with vector %#x.\n", 3165697Snate@binkert.org message.vector); 3175655Sgblack@eecs.umich.edu 3185691Sgblack@eecs.umich.edu requestInterrupt(message.vector, 3195691Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 3205654Sgblack@eecs.umich.edu } 3215651Sgblack@eecs.umich.edu break; 3225651Sgblack@eecs.umich.edu default: 3235651Sgblack@eecs.umich.edu panic("Local apic got unknown interrupt message at offset %#x.\n", 3245651Sgblack@eecs.umich.edu offset); 3255651Sgblack@eecs.umich.edu break; 3265651Sgblack@eecs.umich.edu } 3276064Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 3285651Sgblack@eecs.umich.edu return latency; 3295651Sgblack@eecs.umich.edu} 3305651Sgblack@eecs.umich.edu 3315651Sgblack@eecs.umich.edu 3326065Sgblack@eecs.umich.eduTick 3336065Sgblack@eecs.umich.eduX86ISA::Interrupts::recvResponse(PacketPtr pkt) 3346065Sgblack@eecs.umich.edu{ 3356065Sgblack@eecs.umich.edu assert(!pkt->isError()); 3366065Sgblack@eecs.umich.edu assert(pkt->cmd == MemCmd::MessageResp); 3376069Sgblack@eecs.umich.edu if (--pendingIPIs == 0) { 3386069Sgblack@eecs.umich.edu InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 3396069Sgblack@eecs.umich.edu // Record that the ICR is now idle. 3406069Sgblack@eecs.umich.edu low.deliveryStatus = 0; 3416069Sgblack@eecs.umich.edu regs[APIC_INTERRUPT_COMMAND_LOW] = low; 3426069Sgblack@eecs.umich.edu } 3436065Sgblack@eecs.umich.edu DPRINTF(LocalApic, "ICR is now idle.\n"); 3446065Sgblack@eecs.umich.edu return 0; 3456065Sgblack@eecs.umich.edu} 3466065Sgblack@eecs.umich.edu 3476065Sgblack@eecs.umich.edu 3486041Sgblack@eecs.umich.eduvoid 3496041Sgblack@eecs.umich.eduX86ISA::Interrupts::addressRanges(AddrRangeList &range_list) 3506041Sgblack@eecs.umich.edu{ 3516041Sgblack@eecs.umich.edu range_list.clear(); 3526136Sgblack@eecs.umich.edu Range<Addr> range = RangeEx(x86LocalAPICAddress(initialApicId, 0), 3536136Sgblack@eecs.umich.edu x86LocalAPICAddress(initialApicId, 0) + 3546136Sgblack@eecs.umich.edu PageBytes); 3556061Sgblack@eecs.umich.edu range_list.push_back(range); 3566061Sgblack@eecs.umich.edu pioAddr = range.start; 3576041Sgblack@eecs.umich.edu} 3586041Sgblack@eecs.umich.edu 3596041Sgblack@eecs.umich.edu 3606041Sgblack@eecs.umich.eduvoid 3616041Sgblack@eecs.umich.eduX86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list) 3626041Sgblack@eecs.umich.edu{ 3636041Sgblack@eecs.umich.edu range_list.clear(); 3646136Sgblack@eecs.umich.edu range_list.push_back(RangeEx(x86InterruptAddress(initialApicId, 0), 3656136Sgblack@eecs.umich.edu x86InterruptAddress(initialApicId, 0) + 3666136Sgblack@eecs.umich.edu PhysAddrAPICRangeSize)); 3676041Sgblack@eecs.umich.edu} 3686041Sgblack@eecs.umich.edu 3696041Sgblack@eecs.umich.edu 3705647Sgblack@eecs.umich.eduuint32_t 3715648Sgblack@eecs.umich.eduX86ISA::Interrupts::readReg(ApicRegIndex reg) 3725647Sgblack@eecs.umich.edu{ 3735647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 3745647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 3755647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 3765647Sgblack@eecs.umich.edu } 3775647Sgblack@eecs.umich.edu switch (reg) { 3785647Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 3795647Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 3805647Sgblack@eecs.umich.edu break; 3815647Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 3825647Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 3835647Sgblack@eecs.umich.edu break; 3845647Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 3855647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 3865647Sgblack@eecs.umich.edu break; 3875647Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 3885647Sgblack@eecs.umich.edu { 3895848Sgblack@eecs.umich.edu if (apicTimerEvent.scheduled()) { 3905848Sgblack@eecs.umich.edu assert(clock); 3915848Sgblack@eecs.umich.edu // Compute how many m5 ticks happen per count. 3925848Sgblack@eecs.umich.edu uint64_t ticksPerCount = clock * 3935848Sgblack@eecs.umich.edu divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]); 3945848Sgblack@eecs.umich.edu // Compute how many m5 ticks are left. 3957823Ssteve.reinhardt@amd.com uint64_t val = apicTimerEvent.when() - curTick(); 3965848Sgblack@eecs.umich.edu // Turn that into a count. 3975848Sgblack@eecs.umich.edu val = (val + ticksPerCount - 1) / ticksPerCount; 3985848Sgblack@eecs.umich.edu return val; 3995848Sgblack@eecs.umich.edu } else { 4005848Sgblack@eecs.umich.edu return 0; 4015848Sgblack@eecs.umich.edu } 4025647Sgblack@eecs.umich.edu } 4035647Sgblack@eecs.umich.edu default: 4045647Sgblack@eecs.umich.edu break; 4055647Sgblack@eecs.umich.edu } 4065648Sgblack@eecs.umich.edu return regs[reg]; 4075647Sgblack@eecs.umich.edu} 4085647Sgblack@eecs.umich.edu 4095647Sgblack@eecs.umich.eduvoid 4105648Sgblack@eecs.umich.eduX86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) 4115647Sgblack@eecs.umich.edu{ 4125647Sgblack@eecs.umich.edu uint32_t newVal = val; 4135647Sgblack@eecs.umich.edu if (reg >= APIC_IN_SERVICE(0) && 4145647Sgblack@eecs.umich.edu reg <= APIC_IN_SERVICE(15)) { 4155647Sgblack@eecs.umich.edu panic("Local APIC In-Service registers are unimplemented.\n"); 4165647Sgblack@eecs.umich.edu } 4175647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 4185647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 4195647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 4205647Sgblack@eecs.umich.edu } 4215647Sgblack@eecs.umich.edu if (reg >= APIC_INTERRUPT_REQUEST(0) && 4225647Sgblack@eecs.umich.edu reg <= APIC_INTERRUPT_REQUEST(15)) { 4235647Sgblack@eecs.umich.edu panic("Local APIC Interrupt Request registers " 4245647Sgblack@eecs.umich.edu "are unimplemented.\n"); 4255647Sgblack@eecs.umich.edu } 4265647Sgblack@eecs.umich.edu switch (reg) { 4275647Sgblack@eecs.umich.edu case APIC_ID: 4285647Sgblack@eecs.umich.edu newVal = val & 0xFF; 4295647Sgblack@eecs.umich.edu break; 4305647Sgblack@eecs.umich.edu case APIC_VERSION: 4315647Sgblack@eecs.umich.edu // The Local APIC Version register is read only. 4325647Sgblack@eecs.umich.edu return; 4335647Sgblack@eecs.umich.edu case APIC_TASK_PRIORITY: 4345647Sgblack@eecs.umich.edu newVal = val & 0xFF; 4355647Sgblack@eecs.umich.edu break; 4365647Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 4375647Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 4385647Sgblack@eecs.umich.edu break; 4395647Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 4405647Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 4415647Sgblack@eecs.umich.edu break; 4425647Sgblack@eecs.umich.edu case APIC_EOI: 4435690Sgblack@eecs.umich.edu // Remove the interrupt that just completed from the local apic state. 4445690Sgblack@eecs.umich.edu clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 4455690Sgblack@eecs.umich.edu updateISRV(); 4465690Sgblack@eecs.umich.edu return; 4475647Sgblack@eecs.umich.edu case APIC_LOGICAL_DESTINATION: 4485647Sgblack@eecs.umich.edu newVal = val & 0xFF000000; 4495647Sgblack@eecs.umich.edu break; 4505647Sgblack@eecs.umich.edu case APIC_DESTINATION_FORMAT: 4515647Sgblack@eecs.umich.edu newVal = val | 0x0FFFFFFF; 4525647Sgblack@eecs.umich.edu break; 4535647Sgblack@eecs.umich.edu case APIC_SPURIOUS_INTERRUPT_VECTOR: 4545647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1); 4555647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= val & (1 << 8); 4565647Sgblack@eecs.umich.edu if (val & (1 << 9)) 4575647Sgblack@eecs.umich.edu warn("Focus processor checking not implemented.\n"); 4585647Sgblack@eecs.umich.edu break; 4595647Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 4605647Sgblack@eecs.umich.edu { 4615647Sgblack@eecs.umich.edu if (regs[APIC_INTERNAL_STATE] & 0x1) { 4625647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 4635647Sgblack@eecs.umich.edu newVal = 0; 4645647Sgblack@eecs.umich.edu } else { 4655647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= ULL(0x1); 4665647Sgblack@eecs.umich.edu return; 4675647Sgblack@eecs.umich.edu } 4685647Sgblack@eecs.umich.edu 4695647Sgblack@eecs.umich.edu } 4705647Sgblack@eecs.umich.edu break; 4715647Sgblack@eecs.umich.edu case APIC_INTERRUPT_COMMAND_LOW: 4726046Sgblack@eecs.umich.edu { 4736046Sgblack@eecs.umich.edu InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 4746046Sgblack@eecs.umich.edu // Check if we're already sending an IPI. 4756046Sgblack@eecs.umich.edu if (low.deliveryStatus) { 4766046Sgblack@eecs.umich.edu newVal = low; 4776046Sgblack@eecs.umich.edu break; 4786046Sgblack@eecs.umich.edu } 4796046Sgblack@eecs.umich.edu low = val; 4806046Sgblack@eecs.umich.edu InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH]; 4816046Sgblack@eecs.umich.edu // Record that an IPI is being sent. 4826046Sgblack@eecs.umich.edu low.deliveryStatus = 1; 4836712Snate@binkert.org TriggerIntMessage message = 0; 4846046Sgblack@eecs.umich.edu message.destination = high.destination; 4856046Sgblack@eecs.umich.edu message.vector = low.vector; 4866046Sgblack@eecs.umich.edu message.deliveryMode = low.deliveryMode; 4876046Sgblack@eecs.umich.edu message.destMode = low.destMode; 4886046Sgblack@eecs.umich.edu message.level = low.level; 4896046Sgblack@eecs.umich.edu message.trigger = low.trigger; 4906046Sgblack@eecs.umich.edu bool timing = sys->getMemoryMode() == Enums::timing; 4916065Sgblack@eecs.umich.edu // Be careful no updates of the delivery status bit get lost. 4926065Sgblack@eecs.umich.edu regs[APIC_INTERRUPT_COMMAND_LOW] = low; 4936138Sgblack@eecs.umich.edu ApicList apics; 4946138Sgblack@eecs.umich.edu int numContexts = sys->numContexts(); 4956046Sgblack@eecs.umich.edu switch (low.destShorthand) { 4966046Sgblack@eecs.umich.edu case 0: 4976138Sgblack@eecs.umich.edu if (message.deliveryMode == DeliveryMode::LowestPriority) { 4986138Sgblack@eecs.umich.edu panic("Lowest priority delivery mode " 4996138Sgblack@eecs.umich.edu "IPIs aren't implemented.\n"); 5006138Sgblack@eecs.umich.edu } 5016138Sgblack@eecs.umich.edu if (message.destMode == 1) { 5026138Sgblack@eecs.umich.edu int dest = message.destination; 5036138Sgblack@eecs.umich.edu hack_once("Assuming logical destinations are 1 << id.\n"); 5046138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 5056138Sgblack@eecs.umich.edu if (dest & 0x1) 5066138Sgblack@eecs.umich.edu apics.push_back(i); 5076138Sgblack@eecs.umich.edu dest = dest >> 1; 5086138Sgblack@eecs.umich.edu } 5096138Sgblack@eecs.umich.edu } else { 5106138Sgblack@eecs.umich.edu if (message.destination == 0xFF) { 5116138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 5126138Sgblack@eecs.umich.edu if (i == initialApicId) { 5136138Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5146138Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5156138Sgblack@eecs.umich.edu } else { 5166138Sgblack@eecs.umich.edu apics.push_back(i); 5176138Sgblack@eecs.umich.edu } 5186138Sgblack@eecs.umich.edu } 5196138Sgblack@eecs.umich.edu } else { 5206138Sgblack@eecs.umich.edu if (message.destination == initialApicId) { 5216138Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5226138Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5236138Sgblack@eecs.umich.edu } else { 5246138Sgblack@eecs.umich.edu apics.push_back(message.destination); 5256138Sgblack@eecs.umich.edu } 5266138Sgblack@eecs.umich.edu } 5276138Sgblack@eecs.umich.edu } 5286046Sgblack@eecs.umich.edu break; 5296046Sgblack@eecs.umich.edu case 1: 5306069Sgblack@eecs.umich.edu newVal = val; 5316069Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5326069Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5336046Sgblack@eecs.umich.edu break; 5346046Sgblack@eecs.umich.edu case 2: 5356069Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5366069Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5376069Sgblack@eecs.umich.edu // Fall through 5386046Sgblack@eecs.umich.edu case 3: 5396069Sgblack@eecs.umich.edu { 5406069Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 5416138Sgblack@eecs.umich.edu if (i != initialApicId) { 5426138Sgblack@eecs.umich.edu apics.push_back(i); 5436069Sgblack@eecs.umich.edu } 5446069Sgblack@eecs.umich.edu } 5456069Sgblack@eecs.umich.edu } 5466046Sgblack@eecs.umich.edu break; 5476046Sgblack@eecs.umich.edu } 5486138Sgblack@eecs.umich.edu pendingIPIs += apics.size(); 5496138Sgblack@eecs.umich.edu intPort->sendMessage(apics, message, timing); 5506138Sgblack@eecs.umich.edu newVal = regs[APIC_INTERRUPT_COMMAND_LOW]; 5516046Sgblack@eecs.umich.edu } 5525647Sgblack@eecs.umich.edu break; 5535647Sgblack@eecs.umich.edu case APIC_LVT_TIMER: 5545647Sgblack@eecs.umich.edu case APIC_LVT_THERMAL_SENSOR: 5555647Sgblack@eecs.umich.edu case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS: 5565647Sgblack@eecs.umich.edu case APIC_LVT_LINT0: 5575647Sgblack@eecs.umich.edu case APIC_LVT_LINT1: 5585647Sgblack@eecs.umich.edu case APIC_LVT_ERROR: 5595647Sgblack@eecs.umich.edu { 5605647Sgblack@eecs.umich.edu uint64_t readOnlyMask = (1 << 12) | (1 << 14); 5615647Sgblack@eecs.umich.edu newVal = (val & ~readOnlyMask) | 5625647Sgblack@eecs.umich.edu (regs[reg] & readOnlyMask); 5635647Sgblack@eecs.umich.edu } 5645647Sgblack@eecs.umich.edu break; 5655647Sgblack@eecs.umich.edu case APIC_INITIAL_COUNT: 5665648Sgblack@eecs.umich.edu { 5675648Sgblack@eecs.umich.edu assert(clock); 5685648Sgblack@eecs.umich.edu newVal = bits(val, 31, 0); 5695848Sgblack@eecs.umich.edu // Compute how many timer ticks we're being programmed for. 5705848Sgblack@eecs.umich.edu uint64_t newCount = newVal * 5715848Sgblack@eecs.umich.edu (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION])); 5725648Sgblack@eecs.umich.edu // Schedule on the edge of the next tick plus the new count. 5737823Ssteve.reinhardt@amd.com Tick offset = curTick() % clock; 5745648Sgblack@eecs.umich.edu if (offset) { 5755648Sgblack@eecs.umich.edu reschedule(apicTimerEvent, 5767823Ssteve.reinhardt@amd.com curTick() + (newCount + 1) * clock - offset, true); 5775648Sgblack@eecs.umich.edu } else { 5785648Sgblack@eecs.umich.edu reschedule(apicTimerEvent, 5797823Ssteve.reinhardt@amd.com curTick() + newCount * clock, true); 5805648Sgblack@eecs.umich.edu } 5815648Sgblack@eecs.umich.edu } 5825647Sgblack@eecs.umich.edu break; 5835647Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 5845647Sgblack@eecs.umich.edu //Local APIC Current Count register is read only. 5855647Sgblack@eecs.umich.edu return; 5865647Sgblack@eecs.umich.edu case APIC_DIVIDE_CONFIGURATION: 5875647Sgblack@eecs.umich.edu newVal = val & 0xB; 5885647Sgblack@eecs.umich.edu break; 5895647Sgblack@eecs.umich.edu default: 5905647Sgblack@eecs.umich.edu break; 5915647Sgblack@eecs.umich.edu } 5925648Sgblack@eecs.umich.edu regs[reg] = newVal; 5935647Sgblack@eecs.umich.edu return; 5945647Sgblack@eecs.umich.edu} 5955647Sgblack@eecs.umich.edu 5966041Sgblack@eecs.umich.edu 5976041Sgblack@eecs.umich.eduX86ISA::Interrupts::Interrupts(Params * p) : 5987900Shestness@cs.utexas.edu BasicPioDevice(p), IntDev(this, p->int_latency), latency(p->pio_latency), 5997900Shestness@cs.utexas.edu clock(0), 6006041Sgblack@eecs.umich.edu apicTimerEvent(this), 6016041Sgblack@eecs.umich.edu pendingSmi(false), smiVector(0), 6026041Sgblack@eecs.umich.edu pendingNmi(false), nmiVector(0), 6036041Sgblack@eecs.umich.edu pendingExtInt(false), extIntVector(0), 6046041Sgblack@eecs.umich.edu pendingInit(false), initVector(0), 6056050Sgblack@eecs.umich.edu pendingStartup(false), startupVector(0), 6066069Sgblack@eecs.umich.edu startedUp(false), pendingUnmaskableInt(false), 6076136Sgblack@eecs.umich.edu pendingIPIs(0), cpu(NULL) 6086041Sgblack@eecs.umich.edu{ 6096041Sgblack@eecs.umich.edu pioSize = PageBytes; 6106041Sgblack@eecs.umich.edu memset(regs, 0, sizeof(regs)); 6116041Sgblack@eecs.umich.edu //Set the local apic DFR to the flat model. 6126041Sgblack@eecs.umich.edu regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1); 6136041Sgblack@eecs.umich.edu ISRV = 0; 6146041Sgblack@eecs.umich.edu IRRV = 0; 6156041Sgblack@eecs.umich.edu} 6166041Sgblack@eecs.umich.edu 6176041Sgblack@eecs.umich.edu 6185654Sgblack@eecs.umich.edubool 6195704Snate@binkert.orgX86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const 6205654Sgblack@eecs.umich.edu{ 6215654Sgblack@eecs.umich.edu RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS); 6225689Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6235689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n"); 6245654Sgblack@eecs.umich.edu return true; 6255689Sgblack@eecs.umich.edu } 6265655Sgblack@eecs.umich.edu if (rflags.intf) { 6275689Sgblack@eecs.umich.edu if (pendingExtInt) { 6285689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending external interrupt.\n"); 6295655Sgblack@eecs.umich.edu return true; 6305689Sgblack@eecs.umich.edu } 6315655Sgblack@eecs.umich.edu if (IRRV > ISRV && bits(IRRV, 7, 4) > 6325689Sgblack@eecs.umich.edu bits(regs[APIC_TASK_PRIORITY], 7, 4)) { 6335689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending regular interrupt.\n"); 6345655Sgblack@eecs.umich.edu return true; 6355689Sgblack@eecs.umich.edu } 6365654Sgblack@eecs.umich.edu } 6375654Sgblack@eecs.umich.edu return false; 6385654Sgblack@eecs.umich.edu} 6395654Sgblack@eecs.umich.edu 6405654Sgblack@eecs.umich.eduFault 6415704Snate@binkert.orgX86ISA::Interrupts::getInterrupt(ThreadContext *tc) 6425654Sgblack@eecs.umich.edu{ 6435704Snate@binkert.org assert(checkInterrupts(tc)); 6445655Sgblack@eecs.umich.edu // These are all probably fairly uncommon, so we'll make them easier to 6455655Sgblack@eecs.umich.edu // check for. 6465655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6475655Sgblack@eecs.umich.edu if (pendingSmi) { 6485689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated SMI fault object.\n"); 6495655Sgblack@eecs.umich.edu return new SystemManagementInterrupt(); 6505655Sgblack@eecs.umich.edu } else if (pendingNmi) { 6515689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated NMI fault object.\n"); 6525691Sgblack@eecs.umich.edu return new NonMaskableInterrupt(nmiVector); 6535655Sgblack@eecs.umich.edu } else if (pendingInit) { 6545689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated INIT fault object.\n"); 6555691Sgblack@eecs.umich.edu return new InitInterrupt(initVector); 6566050Sgblack@eecs.umich.edu } else if (pendingStartup) { 6576050Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generating SIPI fault object.\n"); 6586050Sgblack@eecs.umich.edu return new StartupInterrupt(startupVector); 6595655Sgblack@eecs.umich.edu } else { 6605655Sgblack@eecs.umich.edu panic("pendingUnmaskableInt set, but no unmaskable " 6615655Sgblack@eecs.umich.edu "ints were pending.\n"); 6625655Sgblack@eecs.umich.edu return NoFault; 6635655Sgblack@eecs.umich.edu } 6645655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 6655689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated external interrupt fault object.\n"); 6665691Sgblack@eecs.umich.edu return new ExternalInterrupt(extIntVector); 6675655Sgblack@eecs.umich.edu } else { 6685689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated regular interrupt fault object.\n"); 6695655Sgblack@eecs.umich.edu // The only thing left are fixed and lowest priority interrupts. 6705655Sgblack@eecs.umich.edu return new ExternalInterrupt(IRRV); 6715655Sgblack@eecs.umich.edu } 6725654Sgblack@eecs.umich.edu} 6735654Sgblack@eecs.umich.edu 6745654Sgblack@eecs.umich.eduvoid 6755704Snate@binkert.orgX86ISA::Interrupts::updateIntrInfo(ThreadContext *tc) 6765654Sgblack@eecs.umich.edu{ 6775704Snate@binkert.org assert(checkInterrupts(tc)); 6785655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6795655Sgblack@eecs.umich.edu if (pendingSmi) { 6805689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "SMI sent to core.\n"); 6815655Sgblack@eecs.umich.edu pendingSmi = false; 6825655Sgblack@eecs.umich.edu } else if (pendingNmi) { 6835689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "NMI sent to core.\n"); 6845655Sgblack@eecs.umich.edu pendingNmi = false; 6855655Sgblack@eecs.umich.edu } else if (pendingInit) { 6865689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Init sent to core.\n"); 6875655Sgblack@eecs.umich.edu pendingInit = false; 6886066Sgblack@eecs.umich.edu startedUp = false; 6896050Sgblack@eecs.umich.edu } else if (pendingStartup) { 6906050Sgblack@eecs.umich.edu DPRINTF(LocalApic, "SIPI sent to core.\n"); 6916050Sgblack@eecs.umich.edu pendingStartup = false; 6926066Sgblack@eecs.umich.edu startedUp = true; 6935655Sgblack@eecs.umich.edu } 6946050Sgblack@eecs.umich.edu if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup)) 6955655Sgblack@eecs.umich.edu pendingUnmaskableInt = false; 6965655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 6975655Sgblack@eecs.umich.edu pendingExtInt = false; 6985655Sgblack@eecs.umich.edu } else { 6995689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV); 7005655Sgblack@eecs.umich.edu // Mark the interrupt as "in service". 7015655Sgblack@eecs.umich.edu ISRV = IRRV; 7025655Sgblack@eecs.umich.edu setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 7035655Sgblack@eecs.umich.edu // Clear it out of the IRR. 7045655Sgblack@eecs.umich.edu clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV); 7055655Sgblack@eecs.umich.edu updateIRRV(); 7065655Sgblack@eecs.umich.edu } 7075654Sgblack@eecs.umich.edu} 7085654Sgblack@eecs.umich.edu 7095647Sgblack@eecs.umich.eduX86ISA::Interrupts * 7105647Sgblack@eecs.umich.eduX86LocalApicParams::create() 7115647Sgblack@eecs.umich.edu{ 7125647Sgblack@eecs.umich.edu return new X86ISA::Interrupts(this); 7135647Sgblack@eecs.umich.edu} 714