interrupts.cc revision 6136
15647Sgblack@eecs.umich.edu/* 25647Sgblack@eecs.umich.edu * Copyright (c) 2008 The Hewlett-Packard Development Company 35647Sgblack@eecs.umich.edu * All rights reserved. 45647Sgblack@eecs.umich.edu * 55647Sgblack@eecs.umich.edu * Redistribution and use of this software in source and binary forms, 65647Sgblack@eecs.umich.edu * with or without modification, are permitted provided that the 75647Sgblack@eecs.umich.edu * following conditions are met: 85647Sgblack@eecs.umich.edu * 95647Sgblack@eecs.umich.edu * The software must be used only for Non-Commercial Use which means any 105647Sgblack@eecs.umich.edu * use which is NOT directed to receiving any direct monetary 115647Sgblack@eecs.umich.edu * compensation for, or commercial advantage from such use. Illustrative 125647Sgblack@eecs.umich.edu * examples of non-commercial use are academic research, personal study, 135647Sgblack@eecs.umich.edu * teaching, education and corporate research & development. 145647Sgblack@eecs.umich.edu * Illustrative examples of commercial use are distributing products for 155647Sgblack@eecs.umich.edu * commercial advantage and providing services using the software for 165647Sgblack@eecs.umich.edu * commercial advantage. 175647Sgblack@eecs.umich.edu * 185647Sgblack@eecs.umich.edu * If you wish to use this software or functionality therein that may be 195647Sgblack@eecs.umich.edu * covered by patents for commercial use, please contact: 205647Sgblack@eecs.umich.edu * Director of Intellectual Property Licensing 215647Sgblack@eecs.umich.edu * Office of Strategy and Technology 225647Sgblack@eecs.umich.edu * Hewlett-Packard Company 235647Sgblack@eecs.umich.edu * 1501 Page Mill Road 245647Sgblack@eecs.umich.edu * Palo Alto, California 94304 255647Sgblack@eecs.umich.edu * 265647Sgblack@eecs.umich.edu * Redistributions of source code must retain the above copyright notice, 275647Sgblack@eecs.umich.edu * this list of conditions and the following disclaimer. Redistributions 285647Sgblack@eecs.umich.edu * in binary form must reproduce the above copyright notice, this list of 295647Sgblack@eecs.umich.edu * conditions and the following disclaimer in the documentation and/or 305647Sgblack@eecs.umich.edu * other materials provided with the distribution. Neither the name of 315647Sgblack@eecs.umich.edu * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 325647Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 335647Sgblack@eecs.umich.edu * this software without specific prior written permission. No right of 345647Sgblack@eecs.umich.edu * sublicense is granted herewith. Derivatives of the software and 355647Sgblack@eecs.umich.edu * output created using the software may be prepared, but only for 365647Sgblack@eecs.umich.edu * Non-Commercial Uses. Derivatives of the software may be shared with 375647Sgblack@eecs.umich.edu * others provided: (i) the others agree to abide by the list of 385647Sgblack@eecs.umich.edu * conditions herein which includes the Non-Commercial Use restrictions; 395647Sgblack@eecs.umich.edu * and (ii) such Derivatives of the software include the above copyright 405647Sgblack@eecs.umich.edu * notice to acknowledge the contribution from this software where 415647Sgblack@eecs.umich.edu * applicable, this list of conditions and the disclaimer below. 425647Sgblack@eecs.umich.edu * 435647Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 445647Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 455647Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 465647Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 475647Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 485647Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 495647Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 505647Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 515647Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 525647Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 535647Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 545647Sgblack@eecs.umich.edu * 555647Sgblack@eecs.umich.edu * Authors: Gabe Black 565647Sgblack@eecs.umich.edu */ 575647Sgblack@eecs.umich.edu 585648Sgblack@eecs.umich.edu#include "arch/x86/apicregs.hh" 595647Sgblack@eecs.umich.edu#include "arch/x86/interrupts.hh" 605654Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 615647Sgblack@eecs.umich.edu#include "cpu/base.hh" 625654Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 636046Sgblack@eecs.umich.edu#include "sim/system.hh" 645647Sgblack@eecs.umich.edu 655648Sgblack@eecs.umich.eduint 665648Sgblack@eecs.umich.edudivideFromConf(uint32_t conf) 675647Sgblack@eecs.umich.edu{ 685647Sgblack@eecs.umich.edu // This figures out what division we want from the division configuration 695647Sgblack@eecs.umich.edu // register in the local APIC. The encoding is a little odd but it can 705647Sgblack@eecs.umich.edu // be deciphered fairly easily. 715647Sgblack@eecs.umich.edu int shift = ((conf & 0x8) >> 1) | (conf & 0x3); 725647Sgblack@eecs.umich.edu shift = (shift + 1) % 8; 735647Sgblack@eecs.umich.edu return 1 << shift; 745647Sgblack@eecs.umich.edu} 755647Sgblack@eecs.umich.edu 765648Sgblack@eecs.umich.edunamespace X86ISA 775647Sgblack@eecs.umich.edu{ 785648Sgblack@eecs.umich.edu 795648Sgblack@eecs.umich.eduApicRegIndex 805648Sgblack@eecs.umich.edudecodeAddr(Addr paddr) 815648Sgblack@eecs.umich.edu{ 825648Sgblack@eecs.umich.edu ApicRegIndex regNum; 835648Sgblack@eecs.umich.edu paddr &= ~mask(3); 845648Sgblack@eecs.umich.edu switch (paddr) 855648Sgblack@eecs.umich.edu { 865648Sgblack@eecs.umich.edu case 0x20: 875648Sgblack@eecs.umich.edu regNum = APIC_ID; 885648Sgblack@eecs.umich.edu break; 895648Sgblack@eecs.umich.edu case 0x30: 905648Sgblack@eecs.umich.edu regNum = APIC_VERSION; 915648Sgblack@eecs.umich.edu break; 925648Sgblack@eecs.umich.edu case 0x80: 935648Sgblack@eecs.umich.edu regNum = APIC_TASK_PRIORITY; 945648Sgblack@eecs.umich.edu break; 955648Sgblack@eecs.umich.edu case 0x90: 965648Sgblack@eecs.umich.edu regNum = APIC_ARBITRATION_PRIORITY; 975648Sgblack@eecs.umich.edu break; 985648Sgblack@eecs.umich.edu case 0xA0: 995648Sgblack@eecs.umich.edu regNum = APIC_PROCESSOR_PRIORITY; 1005648Sgblack@eecs.umich.edu break; 1015648Sgblack@eecs.umich.edu case 0xB0: 1025648Sgblack@eecs.umich.edu regNum = APIC_EOI; 1035648Sgblack@eecs.umich.edu break; 1045648Sgblack@eecs.umich.edu case 0xD0: 1055648Sgblack@eecs.umich.edu regNum = APIC_LOGICAL_DESTINATION; 1065648Sgblack@eecs.umich.edu break; 1075648Sgblack@eecs.umich.edu case 0xE0: 1085648Sgblack@eecs.umich.edu regNum = APIC_DESTINATION_FORMAT; 1095648Sgblack@eecs.umich.edu break; 1105648Sgblack@eecs.umich.edu case 0xF0: 1115648Sgblack@eecs.umich.edu regNum = APIC_SPURIOUS_INTERRUPT_VECTOR; 1125648Sgblack@eecs.umich.edu break; 1135648Sgblack@eecs.umich.edu case 0x100: 1145648Sgblack@eecs.umich.edu case 0x108: 1155648Sgblack@eecs.umich.edu case 0x110: 1165648Sgblack@eecs.umich.edu case 0x118: 1175648Sgblack@eecs.umich.edu case 0x120: 1185648Sgblack@eecs.umich.edu case 0x128: 1195648Sgblack@eecs.umich.edu case 0x130: 1205648Sgblack@eecs.umich.edu case 0x138: 1215648Sgblack@eecs.umich.edu case 0x140: 1225648Sgblack@eecs.umich.edu case 0x148: 1235648Sgblack@eecs.umich.edu case 0x150: 1245648Sgblack@eecs.umich.edu case 0x158: 1255648Sgblack@eecs.umich.edu case 0x160: 1265648Sgblack@eecs.umich.edu case 0x168: 1275648Sgblack@eecs.umich.edu case 0x170: 1285648Sgblack@eecs.umich.edu case 0x178: 1295648Sgblack@eecs.umich.edu regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8); 1305648Sgblack@eecs.umich.edu break; 1315648Sgblack@eecs.umich.edu case 0x180: 1325648Sgblack@eecs.umich.edu case 0x188: 1335648Sgblack@eecs.umich.edu case 0x190: 1345648Sgblack@eecs.umich.edu case 0x198: 1355648Sgblack@eecs.umich.edu case 0x1A0: 1365648Sgblack@eecs.umich.edu case 0x1A8: 1375648Sgblack@eecs.umich.edu case 0x1B0: 1385648Sgblack@eecs.umich.edu case 0x1B8: 1395648Sgblack@eecs.umich.edu case 0x1C0: 1405648Sgblack@eecs.umich.edu case 0x1C8: 1415648Sgblack@eecs.umich.edu case 0x1D0: 1425648Sgblack@eecs.umich.edu case 0x1D8: 1435648Sgblack@eecs.umich.edu case 0x1E0: 1445648Sgblack@eecs.umich.edu case 0x1E8: 1455648Sgblack@eecs.umich.edu case 0x1F0: 1465648Sgblack@eecs.umich.edu case 0x1F8: 1475648Sgblack@eecs.umich.edu regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8); 1485648Sgblack@eecs.umich.edu break; 1495648Sgblack@eecs.umich.edu case 0x200: 1505648Sgblack@eecs.umich.edu case 0x208: 1515648Sgblack@eecs.umich.edu case 0x210: 1525648Sgblack@eecs.umich.edu case 0x218: 1535648Sgblack@eecs.umich.edu case 0x220: 1545648Sgblack@eecs.umich.edu case 0x228: 1555648Sgblack@eecs.umich.edu case 0x230: 1565648Sgblack@eecs.umich.edu case 0x238: 1575648Sgblack@eecs.umich.edu case 0x240: 1585648Sgblack@eecs.umich.edu case 0x248: 1595648Sgblack@eecs.umich.edu case 0x250: 1605648Sgblack@eecs.umich.edu case 0x258: 1615648Sgblack@eecs.umich.edu case 0x260: 1625648Sgblack@eecs.umich.edu case 0x268: 1635648Sgblack@eecs.umich.edu case 0x270: 1645648Sgblack@eecs.umich.edu case 0x278: 1655648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8); 1665648Sgblack@eecs.umich.edu break; 1675648Sgblack@eecs.umich.edu case 0x280: 1685648Sgblack@eecs.umich.edu regNum = APIC_ERROR_STATUS; 1695648Sgblack@eecs.umich.edu break; 1705648Sgblack@eecs.umich.edu case 0x300: 1715648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_LOW; 1725648Sgblack@eecs.umich.edu break; 1735648Sgblack@eecs.umich.edu case 0x310: 1745648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_HIGH; 1755648Sgblack@eecs.umich.edu break; 1765648Sgblack@eecs.umich.edu case 0x320: 1775648Sgblack@eecs.umich.edu regNum = APIC_LVT_TIMER; 1785648Sgblack@eecs.umich.edu break; 1795648Sgblack@eecs.umich.edu case 0x330: 1805648Sgblack@eecs.umich.edu regNum = APIC_LVT_THERMAL_SENSOR; 1815648Sgblack@eecs.umich.edu break; 1825648Sgblack@eecs.umich.edu case 0x340: 1835648Sgblack@eecs.umich.edu regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS; 1845648Sgblack@eecs.umich.edu break; 1855648Sgblack@eecs.umich.edu case 0x350: 1865648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT0; 1875648Sgblack@eecs.umich.edu break; 1885648Sgblack@eecs.umich.edu case 0x360: 1895648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT1; 1905648Sgblack@eecs.umich.edu break; 1915648Sgblack@eecs.umich.edu case 0x370: 1925648Sgblack@eecs.umich.edu regNum = APIC_LVT_ERROR; 1935648Sgblack@eecs.umich.edu break; 1945648Sgblack@eecs.umich.edu case 0x380: 1955648Sgblack@eecs.umich.edu regNum = APIC_INITIAL_COUNT; 1965648Sgblack@eecs.umich.edu break; 1975648Sgblack@eecs.umich.edu case 0x390: 1985648Sgblack@eecs.umich.edu regNum = APIC_CURRENT_COUNT; 1995648Sgblack@eecs.umich.edu break; 2005648Sgblack@eecs.umich.edu case 0x3E0: 2015648Sgblack@eecs.umich.edu regNum = APIC_DIVIDE_CONFIGURATION; 2025648Sgblack@eecs.umich.edu break; 2035648Sgblack@eecs.umich.edu default: 2045648Sgblack@eecs.umich.edu // A reserved register field. 2055648Sgblack@eecs.umich.edu panic("Accessed reserved register field %#x.\n", paddr); 2065648Sgblack@eecs.umich.edu break; 2075648Sgblack@eecs.umich.edu } 2085648Sgblack@eecs.umich.edu return regNum; 2095648Sgblack@eecs.umich.edu} 2105648Sgblack@eecs.umich.edu} 2115648Sgblack@eecs.umich.edu 2125648Sgblack@eecs.umich.eduTick 2135648Sgblack@eecs.umich.eduX86ISA::Interrupts::read(PacketPtr pkt) 2145648Sgblack@eecs.umich.edu{ 2155648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 2165648Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 2175648Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2185648Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 2195648Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 2205648Sgblack@eecs.umich.edu uint32_t val = htog(readReg(reg)); 2215649Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2225649Sgblack@eecs.umich.edu "Reading Local APIC register %d at offset %#x as %#x.\n", 2235649Sgblack@eecs.umich.edu reg, offset, val); 2245648Sgblack@eecs.umich.edu pkt->setData(((uint8_t *)&val) + (offset & mask(3))); 2255898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2265648Sgblack@eecs.umich.edu return latency; 2275648Sgblack@eecs.umich.edu} 2285648Sgblack@eecs.umich.edu 2295648Sgblack@eecs.umich.eduTick 2305648Sgblack@eecs.umich.eduX86ISA::Interrupts::write(PacketPtr pkt) 2315648Sgblack@eecs.umich.edu{ 2325648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 2335648Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 2345648Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2355648Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 2365648Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 2375648Sgblack@eecs.umich.edu uint32_t val = regs[reg]; 2385648Sgblack@eecs.umich.edu pkt->writeData(((uint8_t *)&val) + (offset & mask(3))); 2395649Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2405649Sgblack@eecs.umich.edu "Writing Local APIC register %d at offset %#x as %#x.\n", 2415649Sgblack@eecs.umich.edu reg, offset, gtoh(val)); 2425648Sgblack@eecs.umich.edu setReg(reg, gtoh(val)); 2435898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2445648Sgblack@eecs.umich.edu return latency; 2455647Sgblack@eecs.umich.edu} 2465691Sgblack@eecs.umich.eduvoid 2475691Sgblack@eecs.umich.eduX86ISA::Interrupts::requestInterrupt(uint8_t vector, 2485691Sgblack@eecs.umich.edu uint8_t deliveryMode, bool level) 2495691Sgblack@eecs.umich.edu{ 2505691Sgblack@eecs.umich.edu /* 2515691Sgblack@eecs.umich.edu * Fixed and lowest-priority delivery mode interrupts are handled 2525691Sgblack@eecs.umich.edu * using the IRR/ISR registers, checking against the TPR, etc. 2535691Sgblack@eecs.umich.edu * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through. 2545691Sgblack@eecs.umich.edu */ 2555691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::Fixed || 2565691Sgblack@eecs.umich.edu deliveryMode == DeliveryMode::LowestPriority) { 2575691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2585691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2595691Sgblack@eecs.umich.edu // Queue up the interrupt in the IRR. 2605691Sgblack@eecs.umich.edu if (vector > IRRV) 2615691Sgblack@eecs.umich.edu IRRV = vector; 2625691Sgblack@eecs.umich.edu if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) { 2635691Sgblack@eecs.umich.edu setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector); 2645691Sgblack@eecs.umich.edu if (level) { 2655691Sgblack@eecs.umich.edu setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2665691Sgblack@eecs.umich.edu } else { 2675691Sgblack@eecs.umich.edu clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2685691Sgblack@eecs.umich.edu } 2695691Sgblack@eecs.umich.edu } 2705691Sgblack@eecs.umich.edu } else if (!DeliveryMode::isReserved(deliveryMode)) { 2715691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2725691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2735691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::SMI && !pendingSmi) { 2745691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingSmi = true; 2755691Sgblack@eecs.umich.edu smiVector = vector; 2765691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) { 2775691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingNmi = true; 2785691Sgblack@eecs.umich.edu nmiVector = vector; 2795691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) { 2805691Sgblack@eecs.umich.edu pendingExtInt = true; 2815691Sgblack@eecs.umich.edu extIntVector = vector; 2825691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) { 2835691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingInit = true; 2845691Sgblack@eecs.umich.edu initVector = vector; 2856066Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::SIPI && 2866066Sgblack@eecs.umich.edu !pendingStartup && !startedUp) { 2876050Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingStartup = true; 2886050Sgblack@eecs.umich.edu startupVector = vector; 2895691Sgblack@eecs.umich.edu } 2905691Sgblack@eecs.umich.edu } 2915811Sgblack@eecs.umich.edu cpu->wakeup(); 2925691Sgblack@eecs.umich.edu} 2935647Sgblack@eecs.umich.edu 2946041Sgblack@eecs.umich.edu 2956041Sgblack@eecs.umich.eduvoid 2966041Sgblack@eecs.umich.eduX86ISA::Interrupts::setCPU(BaseCPU * newCPU) 2976041Sgblack@eecs.umich.edu{ 2986136Sgblack@eecs.umich.edu assert(newCPU); 2996136Sgblack@eecs.umich.edu if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) { 3006136Sgblack@eecs.umich.edu panic("Local APICs can't be moved between CPUs" 3016136Sgblack@eecs.umich.edu " with different IDs.\n"); 3026136Sgblack@eecs.umich.edu } 3036041Sgblack@eecs.umich.edu cpu = newCPU; 3046136Sgblack@eecs.umich.edu initialApicId = cpu->cpuId(); 3056136Sgblack@eecs.umich.edu regs[APIC_ID] = (initialApicId << 24); 3066041Sgblack@eecs.umich.edu} 3076041Sgblack@eecs.umich.edu 3086041Sgblack@eecs.umich.edu 3095651Sgblack@eecs.umich.eduTick 3105651Sgblack@eecs.umich.eduX86ISA::Interrupts::recvMessage(PacketPtr pkt) 3115651Sgblack@eecs.umich.edu{ 3126136Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0); 3135651Sgblack@eecs.umich.edu assert(pkt->cmd == MemCmd::MessageReq); 3145651Sgblack@eecs.umich.edu switch(offset) 3155651Sgblack@eecs.umich.edu { 3165651Sgblack@eecs.umich.edu case 0: 3175654Sgblack@eecs.umich.edu { 3185654Sgblack@eecs.umich.edu TriggerIntMessage message = pkt->get<TriggerIntMessage>(); 3195654Sgblack@eecs.umich.edu DPRINTF(LocalApic, 3205654Sgblack@eecs.umich.edu "Got Trigger Interrupt message with vector %#x.\n", 3215697Snate@binkert.org message.vector); 3225655Sgblack@eecs.umich.edu 3235691Sgblack@eecs.umich.edu requestInterrupt(message.vector, 3245691Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 3255654Sgblack@eecs.umich.edu } 3265651Sgblack@eecs.umich.edu break; 3275651Sgblack@eecs.umich.edu default: 3285651Sgblack@eecs.umich.edu panic("Local apic got unknown interrupt message at offset %#x.\n", 3295651Sgblack@eecs.umich.edu offset); 3305651Sgblack@eecs.umich.edu break; 3315651Sgblack@eecs.umich.edu } 3326064Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 3335651Sgblack@eecs.umich.edu return latency; 3345651Sgblack@eecs.umich.edu} 3355651Sgblack@eecs.umich.edu 3365651Sgblack@eecs.umich.edu 3376065Sgblack@eecs.umich.eduTick 3386065Sgblack@eecs.umich.eduX86ISA::Interrupts::recvResponse(PacketPtr pkt) 3396065Sgblack@eecs.umich.edu{ 3406065Sgblack@eecs.umich.edu assert(!pkt->isError()); 3416065Sgblack@eecs.umich.edu assert(pkt->cmd == MemCmd::MessageResp); 3426069Sgblack@eecs.umich.edu if (--pendingIPIs == 0) { 3436069Sgblack@eecs.umich.edu InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 3446069Sgblack@eecs.umich.edu // Record that the ICR is now idle. 3456069Sgblack@eecs.umich.edu low.deliveryStatus = 0; 3466069Sgblack@eecs.umich.edu regs[APIC_INTERRUPT_COMMAND_LOW] = low; 3476069Sgblack@eecs.umich.edu } 3486065Sgblack@eecs.umich.edu delete pkt->req; 3496065Sgblack@eecs.umich.edu delete pkt; 3506065Sgblack@eecs.umich.edu DPRINTF(LocalApic, "ICR is now idle.\n"); 3516065Sgblack@eecs.umich.edu return 0; 3526065Sgblack@eecs.umich.edu} 3536065Sgblack@eecs.umich.edu 3546065Sgblack@eecs.umich.edu 3556041Sgblack@eecs.umich.eduvoid 3566041Sgblack@eecs.umich.eduX86ISA::Interrupts::addressRanges(AddrRangeList &range_list) 3576041Sgblack@eecs.umich.edu{ 3586041Sgblack@eecs.umich.edu range_list.clear(); 3596136Sgblack@eecs.umich.edu Range<Addr> range = RangeEx(x86LocalAPICAddress(initialApicId, 0), 3606136Sgblack@eecs.umich.edu x86LocalAPICAddress(initialApicId, 0) + 3616136Sgblack@eecs.umich.edu PageBytes); 3626061Sgblack@eecs.umich.edu range_list.push_back(range); 3636061Sgblack@eecs.umich.edu pioAddr = range.start; 3646041Sgblack@eecs.umich.edu} 3656041Sgblack@eecs.umich.edu 3666041Sgblack@eecs.umich.edu 3676041Sgblack@eecs.umich.eduvoid 3686041Sgblack@eecs.umich.eduX86ISA::Interrupts::getIntAddrRange(AddrRangeList &range_list) 3696041Sgblack@eecs.umich.edu{ 3706041Sgblack@eecs.umich.edu range_list.clear(); 3716136Sgblack@eecs.umich.edu range_list.push_back(RangeEx(x86InterruptAddress(initialApicId, 0), 3726136Sgblack@eecs.umich.edu x86InterruptAddress(initialApicId, 0) + 3736136Sgblack@eecs.umich.edu PhysAddrAPICRangeSize)); 3746041Sgblack@eecs.umich.edu} 3756041Sgblack@eecs.umich.edu 3766041Sgblack@eecs.umich.edu 3775647Sgblack@eecs.umich.eduuint32_t 3785648Sgblack@eecs.umich.eduX86ISA::Interrupts::readReg(ApicRegIndex reg) 3795647Sgblack@eecs.umich.edu{ 3805647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 3815647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 3825647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 3835647Sgblack@eecs.umich.edu } 3845647Sgblack@eecs.umich.edu switch (reg) { 3855647Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 3865647Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 3875647Sgblack@eecs.umich.edu break; 3885647Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 3895647Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 3905647Sgblack@eecs.umich.edu break; 3915647Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 3925647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 3935647Sgblack@eecs.umich.edu break; 3945647Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 3955647Sgblack@eecs.umich.edu { 3965848Sgblack@eecs.umich.edu if (apicTimerEvent.scheduled()) { 3975848Sgblack@eecs.umich.edu assert(clock); 3985848Sgblack@eecs.umich.edu // Compute how many m5 ticks happen per count. 3995848Sgblack@eecs.umich.edu uint64_t ticksPerCount = clock * 4005848Sgblack@eecs.umich.edu divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]); 4015848Sgblack@eecs.umich.edu // Compute how many m5 ticks are left. 4025848Sgblack@eecs.umich.edu uint64_t val = apicTimerEvent.when() - curTick; 4035848Sgblack@eecs.umich.edu // Turn that into a count. 4045848Sgblack@eecs.umich.edu val = (val + ticksPerCount - 1) / ticksPerCount; 4055848Sgblack@eecs.umich.edu return val; 4065848Sgblack@eecs.umich.edu } else { 4075848Sgblack@eecs.umich.edu return 0; 4085848Sgblack@eecs.umich.edu } 4095647Sgblack@eecs.umich.edu } 4105647Sgblack@eecs.umich.edu default: 4115647Sgblack@eecs.umich.edu break; 4125647Sgblack@eecs.umich.edu } 4135648Sgblack@eecs.umich.edu return regs[reg]; 4145647Sgblack@eecs.umich.edu} 4155647Sgblack@eecs.umich.edu 4165647Sgblack@eecs.umich.eduvoid 4175648Sgblack@eecs.umich.eduX86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) 4185647Sgblack@eecs.umich.edu{ 4195647Sgblack@eecs.umich.edu uint32_t newVal = val; 4205647Sgblack@eecs.umich.edu if (reg >= APIC_IN_SERVICE(0) && 4215647Sgblack@eecs.umich.edu reg <= APIC_IN_SERVICE(15)) { 4225647Sgblack@eecs.umich.edu panic("Local APIC In-Service registers are unimplemented.\n"); 4235647Sgblack@eecs.umich.edu } 4245647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 4255647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 4265647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 4275647Sgblack@eecs.umich.edu } 4285647Sgblack@eecs.umich.edu if (reg >= APIC_INTERRUPT_REQUEST(0) && 4295647Sgblack@eecs.umich.edu reg <= APIC_INTERRUPT_REQUEST(15)) { 4305647Sgblack@eecs.umich.edu panic("Local APIC Interrupt Request registers " 4315647Sgblack@eecs.umich.edu "are unimplemented.\n"); 4325647Sgblack@eecs.umich.edu } 4335647Sgblack@eecs.umich.edu switch (reg) { 4345647Sgblack@eecs.umich.edu case APIC_ID: 4355647Sgblack@eecs.umich.edu newVal = val & 0xFF; 4365647Sgblack@eecs.umich.edu break; 4375647Sgblack@eecs.umich.edu case APIC_VERSION: 4385647Sgblack@eecs.umich.edu // The Local APIC Version register is read only. 4395647Sgblack@eecs.umich.edu return; 4405647Sgblack@eecs.umich.edu case APIC_TASK_PRIORITY: 4415647Sgblack@eecs.umich.edu newVal = val & 0xFF; 4425647Sgblack@eecs.umich.edu break; 4435647Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 4445647Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 4455647Sgblack@eecs.umich.edu break; 4465647Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 4475647Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 4485647Sgblack@eecs.umich.edu break; 4495647Sgblack@eecs.umich.edu case APIC_EOI: 4505690Sgblack@eecs.umich.edu // Remove the interrupt that just completed from the local apic state. 4515690Sgblack@eecs.umich.edu clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 4525690Sgblack@eecs.umich.edu updateISRV(); 4535690Sgblack@eecs.umich.edu return; 4545647Sgblack@eecs.umich.edu case APIC_LOGICAL_DESTINATION: 4555647Sgblack@eecs.umich.edu newVal = val & 0xFF000000; 4565647Sgblack@eecs.umich.edu break; 4575647Sgblack@eecs.umich.edu case APIC_DESTINATION_FORMAT: 4585647Sgblack@eecs.umich.edu newVal = val | 0x0FFFFFFF; 4595647Sgblack@eecs.umich.edu break; 4605647Sgblack@eecs.umich.edu case APIC_SPURIOUS_INTERRUPT_VECTOR: 4615647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1); 4625647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= val & (1 << 8); 4635647Sgblack@eecs.umich.edu if (val & (1 << 9)) 4645647Sgblack@eecs.umich.edu warn("Focus processor checking not implemented.\n"); 4655647Sgblack@eecs.umich.edu break; 4665647Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 4675647Sgblack@eecs.umich.edu { 4685647Sgblack@eecs.umich.edu if (regs[APIC_INTERNAL_STATE] & 0x1) { 4695647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 4705647Sgblack@eecs.umich.edu newVal = 0; 4715647Sgblack@eecs.umich.edu } else { 4725647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= ULL(0x1); 4735647Sgblack@eecs.umich.edu return; 4745647Sgblack@eecs.umich.edu } 4755647Sgblack@eecs.umich.edu 4765647Sgblack@eecs.umich.edu } 4775647Sgblack@eecs.umich.edu break; 4785647Sgblack@eecs.umich.edu case APIC_INTERRUPT_COMMAND_LOW: 4796046Sgblack@eecs.umich.edu { 4806046Sgblack@eecs.umich.edu InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 4816046Sgblack@eecs.umich.edu // Check if we're already sending an IPI. 4826046Sgblack@eecs.umich.edu if (low.deliveryStatus) { 4836046Sgblack@eecs.umich.edu newVal = low; 4846046Sgblack@eecs.umich.edu break; 4856046Sgblack@eecs.umich.edu } 4866046Sgblack@eecs.umich.edu low = val; 4876046Sgblack@eecs.umich.edu InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH]; 4886046Sgblack@eecs.umich.edu // Record that an IPI is being sent. 4896046Sgblack@eecs.umich.edu low.deliveryStatus = 1; 4906046Sgblack@eecs.umich.edu TriggerIntMessage message; 4916046Sgblack@eecs.umich.edu message.destination = high.destination; 4926046Sgblack@eecs.umich.edu message.vector = low.vector; 4936046Sgblack@eecs.umich.edu message.deliveryMode = low.deliveryMode; 4946046Sgblack@eecs.umich.edu message.destMode = low.destMode; 4956046Sgblack@eecs.umich.edu message.level = low.level; 4966046Sgblack@eecs.umich.edu message.trigger = low.trigger; 4976046Sgblack@eecs.umich.edu bool timing = sys->getMemoryMode() == Enums::timing; 4986065Sgblack@eecs.umich.edu // Be careful no updates of the delivery status bit get lost. 4996065Sgblack@eecs.umich.edu regs[APIC_INTERRUPT_COMMAND_LOW] = low; 5006046Sgblack@eecs.umich.edu switch (low.destShorthand) { 5016046Sgblack@eecs.umich.edu case 0: 5026069Sgblack@eecs.umich.edu pendingIPIs++; 5036046Sgblack@eecs.umich.edu intPort->sendMessage(message, timing); 5046065Sgblack@eecs.umich.edu newVal = regs[APIC_INTERRUPT_COMMAND_LOW]; 5056046Sgblack@eecs.umich.edu break; 5066046Sgblack@eecs.umich.edu case 1: 5076069Sgblack@eecs.umich.edu newVal = val; 5086069Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5096069Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5106046Sgblack@eecs.umich.edu break; 5116046Sgblack@eecs.umich.edu case 2: 5126069Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5136069Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5146069Sgblack@eecs.umich.edu // Fall through 5156046Sgblack@eecs.umich.edu case 3: 5166069Sgblack@eecs.umich.edu { 5176069Sgblack@eecs.umich.edu int numContexts = sys->numContexts(); 5186069Sgblack@eecs.umich.edu pendingIPIs += (numContexts - 1); 5196069Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 5206069Sgblack@eecs.umich.edu int thisId = sys->getThreadContext(i)->contextId(); 5216136Sgblack@eecs.umich.edu if (thisId != initialApicId) { 5226069Sgblack@eecs.umich.edu PacketPtr pkt = buildIntRequest(thisId, message); 5236069Sgblack@eecs.umich.edu if (timing) 5246069Sgblack@eecs.umich.edu intPort->sendMessageTiming(pkt, latency); 5256069Sgblack@eecs.umich.edu else 5266069Sgblack@eecs.umich.edu intPort->sendMessageAtomic(pkt); 5276069Sgblack@eecs.umich.edu } 5286069Sgblack@eecs.umich.edu } 5296069Sgblack@eecs.umich.edu } 5306069Sgblack@eecs.umich.edu newVal = regs[APIC_INTERRUPT_COMMAND_LOW]; 5316046Sgblack@eecs.umich.edu break; 5326046Sgblack@eecs.umich.edu } 5336046Sgblack@eecs.umich.edu } 5345647Sgblack@eecs.umich.edu break; 5355647Sgblack@eecs.umich.edu case APIC_LVT_TIMER: 5365647Sgblack@eecs.umich.edu case APIC_LVT_THERMAL_SENSOR: 5375647Sgblack@eecs.umich.edu case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS: 5385647Sgblack@eecs.umich.edu case APIC_LVT_LINT0: 5395647Sgblack@eecs.umich.edu case APIC_LVT_LINT1: 5405647Sgblack@eecs.umich.edu case APIC_LVT_ERROR: 5415647Sgblack@eecs.umich.edu { 5425647Sgblack@eecs.umich.edu uint64_t readOnlyMask = (1 << 12) | (1 << 14); 5435647Sgblack@eecs.umich.edu newVal = (val & ~readOnlyMask) | 5445647Sgblack@eecs.umich.edu (regs[reg] & readOnlyMask); 5455647Sgblack@eecs.umich.edu } 5465647Sgblack@eecs.umich.edu break; 5475647Sgblack@eecs.umich.edu case APIC_INITIAL_COUNT: 5485648Sgblack@eecs.umich.edu { 5495648Sgblack@eecs.umich.edu assert(clock); 5505648Sgblack@eecs.umich.edu newVal = bits(val, 31, 0); 5515848Sgblack@eecs.umich.edu // Compute how many timer ticks we're being programmed for. 5525848Sgblack@eecs.umich.edu uint64_t newCount = newVal * 5535848Sgblack@eecs.umich.edu (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION])); 5545648Sgblack@eecs.umich.edu // Schedule on the edge of the next tick plus the new count. 5555848Sgblack@eecs.umich.edu Tick offset = curTick % clock; 5565648Sgblack@eecs.umich.edu if (offset) { 5575648Sgblack@eecs.umich.edu reschedule(apicTimerEvent, 5585848Sgblack@eecs.umich.edu curTick + (newCount + 1) * clock - offset, true); 5595648Sgblack@eecs.umich.edu } else { 5605648Sgblack@eecs.umich.edu reschedule(apicTimerEvent, 5615848Sgblack@eecs.umich.edu curTick + newCount * clock, true); 5625648Sgblack@eecs.umich.edu } 5635648Sgblack@eecs.umich.edu } 5645647Sgblack@eecs.umich.edu break; 5655647Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 5665647Sgblack@eecs.umich.edu //Local APIC Current Count register is read only. 5675647Sgblack@eecs.umich.edu return; 5685647Sgblack@eecs.umich.edu case APIC_DIVIDE_CONFIGURATION: 5695647Sgblack@eecs.umich.edu newVal = val & 0xB; 5705647Sgblack@eecs.umich.edu break; 5715647Sgblack@eecs.umich.edu default: 5725647Sgblack@eecs.umich.edu break; 5735647Sgblack@eecs.umich.edu } 5745648Sgblack@eecs.umich.edu regs[reg] = newVal; 5755647Sgblack@eecs.umich.edu return; 5765647Sgblack@eecs.umich.edu} 5775647Sgblack@eecs.umich.edu 5786041Sgblack@eecs.umich.edu 5796041Sgblack@eecs.umich.eduX86ISA::Interrupts::Interrupts(Params * p) : 5806041Sgblack@eecs.umich.edu BasicPioDevice(p), IntDev(this), latency(p->pio_latency), clock(0), 5816041Sgblack@eecs.umich.edu apicTimerEvent(this), 5826041Sgblack@eecs.umich.edu pendingSmi(false), smiVector(0), 5836041Sgblack@eecs.umich.edu pendingNmi(false), nmiVector(0), 5846041Sgblack@eecs.umich.edu pendingExtInt(false), extIntVector(0), 5856041Sgblack@eecs.umich.edu pendingInit(false), initVector(0), 5866050Sgblack@eecs.umich.edu pendingStartup(false), startupVector(0), 5876069Sgblack@eecs.umich.edu startedUp(false), pendingUnmaskableInt(false), 5886136Sgblack@eecs.umich.edu pendingIPIs(0), cpu(NULL) 5896041Sgblack@eecs.umich.edu{ 5906041Sgblack@eecs.umich.edu pioSize = PageBytes; 5916041Sgblack@eecs.umich.edu memset(regs, 0, sizeof(regs)); 5926041Sgblack@eecs.umich.edu //Set the local apic DFR to the flat model. 5936041Sgblack@eecs.umich.edu regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1); 5946041Sgblack@eecs.umich.edu ISRV = 0; 5956041Sgblack@eecs.umich.edu IRRV = 0; 5966041Sgblack@eecs.umich.edu} 5976041Sgblack@eecs.umich.edu 5986041Sgblack@eecs.umich.edu 5995654Sgblack@eecs.umich.edubool 6005704Snate@binkert.orgX86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const 6015654Sgblack@eecs.umich.edu{ 6025654Sgblack@eecs.umich.edu RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS); 6035689Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6045689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n"); 6055654Sgblack@eecs.umich.edu return true; 6065689Sgblack@eecs.umich.edu } 6075655Sgblack@eecs.umich.edu if (rflags.intf) { 6085689Sgblack@eecs.umich.edu if (pendingExtInt) { 6095689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending external interrupt.\n"); 6105655Sgblack@eecs.umich.edu return true; 6115689Sgblack@eecs.umich.edu } 6125655Sgblack@eecs.umich.edu if (IRRV > ISRV && bits(IRRV, 7, 4) > 6135689Sgblack@eecs.umich.edu bits(regs[APIC_TASK_PRIORITY], 7, 4)) { 6145689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending regular interrupt.\n"); 6155655Sgblack@eecs.umich.edu return true; 6165689Sgblack@eecs.umich.edu } 6175654Sgblack@eecs.umich.edu } 6185654Sgblack@eecs.umich.edu return false; 6195654Sgblack@eecs.umich.edu} 6205654Sgblack@eecs.umich.edu 6215654Sgblack@eecs.umich.eduFault 6225704Snate@binkert.orgX86ISA::Interrupts::getInterrupt(ThreadContext *tc) 6235654Sgblack@eecs.umich.edu{ 6245704Snate@binkert.org assert(checkInterrupts(tc)); 6255655Sgblack@eecs.umich.edu // These are all probably fairly uncommon, so we'll make them easier to 6265655Sgblack@eecs.umich.edu // check for. 6275655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6285655Sgblack@eecs.umich.edu if (pendingSmi) { 6295689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated SMI fault object.\n"); 6305655Sgblack@eecs.umich.edu return new SystemManagementInterrupt(); 6315655Sgblack@eecs.umich.edu } else if (pendingNmi) { 6325689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated NMI fault object.\n"); 6335691Sgblack@eecs.umich.edu return new NonMaskableInterrupt(nmiVector); 6345655Sgblack@eecs.umich.edu } else if (pendingInit) { 6355689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated INIT fault object.\n"); 6365691Sgblack@eecs.umich.edu return new InitInterrupt(initVector); 6376050Sgblack@eecs.umich.edu } else if (pendingStartup) { 6386050Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generating SIPI fault object.\n"); 6396050Sgblack@eecs.umich.edu return new StartupInterrupt(startupVector); 6405655Sgblack@eecs.umich.edu } else { 6415655Sgblack@eecs.umich.edu panic("pendingUnmaskableInt set, but no unmaskable " 6425655Sgblack@eecs.umich.edu "ints were pending.\n"); 6435655Sgblack@eecs.umich.edu return NoFault; 6445655Sgblack@eecs.umich.edu } 6455655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 6465689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated external interrupt fault object.\n"); 6475691Sgblack@eecs.umich.edu return new ExternalInterrupt(extIntVector); 6485655Sgblack@eecs.umich.edu } else { 6495689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated regular interrupt fault object.\n"); 6505655Sgblack@eecs.umich.edu // The only thing left are fixed and lowest priority interrupts. 6515655Sgblack@eecs.umich.edu return new ExternalInterrupt(IRRV); 6525655Sgblack@eecs.umich.edu } 6535654Sgblack@eecs.umich.edu} 6545654Sgblack@eecs.umich.edu 6555654Sgblack@eecs.umich.eduvoid 6565704Snate@binkert.orgX86ISA::Interrupts::updateIntrInfo(ThreadContext *tc) 6575654Sgblack@eecs.umich.edu{ 6585704Snate@binkert.org assert(checkInterrupts(tc)); 6595655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6605655Sgblack@eecs.umich.edu if (pendingSmi) { 6615689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "SMI sent to core.\n"); 6625655Sgblack@eecs.umich.edu pendingSmi = false; 6635655Sgblack@eecs.umich.edu } else if (pendingNmi) { 6645689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "NMI sent to core.\n"); 6655655Sgblack@eecs.umich.edu pendingNmi = false; 6665655Sgblack@eecs.umich.edu } else if (pendingInit) { 6675689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Init sent to core.\n"); 6685655Sgblack@eecs.umich.edu pendingInit = false; 6696066Sgblack@eecs.umich.edu startedUp = false; 6706050Sgblack@eecs.umich.edu } else if (pendingStartup) { 6716050Sgblack@eecs.umich.edu DPRINTF(LocalApic, "SIPI sent to core.\n"); 6726050Sgblack@eecs.umich.edu pendingStartup = false; 6736066Sgblack@eecs.umich.edu startedUp = true; 6745655Sgblack@eecs.umich.edu } 6756050Sgblack@eecs.umich.edu if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup)) 6765655Sgblack@eecs.umich.edu pendingUnmaskableInt = false; 6775655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 6785655Sgblack@eecs.umich.edu pendingExtInt = false; 6795655Sgblack@eecs.umich.edu } else { 6805689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV); 6815655Sgblack@eecs.umich.edu // Mark the interrupt as "in service". 6825655Sgblack@eecs.umich.edu ISRV = IRRV; 6835655Sgblack@eecs.umich.edu setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 6845655Sgblack@eecs.umich.edu // Clear it out of the IRR. 6855655Sgblack@eecs.umich.edu clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV); 6865655Sgblack@eecs.umich.edu updateIRRV(); 6875655Sgblack@eecs.umich.edu } 6885654Sgblack@eecs.umich.edu} 6895654Sgblack@eecs.umich.edu 6905647Sgblack@eecs.umich.eduX86ISA::Interrupts * 6915647Sgblack@eecs.umich.eduX86LocalApicParams::create() 6925647Sgblack@eecs.umich.edu{ 6935647Sgblack@eecs.umich.edu return new X86ISA::Interrupts(this); 6945647Sgblack@eecs.umich.edu} 695