interrupts.cc revision 5898
15647Sgblack@eecs.umich.edu/* 25647Sgblack@eecs.umich.edu * Copyright (c) 2008 The Hewlett-Packard Development Company 35647Sgblack@eecs.umich.edu * All rights reserved. 45647Sgblack@eecs.umich.edu * 55647Sgblack@eecs.umich.edu * Redistribution and use of this software in source and binary forms, 65647Sgblack@eecs.umich.edu * with or without modification, are permitted provided that the 75647Sgblack@eecs.umich.edu * following conditions are met: 85647Sgblack@eecs.umich.edu * 95647Sgblack@eecs.umich.edu * The software must be used only for Non-Commercial Use which means any 105647Sgblack@eecs.umich.edu * use which is NOT directed to receiving any direct monetary 115647Sgblack@eecs.umich.edu * compensation for, or commercial advantage from such use. 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Derivatives of the software may be shared with 375647Sgblack@eecs.umich.edu * others provided: (i) the others agree to abide by the list of 385647Sgblack@eecs.umich.edu * conditions herein which includes the Non-Commercial Use restrictions; 395647Sgblack@eecs.umich.edu * and (ii) such Derivatives of the software include the above copyright 405647Sgblack@eecs.umich.edu * notice to acknowledge the contribution from this software where 415647Sgblack@eecs.umich.edu * applicable, this list of conditions and the disclaimer below. 425647Sgblack@eecs.umich.edu * 435647Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 445647Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 455647Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 465647Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 475647Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 485647Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 495647Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 505647Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 515647Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 525647Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 535647Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 545647Sgblack@eecs.umich.edu * 555647Sgblack@eecs.umich.edu * Authors: Gabe Black 565647Sgblack@eecs.umich.edu */ 575647Sgblack@eecs.umich.edu 585648Sgblack@eecs.umich.edu#include "arch/x86/apicregs.hh" 595647Sgblack@eecs.umich.edu#include "arch/x86/interrupts.hh" 605654Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 615647Sgblack@eecs.umich.edu#include "cpu/base.hh" 625654Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 635647Sgblack@eecs.umich.edu 645648Sgblack@eecs.umich.eduint 655648Sgblack@eecs.umich.edudivideFromConf(uint32_t conf) 665647Sgblack@eecs.umich.edu{ 675647Sgblack@eecs.umich.edu // This figures out what division we want from the division configuration 685647Sgblack@eecs.umich.edu // register in the local APIC. The encoding is a little odd but it can 695647Sgblack@eecs.umich.edu // be deciphered fairly easily. 705647Sgblack@eecs.umich.edu int shift = ((conf & 0x8) >> 1) | (conf & 0x3); 715647Sgblack@eecs.umich.edu shift = (shift + 1) % 8; 725647Sgblack@eecs.umich.edu return 1 << shift; 735647Sgblack@eecs.umich.edu} 745647Sgblack@eecs.umich.edu 755648Sgblack@eecs.umich.edunamespace X86ISA 765647Sgblack@eecs.umich.edu{ 775648Sgblack@eecs.umich.edu 785648Sgblack@eecs.umich.eduApicRegIndex 795648Sgblack@eecs.umich.edudecodeAddr(Addr paddr) 805648Sgblack@eecs.umich.edu{ 815648Sgblack@eecs.umich.edu ApicRegIndex regNum; 825648Sgblack@eecs.umich.edu paddr &= ~mask(3); 835648Sgblack@eecs.umich.edu switch (paddr) 845648Sgblack@eecs.umich.edu { 855648Sgblack@eecs.umich.edu case 0x20: 865648Sgblack@eecs.umich.edu regNum = APIC_ID; 875648Sgblack@eecs.umich.edu break; 885648Sgblack@eecs.umich.edu case 0x30: 895648Sgblack@eecs.umich.edu regNum = APIC_VERSION; 905648Sgblack@eecs.umich.edu break; 915648Sgblack@eecs.umich.edu case 0x80: 925648Sgblack@eecs.umich.edu regNum = APIC_TASK_PRIORITY; 935648Sgblack@eecs.umich.edu break; 945648Sgblack@eecs.umich.edu case 0x90: 955648Sgblack@eecs.umich.edu regNum = APIC_ARBITRATION_PRIORITY; 965648Sgblack@eecs.umich.edu break; 975648Sgblack@eecs.umich.edu case 0xA0: 985648Sgblack@eecs.umich.edu regNum = APIC_PROCESSOR_PRIORITY; 995648Sgblack@eecs.umich.edu break; 1005648Sgblack@eecs.umich.edu case 0xB0: 1015648Sgblack@eecs.umich.edu regNum = APIC_EOI; 1025648Sgblack@eecs.umich.edu break; 1035648Sgblack@eecs.umich.edu case 0xD0: 1045648Sgblack@eecs.umich.edu regNum = APIC_LOGICAL_DESTINATION; 1055648Sgblack@eecs.umich.edu break; 1065648Sgblack@eecs.umich.edu case 0xE0: 1075648Sgblack@eecs.umich.edu regNum = APIC_DESTINATION_FORMAT; 1085648Sgblack@eecs.umich.edu break; 1095648Sgblack@eecs.umich.edu case 0xF0: 1105648Sgblack@eecs.umich.edu regNum = APIC_SPURIOUS_INTERRUPT_VECTOR; 1115648Sgblack@eecs.umich.edu break; 1125648Sgblack@eecs.umich.edu case 0x100: 1135648Sgblack@eecs.umich.edu case 0x108: 1145648Sgblack@eecs.umich.edu case 0x110: 1155648Sgblack@eecs.umich.edu case 0x118: 1165648Sgblack@eecs.umich.edu case 0x120: 1175648Sgblack@eecs.umich.edu case 0x128: 1185648Sgblack@eecs.umich.edu case 0x130: 1195648Sgblack@eecs.umich.edu case 0x138: 1205648Sgblack@eecs.umich.edu case 0x140: 1215648Sgblack@eecs.umich.edu case 0x148: 1225648Sgblack@eecs.umich.edu case 0x150: 1235648Sgblack@eecs.umich.edu case 0x158: 1245648Sgblack@eecs.umich.edu case 0x160: 1255648Sgblack@eecs.umich.edu case 0x168: 1265648Sgblack@eecs.umich.edu case 0x170: 1275648Sgblack@eecs.umich.edu case 0x178: 1285648Sgblack@eecs.umich.edu regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x8); 1295648Sgblack@eecs.umich.edu break; 1305648Sgblack@eecs.umich.edu case 0x180: 1315648Sgblack@eecs.umich.edu case 0x188: 1325648Sgblack@eecs.umich.edu case 0x190: 1335648Sgblack@eecs.umich.edu case 0x198: 1345648Sgblack@eecs.umich.edu case 0x1A0: 1355648Sgblack@eecs.umich.edu case 0x1A8: 1365648Sgblack@eecs.umich.edu case 0x1B0: 1375648Sgblack@eecs.umich.edu case 0x1B8: 1385648Sgblack@eecs.umich.edu case 0x1C0: 1395648Sgblack@eecs.umich.edu case 0x1C8: 1405648Sgblack@eecs.umich.edu case 0x1D0: 1415648Sgblack@eecs.umich.edu case 0x1D8: 1425648Sgblack@eecs.umich.edu case 0x1E0: 1435648Sgblack@eecs.umich.edu case 0x1E8: 1445648Sgblack@eecs.umich.edu case 0x1F0: 1455648Sgblack@eecs.umich.edu case 0x1F8: 1465648Sgblack@eecs.umich.edu regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x8); 1475648Sgblack@eecs.umich.edu break; 1485648Sgblack@eecs.umich.edu case 0x200: 1495648Sgblack@eecs.umich.edu case 0x208: 1505648Sgblack@eecs.umich.edu case 0x210: 1515648Sgblack@eecs.umich.edu case 0x218: 1525648Sgblack@eecs.umich.edu case 0x220: 1535648Sgblack@eecs.umich.edu case 0x228: 1545648Sgblack@eecs.umich.edu case 0x230: 1555648Sgblack@eecs.umich.edu case 0x238: 1565648Sgblack@eecs.umich.edu case 0x240: 1575648Sgblack@eecs.umich.edu case 0x248: 1585648Sgblack@eecs.umich.edu case 0x250: 1595648Sgblack@eecs.umich.edu case 0x258: 1605648Sgblack@eecs.umich.edu case 0x260: 1615648Sgblack@eecs.umich.edu case 0x268: 1625648Sgblack@eecs.umich.edu case 0x270: 1635648Sgblack@eecs.umich.edu case 0x278: 1645648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x8); 1655648Sgblack@eecs.umich.edu break; 1665648Sgblack@eecs.umich.edu case 0x280: 1675648Sgblack@eecs.umich.edu regNum = APIC_ERROR_STATUS; 1685648Sgblack@eecs.umich.edu break; 1695648Sgblack@eecs.umich.edu case 0x300: 1705648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_LOW; 1715648Sgblack@eecs.umich.edu break; 1725648Sgblack@eecs.umich.edu case 0x310: 1735648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_HIGH; 1745648Sgblack@eecs.umich.edu break; 1755648Sgblack@eecs.umich.edu case 0x320: 1765648Sgblack@eecs.umich.edu regNum = APIC_LVT_TIMER; 1775648Sgblack@eecs.umich.edu break; 1785648Sgblack@eecs.umich.edu case 0x330: 1795648Sgblack@eecs.umich.edu regNum = APIC_LVT_THERMAL_SENSOR; 1805648Sgblack@eecs.umich.edu break; 1815648Sgblack@eecs.umich.edu case 0x340: 1825648Sgblack@eecs.umich.edu regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS; 1835648Sgblack@eecs.umich.edu break; 1845648Sgblack@eecs.umich.edu case 0x350: 1855648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT0; 1865648Sgblack@eecs.umich.edu break; 1875648Sgblack@eecs.umich.edu case 0x360: 1885648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT1; 1895648Sgblack@eecs.umich.edu break; 1905648Sgblack@eecs.umich.edu case 0x370: 1915648Sgblack@eecs.umich.edu regNum = APIC_LVT_ERROR; 1925648Sgblack@eecs.umich.edu break; 1935648Sgblack@eecs.umich.edu case 0x380: 1945648Sgblack@eecs.umich.edu regNum = APIC_INITIAL_COUNT; 1955648Sgblack@eecs.umich.edu break; 1965648Sgblack@eecs.umich.edu case 0x390: 1975648Sgblack@eecs.umich.edu regNum = APIC_CURRENT_COUNT; 1985648Sgblack@eecs.umich.edu break; 1995648Sgblack@eecs.umich.edu case 0x3E0: 2005648Sgblack@eecs.umich.edu regNum = APIC_DIVIDE_CONFIGURATION; 2015648Sgblack@eecs.umich.edu break; 2025648Sgblack@eecs.umich.edu default: 2035648Sgblack@eecs.umich.edu // A reserved register field. 2045648Sgblack@eecs.umich.edu panic("Accessed reserved register field %#x.\n", paddr); 2055648Sgblack@eecs.umich.edu break; 2065648Sgblack@eecs.umich.edu } 2075648Sgblack@eecs.umich.edu return regNum; 2085648Sgblack@eecs.umich.edu} 2095648Sgblack@eecs.umich.edu} 2105648Sgblack@eecs.umich.edu 2115648Sgblack@eecs.umich.eduTick 2125648Sgblack@eecs.umich.eduX86ISA::Interrupts::read(PacketPtr pkt) 2135648Sgblack@eecs.umich.edu{ 2145648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 2155648Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 2165648Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2175648Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 2185648Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 2195648Sgblack@eecs.umich.edu uint32_t val = htog(readReg(reg)); 2205649Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2215649Sgblack@eecs.umich.edu "Reading Local APIC register %d at offset %#x as %#x.\n", 2225649Sgblack@eecs.umich.edu reg, offset, val); 2235648Sgblack@eecs.umich.edu pkt->setData(((uint8_t *)&val) + (offset & mask(3))); 2245898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2255648Sgblack@eecs.umich.edu return latency; 2265648Sgblack@eecs.umich.edu} 2275648Sgblack@eecs.umich.edu 2285648Sgblack@eecs.umich.eduTick 2295648Sgblack@eecs.umich.eduX86ISA::Interrupts::write(PacketPtr pkt) 2305648Sgblack@eecs.umich.edu{ 2315648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 2325648Sgblack@eecs.umich.edu //Make sure we're at least only accessing one register. 2335648Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2345648Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 2355648Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 2365648Sgblack@eecs.umich.edu uint32_t val = regs[reg]; 2375648Sgblack@eecs.umich.edu pkt->writeData(((uint8_t *)&val) + (offset & mask(3))); 2385649Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2395649Sgblack@eecs.umich.edu "Writing Local APIC register %d at offset %#x as %#x.\n", 2405649Sgblack@eecs.umich.edu reg, offset, gtoh(val)); 2415648Sgblack@eecs.umich.edu setReg(reg, gtoh(val)); 2425898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2435648Sgblack@eecs.umich.edu return latency; 2445647Sgblack@eecs.umich.edu} 2455691Sgblack@eecs.umich.eduvoid 2465691Sgblack@eecs.umich.eduX86ISA::Interrupts::requestInterrupt(uint8_t vector, 2475691Sgblack@eecs.umich.edu uint8_t deliveryMode, bool level) 2485691Sgblack@eecs.umich.edu{ 2495691Sgblack@eecs.umich.edu /* 2505691Sgblack@eecs.umich.edu * Fixed and lowest-priority delivery mode interrupts are handled 2515691Sgblack@eecs.umich.edu * using the IRR/ISR registers, checking against the TPR, etc. 2525691Sgblack@eecs.umich.edu * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through. 2535691Sgblack@eecs.umich.edu */ 2545691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::Fixed || 2555691Sgblack@eecs.umich.edu deliveryMode == DeliveryMode::LowestPriority) { 2565691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2575691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2585691Sgblack@eecs.umich.edu // Queue up the interrupt in the IRR. 2595691Sgblack@eecs.umich.edu if (vector > IRRV) 2605691Sgblack@eecs.umich.edu IRRV = vector; 2615691Sgblack@eecs.umich.edu if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) { 2625691Sgblack@eecs.umich.edu setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector); 2635691Sgblack@eecs.umich.edu if (level) { 2645691Sgblack@eecs.umich.edu setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2655691Sgblack@eecs.umich.edu } else { 2665691Sgblack@eecs.umich.edu clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2675691Sgblack@eecs.umich.edu } 2685691Sgblack@eecs.umich.edu } 2695691Sgblack@eecs.umich.edu } else if (!DeliveryMode::isReserved(deliveryMode)) { 2705691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2715691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2725691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::SMI && !pendingSmi) { 2735691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingSmi = true; 2745691Sgblack@eecs.umich.edu smiVector = vector; 2755691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) { 2765691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingNmi = true; 2775691Sgblack@eecs.umich.edu nmiVector = vector; 2785691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) { 2795691Sgblack@eecs.umich.edu pendingExtInt = true; 2805691Sgblack@eecs.umich.edu extIntVector = vector; 2815691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) { 2825691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingInit = true; 2835691Sgblack@eecs.umich.edu initVector = vector; 2845691Sgblack@eecs.umich.edu } 2855691Sgblack@eecs.umich.edu } 2865811Sgblack@eecs.umich.edu cpu->wakeup(); 2875691Sgblack@eecs.umich.edu} 2885647Sgblack@eecs.umich.edu 2895651Sgblack@eecs.umich.eduTick 2905651Sgblack@eecs.umich.eduX86ISA::Interrupts::recvMessage(PacketPtr pkt) 2915651Sgblack@eecs.umich.edu{ 2925654Sgblack@eecs.umich.edu uint8_t id = 0; 2935654Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - x86InterruptAddress(id, 0); 2945651Sgblack@eecs.umich.edu assert(pkt->cmd == MemCmd::MessageReq); 2955651Sgblack@eecs.umich.edu switch(offset) 2965651Sgblack@eecs.umich.edu { 2975651Sgblack@eecs.umich.edu case 0: 2985654Sgblack@eecs.umich.edu { 2995654Sgblack@eecs.umich.edu TriggerIntMessage message = pkt->get<TriggerIntMessage>(); 3005654Sgblack@eecs.umich.edu DPRINTF(LocalApic, 3015654Sgblack@eecs.umich.edu "Got Trigger Interrupt message with vector %#x.\n", 3025697Snate@binkert.org message.vector); 3035654Sgblack@eecs.umich.edu // Make sure we're really supposed to get this. 3045654Sgblack@eecs.umich.edu assert((message.destMode == 0 && message.destination == id) || 3055654Sgblack@eecs.umich.edu (bits((int)message.destination, id))); 3065655Sgblack@eecs.umich.edu 3075691Sgblack@eecs.umich.edu requestInterrupt(message.vector, 3085691Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 3095654Sgblack@eecs.umich.edu } 3105651Sgblack@eecs.umich.edu break; 3115651Sgblack@eecs.umich.edu default: 3125651Sgblack@eecs.umich.edu panic("Local apic got unknown interrupt message at offset %#x.\n", 3135651Sgblack@eecs.umich.edu offset); 3145651Sgblack@eecs.umich.edu break; 3155651Sgblack@eecs.umich.edu } 3165651Sgblack@eecs.umich.edu delete pkt->req; 3175651Sgblack@eecs.umich.edu delete pkt; 3185651Sgblack@eecs.umich.edu return latency; 3195651Sgblack@eecs.umich.edu} 3205651Sgblack@eecs.umich.edu 3215651Sgblack@eecs.umich.edu 3225647Sgblack@eecs.umich.eduuint32_t 3235648Sgblack@eecs.umich.eduX86ISA::Interrupts::readReg(ApicRegIndex reg) 3245647Sgblack@eecs.umich.edu{ 3255647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 3265647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 3275647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 3285647Sgblack@eecs.umich.edu } 3295647Sgblack@eecs.umich.edu switch (reg) { 3305647Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 3315647Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 3325647Sgblack@eecs.umich.edu break; 3335647Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 3345647Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 3355647Sgblack@eecs.umich.edu break; 3365647Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 3375647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 3385647Sgblack@eecs.umich.edu break; 3395647Sgblack@eecs.umich.edu case APIC_INTERRUPT_COMMAND_LOW: 3405647Sgblack@eecs.umich.edu panic("Local APIC Interrupt Command low" 3415647Sgblack@eecs.umich.edu " register unimplemented.\n"); 3425647Sgblack@eecs.umich.edu break; 3435647Sgblack@eecs.umich.edu case APIC_INTERRUPT_COMMAND_HIGH: 3445647Sgblack@eecs.umich.edu panic("Local APIC Interrupt Command high" 3455647Sgblack@eecs.umich.edu " register unimplemented.\n"); 3465647Sgblack@eecs.umich.edu break; 3475647Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 3485647Sgblack@eecs.umich.edu { 3495848Sgblack@eecs.umich.edu if (apicTimerEvent.scheduled()) { 3505848Sgblack@eecs.umich.edu assert(clock); 3515848Sgblack@eecs.umich.edu // Compute how many m5 ticks happen per count. 3525848Sgblack@eecs.umich.edu uint64_t ticksPerCount = clock * 3535848Sgblack@eecs.umich.edu divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]); 3545848Sgblack@eecs.umich.edu // Compute how many m5 ticks are left. 3555848Sgblack@eecs.umich.edu uint64_t val = apicTimerEvent.when() - curTick; 3565848Sgblack@eecs.umich.edu // Turn that into a count. 3575848Sgblack@eecs.umich.edu val = (val + ticksPerCount - 1) / ticksPerCount; 3585848Sgblack@eecs.umich.edu return val; 3595848Sgblack@eecs.umich.edu } else { 3605848Sgblack@eecs.umich.edu return 0; 3615848Sgblack@eecs.umich.edu } 3625647Sgblack@eecs.umich.edu } 3635647Sgblack@eecs.umich.edu default: 3645647Sgblack@eecs.umich.edu break; 3655647Sgblack@eecs.umich.edu } 3665648Sgblack@eecs.umich.edu return regs[reg]; 3675647Sgblack@eecs.umich.edu} 3685647Sgblack@eecs.umich.edu 3695647Sgblack@eecs.umich.eduvoid 3705648Sgblack@eecs.umich.eduX86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) 3715647Sgblack@eecs.umich.edu{ 3725647Sgblack@eecs.umich.edu uint32_t newVal = val; 3735647Sgblack@eecs.umich.edu if (reg >= APIC_IN_SERVICE(0) && 3745647Sgblack@eecs.umich.edu reg <= APIC_IN_SERVICE(15)) { 3755647Sgblack@eecs.umich.edu panic("Local APIC In-Service registers are unimplemented.\n"); 3765647Sgblack@eecs.umich.edu } 3775647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 3785647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 3795647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 3805647Sgblack@eecs.umich.edu } 3815647Sgblack@eecs.umich.edu if (reg >= APIC_INTERRUPT_REQUEST(0) && 3825647Sgblack@eecs.umich.edu reg <= APIC_INTERRUPT_REQUEST(15)) { 3835647Sgblack@eecs.umich.edu panic("Local APIC Interrupt Request registers " 3845647Sgblack@eecs.umich.edu "are unimplemented.\n"); 3855647Sgblack@eecs.umich.edu } 3865647Sgblack@eecs.umich.edu switch (reg) { 3875647Sgblack@eecs.umich.edu case APIC_ID: 3885647Sgblack@eecs.umich.edu newVal = val & 0xFF; 3895647Sgblack@eecs.umich.edu break; 3905647Sgblack@eecs.umich.edu case APIC_VERSION: 3915647Sgblack@eecs.umich.edu // The Local APIC Version register is read only. 3925647Sgblack@eecs.umich.edu return; 3935647Sgblack@eecs.umich.edu case APIC_TASK_PRIORITY: 3945647Sgblack@eecs.umich.edu newVal = val & 0xFF; 3955647Sgblack@eecs.umich.edu break; 3965647Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 3975647Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 3985647Sgblack@eecs.umich.edu break; 3995647Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 4005647Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 4015647Sgblack@eecs.umich.edu break; 4025647Sgblack@eecs.umich.edu case APIC_EOI: 4035690Sgblack@eecs.umich.edu // Remove the interrupt that just completed from the local apic state. 4045690Sgblack@eecs.umich.edu clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 4055690Sgblack@eecs.umich.edu updateISRV(); 4065690Sgblack@eecs.umich.edu return; 4075647Sgblack@eecs.umich.edu case APIC_LOGICAL_DESTINATION: 4085647Sgblack@eecs.umich.edu newVal = val & 0xFF000000; 4095647Sgblack@eecs.umich.edu break; 4105647Sgblack@eecs.umich.edu case APIC_DESTINATION_FORMAT: 4115647Sgblack@eecs.umich.edu newVal = val | 0x0FFFFFFF; 4125647Sgblack@eecs.umich.edu break; 4135647Sgblack@eecs.umich.edu case APIC_SPURIOUS_INTERRUPT_VECTOR: 4145647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1); 4155647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= val & (1 << 8); 4165647Sgblack@eecs.umich.edu if (val & (1 << 9)) 4175647Sgblack@eecs.umich.edu warn("Focus processor checking not implemented.\n"); 4185647Sgblack@eecs.umich.edu break; 4195647Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 4205647Sgblack@eecs.umich.edu { 4215647Sgblack@eecs.umich.edu if (regs[APIC_INTERNAL_STATE] & 0x1) { 4225647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 4235647Sgblack@eecs.umich.edu newVal = 0; 4245647Sgblack@eecs.umich.edu } else { 4255647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= ULL(0x1); 4265647Sgblack@eecs.umich.edu return; 4275647Sgblack@eecs.umich.edu } 4285647Sgblack@eecs.umich.edu 4295647Sgblack@eecs.umich.edu } 4305647Sgblack@eecs.umich.edu break; 4315647Sgblack@eecs.umich.edu case APIC_INTERRUPT_COMMAND_LOW: 4325647Sgblack@eecs.umich.edu panic("Local APIC Interrupt Command low" 4335647Sgblack@eecs.umich.edu " register unimplemented.\n"); 4345647Sgblack@eecs.umich.edu break; 4355647Sgblack@eecs.umich.edu case APIC_INTERRUPT_COMMAND_HIGH: 4365647Sgblack@eecs.umich.edu panic("Local APIC Interrupt Command high" 4375647Sgblack@eecs.umich.edu " register unimplemented.\n"); 4385647Sgblack@eecs.umich.edu break; 4395647Sgblack@eecs.umich.edu case APIC_LVT_TIMER: 4405647Sgblack@eecs.umich.edu case APIC_LVT_THERMAL_SENSOR: 4415647Sgblack@eecs.umich.edu case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS: 4425647Sgblack@eecs.umich.edu case APIC_LVT_LINT0: 4435647Sgblack@eecs.umich.edu case APIC_LVT_LINT1: 4445647Sgblack@eecs.umich.edu case APIC_LVT_ERROR: 4455647Sgblack@eecs.umich.edu { 4465647Sgblack@eecs.umich.edu uint64_t readOnlyMask = (1 << 12) | (1 << 14); 4475647Sgblack@eecs.umich.edu newVal = (val & ~readOnlyMask) | 4485647Sgblack@eecs.umich.edu (regs[reg] & readOnlyMask); 4495647Sgblack@eecs.umich.edu } 4505647Sgblack@eecs.umich.edu break; 4515647Sgblack@eecs.umich.edu case APIC_INITIAL_COUNT: 4525648Sgblack@eecs.umich.edu { 4535648Sgblack@eecs.umich.edu assert(clock); 4545648Sgblack@eecs.umich.edu newVal = bits(val, 31, 0); 4555848Sgblack@eecs.umich.edu // Compute how many timer ticks we're being programmed for. 4565848Sgblack@eecs.umich.edu uint64_t newCount = newVal * 4575848Sgblack@eecs.umich.edu (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION])); 4585648Sgblack@eecs.umich.edu // Schedule on the edge of the next tick plus the new count. 4595848Sgblack@eecs.umich.edu Tick offset = curTick % clock; 4605648Sgblack@eecs.umich.edu if (offset) { 4615648Sgblack@eecs.umich.edu reschedule(apicTimerEvent, 4625848Sgblack@eecs.umich.edu curTick + (newCount + 1) * clock - offset, true); 4635648Sgblack@eecs.umich.edu } else { 4645648Sgblack@eecs.umich.edu reschedule(apicTimerEvent, 4655848Sgblack@eecs.umich.edu curTick + newCount * clock, true); 4665648Sgblack@eecs.umich.edu } 4675648Sgblack@eecs.umich.edu } 4685647Sgblack@eecs.umich.edu break; 4695647Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 4705647Sgblack@eecs.umich.edu //Local APIC Current Count register is read only. 4715647Sgblack@eecs.umich.edu return; 4725647Sgblack@eecs.umich.edu case APIC_DIVIDE_CONFIGURATION: 4735647Sgblack@eecs.umich.edu newVal = val & 0xB; 4745647Sgblack@eecs.umich.edu break; 4755647Sgblack@eecs.umich.edu default: 4765647Sgblack@eecs.umich.edu break; 4775647Sgblack@eecs.umich.edu } 4785648Sgblack@eecs.umich.edu regs[reg] = newVal; 4795647Sgblack@eecs.umich.edu return; 4805647Sgblack@eecs.umich.edu} 4815647Sgblack@eecs.umich.edu 4825654Sgblack@eecs.umich.edubool 4835704Snate@binkert.orgX86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const 4845654Sgblack@eecs.umich.edu{ 4855654Sgblack@eecs.umich.edu RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS); 4865689Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 4875689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n"); 4885654Sgblack@eecs.umich.edu return true; 4895689Sgblack@eecs.umich.edu } 4905655Sgblack@eecs.umich.edu if (rflags.intf) { 4915689Sgblack@eecs.umich.edu if (pendingExtInt) { 4925689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending external interrupt.\n"); 4935655Sgblack@eecs.umich.edu return true; 4945689Sgblack@eecs.umich.edu } 4955655Sgblack@eecs.umich.edu if (IRRV > ISRV && bits(IRRV, 7, 4) > 4965689Sgblack@eecs.umich.edu bits(regs[APIC_TASK_PRIORITY], 7, 4)) { 4975689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending regular interrupt.\n"); 4985655Sgblack@eecs.umich.edu return true; 4995689Sgblack@eecs.umich.edu } 5005654Sgblack@eecs.umich.edu } 5015654Sgblack@eecs.umich.edu return false; 5025654Sgblack@eecs.umich.edu} 5035654Sgblack@eecs.umich.edu 5045654Sgblack@eecs.umich.eduFault 5055704Snate@binkert.orgX86ISA::Interrupts::getInterrupt(ThreadContext *tc) 5065654Sgblack@eecs.umich.edu{ 5075704Snate@binkert.org assert(checkInterrupts(tc)); 5085655Sgblack@eecs.umich.edu // These are all probably fairly uncommon, so we'll make them easier to 5095655Sgblack@eecs.umich.edu // check for. 5105655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 5115655Sgblack@eecs.umich.edu if (pendingSmi) { 5125689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated SMI fault object.\n"); 5135655Sgblack@eecs.umich.edu return new SystemManagementInterrupt(); 5145655Sgblack@eecs.umich.edu } else if (pendingNmi) { 5155689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated NMI fault object.\n"); 5165691Sgblack@eecs.umich.edu return new NonMaskableInterrupt(nmiVector); 5175655Sgblack@eecs.umich.edu } else if (pendingInit) { 5185689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated INIT fault object.\n"); 5195691Sgblack@eecs.umich.edu return new InitInterrupt(initVector); 5205655Sgblack@eecs.umich.edu } else { 5215655Sgblack@eecs.umich.edu panic("pendingUnmaskableInt set, but no unmaskable " 5225655Sgblack@eecs.umich.edu "ints were pending.\n"); 5235655Sgblack@eecs.umich.edu return NoFault; 5245655Sgblack@eecs.umich.edu } 5255655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 5265689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated external interrupt fault object.\n"); 5275691Sgblack@eecs.umich.edu return new ExternalInterrupt(extIntVector); 5285655Sgblack@eecs.umich.edu } else { 5295689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated regular interrupt fault object.\n"); 5305655Sgblack@eecs.umich.edu // The only thing left are fixed and lowest priority interrupts. 5315655Sgblack@eecs.umich.edu return new ExternalInterrupt(IRRV); 5325655Sgblack@eecs.umich.edu } 5335654Sgblack@eecs.umich.edu} 5345654Sgblack@eecs.umich.edu 5355654Sgblack@eecs.umich.eduvoid 5365704Snate@binkert.orgX86ISA::Interrupts::updateIntrInfo(ThreadContext *tc) 5375654Sgblack@eecs.umich.edu{ 5385704Snate@binkert.org assert(checkInterrupts(tc)); 5395655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 5405655Sgblack@eecs.umich.edu if (pendingSmi) { 5415689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "SMI sent to core.\n"); 5425655Sgblack@eecs.umich.edu pendingSmi = false; 5435655Sgblack@eecs.umich.edu } else if (pendingNmi) { 5445689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "NMI sent to core.\n"); 5455655Sgblack@eecs.umich.edu pendingNmi = false; 5465655Sgblack@eecs.umich.edu } else if (pendingInit) { 5475689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Init sent to core.\n"); 5485655Sgblack@eecs.umich.edu pendingInit = false; 5495655Sgblack@eecs.umich.edu } 5505655Sgblack@eecs.umich.edu if (!(pendingSmi || pendingNmi || pendingInit)) 5515655Sgblack@eecs.umich.edu pendingUnmaskableInt = false; 5525655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 5535655Sgblack@eecs.umich.edu pendingExtInt = false; 5545655Sgblack@eecs.umich.edu } else { 5555689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV); 5565655Sgblack@eecs.umich.edu // Mark the interrupt as "in service". 5575655Sgblack@eecs.umich.edu ISRV = IRRV; 5585655Sgblack@eecs.umich.edu setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 5595655Sgblack@eecs.umich.edu // Clear it out of the IRR. 5605655Sgblack@eecs.umich.edu clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV); 5615655Sgblack@eecs.umich.edu updateIRRV(); 5625655Sgblack@eecs.umich.edu } 5635654Sgblack@eecs.umich.edu} 5645654Sgblack@eecs.umich.edu 5655647Sgblack@eecs.umich.eduX86ISA::Interrupts * 5665647Sgblack@eecs.umich.eduX86LocalApicParams::create() 5675647Sgblack@eecs.umich.edu{ 5685647Sgblack@eecs.umich.edu return new X86ISA::Interrupts(this); 5695647Sgblack@eecs.umich.edu} 570