interrupts.cc revision 14295
15647Sgblack@eecs.umich.edu/* 29544Sandreas.hansson@arm.com * Copyright (c) 2012-2013 ARM Limited 38922Swilliam.wang@arm.com * All rights reserved 48922Swilliam.wang@arm.com * 58922Swilliam.wang@arm.com * The license below extends only to copyright in the software and shall 68922Swilliam.wang@arm.com * not be construed as granting a license to any other intellectual 78922Swilliam.wang@arm.com * property including but not limited to intellectual property relating 88922Swilliam.wang@arm.com * to a hardware implementation of the functionality of the software 98922Swilliam.wang@arm.com * licensed hereunder. You may use the software subject to the license 108922Swilliam.wang@arm.com * terms below provided that you ensure that this notice is replicated 118922Swilliam.wang@arm.com * unmodified and in its entirety in all distributions of the software, 128922Swilliam.wang@arm.com * modified or unmodified, in source code or in binary form. 138922Swilliam.wang@arm.com * 145647Sgblack@eecs.umich.edu * Copyright (c) 2008 The Hewlett-Packard Development Company 155647Sgblack@eecs.umich.edu * All rights reserved. 165647Sgblack@eecs.umich.edu * 177087Snate@binkert.org * The license below extends only to copyright in the software and shall 187087Snate@binkert.org * not be construed as granting a license to any other intellectual 197087Snate@binkert.org * property including but not limited to intellectual property relating 207087Snate@binkert.org * to a hardware implementation of the functionality of the software 217087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 227087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 237087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 247087Snate@binkert.org * modified or unmodified, in source code or in binary form. 255647Sgblack@eecs.umich.edu * 267087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 277087Snate@binkert.org * modification, are permitted provided that the following conditions are 287087Snate@binkert.org * met: redistributions of source code must retain the above copyright 297087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 307087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 317087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 327087Snate@binkert.org * documentation and/or other materials provided with the distribution; 337087Snate@binkert.org * neither the name of the copyright holders nor the names of its 345647Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 357087Snate@binkert.org * this software without specific prior written permission. 365647Sgblack@eecs.umich.edu * 375647Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 385647Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 395647Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 405647Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 415647Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 425647Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 435647Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 445647Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 455647Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 465647Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 475647Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 485647Sgblack@eecs.umich.edu * 495647Sgblack@eecs.umich.edu * Authors: Gabe Black 505647Sgblack@eecs.umich.edu */ 515647Sgblack@eecs.umich.edu 5211793Sbrandon.potter@amd.com#include "arch/x86/interrupts.hh" 5311793Sbrandon.potter@amd.com 5410474Sandreas.hansson@arm.com#include <memory> 5510474Sandreas.hansson@arm.com 5611793Sbrandon.potter@amd.com#include "arch/x86/intmessage.hh" 578229Snate@binkert.org#include "arch/x86/regs/apic.hh" 585647Sgblack@eecs.umich.edu#include "cpu/base.hh" 598232Snate@binkert.org#include "debug/LocalApic.hh" 606137Sgblack@eecs.umich.edu#include "dev/x86/i82094aa.hh" 616137Sgblack@eecs.umich.edu#include "dev/x86/pc.hh" 626137Sgblack@eecs.umich.edu#include "dev/x86/south_bridge.hh" 635654Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 6411793Sbrandon.potter@amd.com#include "sim/full_system.hh" 656046Sgblack@eecs.umich.edu#include "sim/system.hh" 665647Sgblack@eecs.umich.edu 675648Sgblack@eecs.umich.eduint 685648Sgblack@eecs.umich.edudivideFromConf(uint32_t conf) 695647Sgblack@eecs.umich.edu{ 705647Sgblack@eecs.umich.edu // This figures out what division we want from the division configuration 715647Sgblack@eecs.umich.edu // register in the local APIC. The encoding is a little odd but it can 725647Sgblack@eecs.umich.edu // be deciphered fairly easily. 735647Sgblack@eecs.umich.edu int shift = ((conf & 0x8) >> 1) | (conf & 0x3); 745647Sgblack@eecs.umich.edu shift = (shift + 1) % 8; 755647Sgblack@eecs.umich.edu return 1 << shift; 765647Sgblack@eecs.umich.edu} 775647Sgblack@eecs.umich.edu 785648Sgblack@eecs.umich.edunamespace X86ISA 795647Sgblack@eecs.umich.edu{ 805648Sgblack@eecs.umich.edu 815648Sgblack@eecs.umich.eduApicRegIndex 825648Sgblack@eecs.umich.edudecodeAddr(Addr paddr) 835648Sgblack@eecs.umich.edu{ 845648Sgblack@eecs.umich.edu ApicRegIndex regNum; 855648Sgblack@eecs.umich.edu paddr &= ~mask(3); 865648Sgblack@eecs.umich.edu switch (paddr) 875648Sgblack@eecs.umich.edu { 885648Sgblack@eecs.umich.edu case 0x20: 895648Sgblack@eecs.umich.edu regNum = APIC_ID; 905648Sgblack@eecs.umich.edu break; 915648Sgblack@eecs.umich.edu case 0x30: 925648Sgblack@eecs.umich.edu regNum = APIC_VERSION; 935648Sgblack@eecs.umich.edu break; 945648Sgblack@eecs.umich.edu case 0x80: 955648Sgblack@eecs.umich.edu regNum = APIC_TASK_PRIORITY; 965648Sgblack@eecs.umich.edu break; 975648Sgblack@eecs.umich.edu case 0x90: 985648Sgblack@eecs.umich.edu regNum = APIC_ARBITRATION_PRIORITY; 995648Sgblack@eecs.umich.edu break; 1005648Sgblack@eecs.umich.edu case 0xA0: 1015648Sgblack@eecs.umich.edu regNum = APIC_PROCESSOR_PRIORITY; 1025648Sgblack@eecs.umich.edu break; 1035648Sgblack@eecs.umich.edu case 0xB0: 1045648Sgblack@eecs.umich.edu regNum = APIC_EOI; 1055648Sgblack@eecs.umich.edu break; 1065648Sgblack@eecs.umich.edu case 0xD0: 1075648Sgblack@eecs.umich.edu regNum = APIC_LOGICAL_DESTINATION; 1085648Sgblack@eecs.umich.edu break; 1095648Sgblack@eecs.umich.edu case 0xE0: 1105648Sgblack@eecs.umich.edu regNum = APIC_DESTINATION_FORMAT; 1115648Sgblack@eecs.umich.edu break; 1125648Sgblack@eecs.umich.edu case 0xF0: 1135648Sgblack@eecs.umich.edu regNum = APIC_SPURIOUS_INTERRUPT_VECTOR; 1145648Sgblack@eecs.umich.edu break; 1155648Sgblack@eecs.umich.edu case 0x100: 1165648Sgblack@eecs.umich.edu case 0x110: 1175648Sgblack@eecs.umich.edu case 0x120: 1185648Sgblack@eecs.umich.edu case 0x130: 1195648Sgblack@eecs.umich.edu case 0x140: 1205648Sgblack@eecs.umich.edu case 0x150: 1215648Sgblack@eecs.umich.edu case 0x160: 1225648Sgblack@eecs.umich.edu case 0x170: 12311479Sbaz21@cam.ac.uk regNum = APIC_IN_SERVICE((paddr - 0x100) / 0x10); 1245648Sgblack@eecs.umich.edu break; 1255648Sgblack@eecs.umich.edu case 0x180: 1265648Sgblack@eecs.umich.edu case 0x190: 1275648Sgblack@eecs.umich.edu case 0x1A0: 1285648Sgblack@eecs.umich.edu case 0x1B0: 1295648Sgblack@eecs.umich.edu case 0x1C0: 1305648Sgblack@eecs.umich.edu case 0x1D0: 1315648Sgblack@eecs.umich.edu case 0x1E0: 1325648Sgblack@eecs.umich.edu case 0x1F0: 13311479Sbaz21@cam.ac.uk regNum = APIC_TRIGGER_MODE((paddr - 0x180) / 0x10); 1345648Sgblack@eecs.umich.edu break; 1355648Sgblack@eecs.umich.edu case 0x200: 1365648Sgblack@eecs.umich.edu case 0x210: 1375648Sgblack@eecs.umich.edu case 0x220: 1385648Sgblack@eecs.umich.edu case 0x230: 1395648Sgblack@eecs.umich.edu case 0x240: 1405648Sgblack@eecs.umich.edu case 0x250: 1415648Sgblack@eecs.umich.edu case 0x260: 1425648Sgblack@eecs.umich.edu case 0x270: 14311479Sbaz21@cam.ac.uk regNum = APIC_INTERRUPT_REQUEST((paddr - 0x200) / 0x10); 1445648Sgblack@eecs.umich.edu break; 1455648Sgblack@eecs.umich.edu case 0x280: 1465648Sgblack@eecs.umich.edu regNum = APIC_ERROR_STATUS; 1475648Sgblack@eecs.umich.edu break; 1485648Sgblack@eecs.umich.edu case 0x300: 1495648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_LOW; 1505648Sgblack@eecs.umich.edu break; 1515648Sgblack@eecs.umich.edu case 0x310: 1525648Sgblack@eecs.umich.edu regNum = APIC_INTERRUPT_COMMAND_HIGH; 1535648Sgblack@eecs.umich.edu break; 1545648Sgblack@eecs.umich.edu case 0x320: 1555648Sgblack@eecs.umich.edu regNum = APIC_LVT_TIMER; 1565648Sgblack@eecs.umich.edu break; 1575648Sgblack@eecs.umich.edu case 0x330: 1585648Sgblack@eecs.umich.edu regNum = APIC_LVT_THERMAL_SENSOR; 1595648Sgblack@eecs.umich.edu break; 1605648Sgblack@eecs.umich.edu case 0x340: 1615648Sgblack@eecs.umich.edu regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS; 1625648Sgblack@eecs.umich.edu break; 1635648Sgblack@eecs.umich.edu case 0x350: 1645648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT0; 1655648Sgblack@eecs.umich.edu break; 1665648Sgblack@eecs.umich.edu case 0x360: 1675648Sgblack@eecs.umich.edu regNum = APIC_LVT_LINT1; 1685648Sgblack@eecs.umich.edu break; 1695648Sgblack@eecs.umich.edu case 0x370: 1705648Sgblack@eecs.umich.edu regNum = APIC_LVT_ERROR; 1715648Sgblack@eecs.umich.edu break; 1725648Sgblack@eecs.umich.edu case 0x380: 1735648Sgblack@eecs.umich.edu regNum = APIC_INITIAL_COUNT; 1745648Sgblack@eecs.umich.edu break; 1755648Sgblack@eecs.umich.edu case 0x390: 1765648Sgblack@eecs.umich.edu regNum = APIC_CURRENT_COUNT; 1775648Sgblack@eecs.umich.edu break; 1785648Sgblack@eecs.umich.edu case 0x3E0: 1795648Sgblack@eecs.umich.edu regNum = APIC_DIVIDE_CONFIGURATION; 1805648Sgblack@eecs.umich.edu break; 1815648Sgblack@eecs.umich.edu default: 1825648Sgblack@eecs.umich.edu // A reserved register field. 1835648Sgblack@eecs.umich.edu panic("Accessed reserved register field %#x.\n", paddr); 1845648Sgblack@eecs.umich.edu break; 1855648Sgblack@eecs.umich.edu } 1865648Sgblack@eecs.umich.edu return regNum; 1875648Sgblack@eecs.umich.edu} 1885648Sgblack@eecs.umich.edu} 1895648Sgblack@eecs.umich.edu 1905648Sgblack@eecs.umich.eduTick 1915648Sgblack@eecs.umich.eduX86ISA::Interrupts::read(PacketPtr pkt) 1925648Sgblack@eecs.umich.edu{ 1935648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 19414293Sgabeblack@google.com // Make sure we're at least only accessing one register. 1955648Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 1965648Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 1975648Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 1985648Sgblack@eecs.umich.edu uint32_t val = htog(readReg(reg)); 1995649Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2005649Sgblack@eecs.umich.edu "Reading Local APIC register %d at offset %#x as %#x.\n", 2015649Sgblack@eecs.umich.edu reg, offset, val); 2025648Sgblack@eecs.umich.edu pkt->setData(((uint8_t *)&val) + (offset & mask(3))); 2035898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2049805Sstever@gmail.com return pioDelay; 2055648Sgblack@eecs.umich.edu} 2065648Sgblack@eecs.umich.edu 2075648Sgblack@eecs.umich.eduTick 2085648Sgblack@eecs.umich.eduX86ISA::Interrupts::write(PacketPtr pkt) 2095648Sgblack@eecs.umich.edu{ 2105648Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 21114293Sgabeblack@google.com // Make sure we're at least only accessing one register. 2125648Sgblack@eecs.umich.edu if ((offset & ~mask(3)) != ((offset + pkt->getSize()) & ~mask(3))) 2135648Sgblack@eecs.umich.edu panic("Accessed more than one register at a time in the APIC!\n"); 2145648Sgblack@eecs.umich.edu ApicRegIndex reg = decodeAddr(offset); 2155648Sgblack@eecs.umich.edu uint32_t val = regs[reg]; 2165648Sgblack@eecs.umich.edu pkt->writeData(((uint8_t *)&val) + (offset & mask(3))); 2175649Sgblack@eecs.umich.edu DPRINTF(LocalApic, 2185649Sgblack@eecs.umich.edu "Writing Local APIC register %d at offset %#x as %#x.\n", 2195649Sgblack@eecs.umich.edu reg, offset, gtoh(val)); 2205648Sgblack@eecs.umich.edu setReg(reg, gtoh(val)); 2215898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2229805Sstever@gmail.com return pioDelay; 2235647Sgblack@eecs.umich.edu} 2245691Sgblack@eecs.umich.eduvoid 2255691Sgblack@eecs.umich.eduX86ISA::Interrupts::requestInterrupt(uint8_t vector, 2265691Sgblack@eecs.umich.edu uint8_t deliveryMode, bool level) 2275691Sgblack@eecs.umich.edu{ 2285691Sgblack@eecs.umich.edu /* 2295691Sgblack@eecs.umich.edu * Fixed and lowest-priority delivery mode interrupts are handled 2305691Sgblack@eecs.umich.edu * using the IRR/ISR registers, checking against the TPR, etc. 2315691Sgblack@eecs.umich.edu * The SMI, NMI, ExtInt, INIT, etc interrupts go straight through. 2325691Sgblack@eecs.umich.edu */ 2335691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::Fixed || 2345691Sgblack@eecs.umich.edu deliveryMode == DeliveryMode::LowestPriority) { 2355691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2365691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2375691Sgblack@eecs.umich.edu // Queue up the interrupt in the IRR. 2385691Sgblack@eecs.umich.edu if (vector > IRRV) 2395691Sgblack@eecs.umich.edu IRRV = vector; 2405691Sgblack@eecs.umich.edu if (!getRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector)) { 2415691Sgblack@eecs.umich.edu setRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, vector); 2425691Sgblack@eecs.umich.edu if (level) { 2435691Sgblack@eecs.umich.edu setRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2445691Sgblack@eecs.umich.edu } else { 2455691Sgblack@eecs.umich.edu clearRegArrayBit(APIC_TRIGGER_MODE_BASE, vector); 2465691Sgblack@eecs.umich.edu } 2475691Sgblack@eecs.umich.edu } 2485691Sgblack@eecs.umich.edu } else if (!DeliveryMode::isReserved(deliveryMode)) { 2495691Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt is an %s.\n", 2505691Sgblack@eecs.umich.edu DeliveryMode::names[deliveryMode]); 2515691Sgblack@eecs.umich.edu if (deliveryMode == DeliveryMode::SMI && !pendingSmi) { 2525691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingSmi = true; 2535691Sgblack@eecs.umich.edu smiVector = vector; 2545691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::NMI && !pendingNmi) { 2555691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingNmi = true; 2565691Sgblack@eecs.umich.edu nmiVector = vector; 2575691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::ExtInt && !pendingExtInt) { 2585691Sgblack@eecs.umich.edu pendingExtInt = true; 2595691Sgblack@eecs.umich.edu extIntVector = vector; 2605691Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::INIT && !pendingInit) { 2615691Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingInit = true; 2625691Sgblack@eecs.umich.edu initVector = vector; 2636066Sgblack@eecs.umich.edu } else if (deliveryMode == DeliveryMode::SIPI && 2646066Sgblack@eecs.umich.edu !pendingStartup && !startedUp) { 2656050Sgblack@eecs.umich.edu pendingUnmaskableInt = pendingStartup = true; 2666050Sgblack@eecs.umich.edu startupVector = vector; 2675691Sgblack@eecs.umich.edu } 2688745Sgblack@eecs.umich.edu } 2698781Sgblack@eecs.umich.edu if (FullSystem) 27011151Smitch.hayenga@arm.com cpu->wakeup(0); 2715691Sgblack@eecs.umich.edu} 2725647Sgblack@eecs.umich.edu 2736041Sgblack@eecs.umich.edu 2746041Sgblack@eecs.umich.eduvoid 2756041Sgblack@eecs.umich.eduX86ISA::Interrupts::setCPU(BaseCPU * newCPU) 2766041Sgblack@eecs.umich.edu{ 2776136Sgblack@eecs.umich.edu assert(newCPU); 2786136Sgblack@eecs.umich.edu if (cpu != NULL && cpu->cpuId() != newCPU->cpuId()) { 2796136Sgblack@eecs.umich.edu panic("Local APICs can't be moved between CPUs" 2806136Sgblack@eecs.umich.edu " with different IDs.\n"); 2816136Sgblack@eecs.umich.edu } 2826041Sgblack@eecs.umich.edu cpu = newCPU; 2836136Sgblack@eecs.umich.edu initialApicId = cpu->cpuId(); 2846136Sgblack@eecs.umich.edu regs[APIC_ID] = (initialApicId << 24); 2859090Sandreas.hansson@arm.com pioAddr = x86LocalAPICAddress(initialApicId, 0); 2866041Sgblack@eecs.umich.edu} 2876041Sgblack@eecs.umich.edu 2886041Sgblack@eecs.umich.edu 2896137Sgblack@eecs.umich.eduvoid 2906137Sgblack@eecs.umich.eduX86ISA::Interrupts::init() 2916137Sgblack@eecs.umich.edu{ 2927913SBrad.Beckmann@amd.com // 2939807Sstever@gmail.com // The local apic must register its address ranges on both its pio 2949807Sstever@gmail.com // port via the basicpiodevice(piodevice) init() function and its 2959807Sstever@gmail.com // int port that it inherited from IntDevice. Note IntDevice is 2969807Sstever@gmail.com // not a SimObject itself. 2977913SBrad.Beckmann@amd.com // 29814293Sgabeblack@google.com PioDevice::init(); 2999807Sstever@gmail.com IntDevice::init(); 3008922Swilliam.wang@arm.com 3018922Swilliam.wang@arm.com // the slave port has a range so inform the connected master 3028922Swilliam.wang@arm.com intSlavePort.sendRangeChange(); 3036137Sgblack@eecs.umich.edu} 3046137Sgblack@eecs.umich.edu 3056137Sgblack@eecs.umich.edu 3065651Sgblack@eecs.umich.eduTick 3075651Sgblack@eecs.umich.eduX86ISA::Interrupts::recvMessage(PacketPtr pkt) 3085651Sgblack@eecs.umich.edu{ 3096136Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - x86InterruptAddress(initialApicId, 0); 3105651Sgblack@eecs.umich.edu assert(pkt->cmd == MemCmd::MessageReq); 3115651Sgblack@eecs.umich.edu switch(offset) 3125651Sgblack@eecs.umich.edu { 3135651Sgblack@eecs.umich.edu case 0: 3145654Sgblack@eecs.umich.edu { 31513229Sgabeblack@google.com TriggerIntMessage message = pkt->getRaw<TriggerIntMessage>(); 3165654Sgblack@eecs.umich.edu DPRINTF(LocalApic, 3175654Sgblack@eecs.umich.edu "Got Trigger Interrupt message with vector %#x.\n", 3185697Snate@binkert.org message.vector); 3195655Sgblack@eecs.umich.edu 3205691Sgblack@eecs.umich.edu requestInterrupt(message.vector, 3215691Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 3225654Sgblack@eecs.umich.edu } 3235651Sgblack@eecs.umich.edu break; 3245651Sgblack@eecs.umich.edu default: 3255651Sgblack@eecs.umich.edu panic("Local apic got unknown interrupt message at offset %#x.\n", 3265651Sgblack@eecs.umich.edu offset); 3275651Sgblack@eecs.umich.edu break; 3285651Sgblack@eecs.umich.edu } 3296064Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 3309805Sstever@gmail.com return pioDelay; 3315651Sgblack@eecs.umich.edu} 3325651Sgblack@eecs.umich.edu 3335651Sgblack@eecs.umich.edu 33414295Sgabeblack@google.combool 3356065Sgblack@eecs.umich.eduX86ISA::Interrupts::recvResponse(PacketPtr pkt) 3366065Sgblack@eecs.umich.edu{ 3376065Sgblack@eecs.umich.edu assert(!pkt->isError()); 3386065Sgblack@eecs.umich.edu assert(pkt->cmd == MemCmd::MessageResp); 3396069Sgblack@eecs.umich.edu if (--pendingIPIs == 0) { 3406069Sgblack@eecs.umich.edu InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 3416069Sgblack@eecs.umich.edu // Record that the ICR is now idle. 3426069Sgblack@eecs.umich.edu low.deliveryStatus = 0; 3436069Sgblack@eecs.umich.edu regs[APIC_INTERRUPT_COMMAND_LOW] = low; 3446069Sgblack@eecs.umich.edu } 3456065Sgblack@eecs.umich.edu DPRINTF(LocalApic, "ICR is now idle.\n"); 34614295Sgabeblack@google.com return true; 3476065Sgblack@eecs.umich.edu} 3486065Sgblack@eecs.umich.edu 3496065Sgblack@eecs.umich.edu 3508711Sandreas.hansson@arm.comAddrRangeList 35114293Sgabeblack@google.comX86ISA::Interrupts::getAddrRanges() const 35214293Sgabeblack@google.com{ 35314293Sgabeblack@google.com assert(cpu); 35414293Sgabeblack@google.com AddrRangeList ranges; 35514293Sgabeblack@google.com ranges.push_back(RangeSize(pioAddr, PageBytes)); 35614293Sgabeblack@google.com return ranges; 35714293Sgabeblack@google.com} 35814293Sgabeblack@google.com 35914293Sgabeblack@google.com 36014293Sgabeblack@google.comAddrRangeList 3619090Sandreas.hansson@arm.comX86ISA::Interrupts::getIntAddrRange() const 3626041Sgblack@eecs.umich.edu{ 3638711Sandreas.hansson@arm.com AddrRangeList ranges; 3648711Sandreas.hansson@arm.com ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0), 3658711Sandreas.hansson@arm.com x86InterruptAddress(initialApicId, 0) + 3668711Sandreas.hansson@arm.com PhysAddrAPICRangeSize)); 3678711Sandreas.hansson@arm.com return ranges; 3686041Sgblack@eecs.umich.edu} 3696041Sgblack@eecs.umich.edu 3706041Sgblack@eecs.umich.edu 3715647Sgblack@eecs.umich.eduuint32_t 3725648Sgblack@eecs.umich.eduX86ISA::Interrupts::readReg(ApicRegIndex reg) 3735647Sgblack@eecs.umich.edu{ 3745647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 3755647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 3765647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 3775647Sgblack@eecs.umich.edu } 3785647Sgblack@eecs.umich.edu switch (reg) { 3795647Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 3805647Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 3815647Sgblack@eecs.umich.edu break; 3825647Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 3835647Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 3845647Sgblack@eecs.umich.edu break; 3855647Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 3865647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 3875647Sgblack@eecs.umich.edu break; 3885647Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 3895647Sgblack@eecs.umich.edu { 3905848Sgblack@eecs.umich.edu if (apicTimerEvent.scheduled()) { 3915848Sgblack@eecs.umich.edu // Compute how many m5 ticks happen per count. 3929544Sandreas.hansson@arm.com uint64_t ticksPerCount = clockPeriod() * 3935848Sgblack@eecs.umich.edu divideFromConf(regs[APIC_DIVIDE_CONFIGURATION]); 3945848Sgblack@eecs.umich.edu // Compute how many m5 ticks are left. 3957823Ssteve.reinhardt@amd.com uint64_t val = apicTimerEvent.when() - curTick(); 3965848Sgblack@eecs.umich.edu // Turn that into a count. 3975848Sgblack@eecs.umich.edu val = (val + ticksPerCount - 1) / ticksPerCount; 3985848Sgblack@eecs.umich.edu return val; 3995848Sgblack@eecs.umich.edu } else { 4005848Sgblack@eecs.umich.edu return 0; 4015848Sgblack@eecs.umich.edu } 4025647Sgblack@eecs.umich.edu } 4035647Sgblack@eecs.umich.edu default: 4045647Sgblack@eecs.umich.edu break; 4055647Sgblack@eecs.umich.edu } 4065648Sgblack@eecs.umich.edu return regs[reg]; 4075647Sgblack@eecs.umich.edu} 4085647Sgblack@eecs.umich.edu 4095647Sgblack@eecs.umich.eduvoid 4105648Sgblack@eecs.umich.eduX86ISA::Interrupts::setReg(ApicRegIndex reg, uint32_t val) 4115647Sgblack@eecs.umich.edu{ 4125647Sgblack@eecs.umich.edu uint32_t newVal = val; 4135647Sgblack@eecs.umich.edu if (reg >= APIC_IN_SERVICE(0) && 4145647Sgblack@eecs.umich.edu reg <= APIC_IN_SERVICE(15)) { 4155647Sgblack@eecs.umich.edu panic("Local APIC In-Service registers are unimplemented.\n"); 4165647Sgblack@eecs.umich.edu } 4175647Sgblack@eecs.umich.edu if (reg >= APIC_TRIGGER_MODE(0) && 4185647Sgblack@eecs.umich.edu reg <= APIC_TRIGGER_MODE(15)) { 4195647Sgblack@eecs.umich.edu panic("Local APIC Trigger Mode registers are unimplemented.\n"); 4205647Sgblack@eecs.umich.edu } 4215647Sgblack@eecs.umich.edu if (reg >= APIC_INTERRUPT_REQUEST(0) && 4225647Sgblack@eecs.umich.edu reg <= APIC_INTERRUPT_REQUEST(15)) { 4235647Sgblack@eecs.umich.edu panic("Local APIC Interrupt Request registers " 4245647Sgblack@eecs.umich.edu "are unimplemented.\n"); 4255647Sgblack@eecs.umich.edu } 4265647Sgblack@eecs.umich.edu switch (reg) { 4275647Sgblack@eecs.umich.edu case APIC_ID: 4285647Sgblack@eecs.umich.edu newVal = val & 0xFF; 4295647Sgblack@eecs.umich.edu break; 4305647Sgblack@eecs.umich.edu case APIC_VERSION: 4315647Sgblack@eecs.umich.edu // The Local APIC Version register is read only. 4325647Sgblack@eecs.umich.edu return; 4335647Sgblack@eecs.umich.edu case APIC_TASK_PRIORITY: 4345647Sgblack@eecs.umich.edu newVal = val & 0xFF; 4355647Sgblack@eecs.umich.edu break; 4365647Sgblack@eecs.umich.edu case APIC_ARBITRATION_PRIORITY: 4375647Sgblack@eecs.umich.edu panic("Local APIC Arbitration Priority register unimplemented.\n"); 4385647Sgblack@eecs.umich.edu break; 4395647Sgblack@eecs.umich.edu case APIC_PROCESSOR_PRIORITY: 4405647Sgblack@eecs.umich.edu panic("Local APIC Processor Priority register unimplemented.\n"); 4415647Sgblack@eecs.umich.edu break; 4425647Sgblack@eecs.umich.edu case APIC_EOI: 4435690Sgblack@eecs.umich.edu // Remove the interrupt that just completed from the local apic state. 4445690Sgblack@eecs.umich.edu clearRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 4455690Sgblack@eecs.umich.edu updateISRV(); 4465690Sgblack@eecs.umich.edu return; 4475647Sgblack@eecs.umich.edu case APIC_LOGICAL_DESTINATION: 4485647Sgblack@eecs.umich.edu newVal = val & 0xFF000000; 4495647Sgblack@eecs.umich.edu break; 4505647Sgblack@eecs.umich.edu case APIC_DESTINATION_FORMAT: 4515647Sgblack@eecs.umich.edu newVal = val | 0x0FFFFFFF; 4525647Sgblack@eecs.umich.edu break; 4535647Sgblack@eecs.umich.edu case APIC_SPURIOUS_INTERRUPT_VECTOR: 4545647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(1 << 1); 4555647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= val & (1 << 8); 4565647Sgblack@eecs.umich.edu if (val & (1 << 9)) 4575647Sgblack@eecs.umich.edu warn("Focus processor checking not implemented.\n"); 4585647Sgblack@eecs.umich.edu break; 4595647Sgblack@eecs.umich.edu case APIC_ERROR_STATUS: 4605647Sgblack@eecs.umich.edu { 4615647Sgblack@eecs.umich.edu if (regs[APIC_INTERNAL_STATE] & 0x1) { 4625647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] &= ~ULL(0x1); 4635647Sgblack@eecs.umich.edu newVal = 0; 4645647Sgblack@eecs.umich.edu } else { 4655647Sgblack@eecs.umich.edu regs[APIC_INTERNAL_STATE] |= ULL(0x1); 4665647Sgblack@eecs.umich.edu return; 4675647Sgblack@eecs.umich.edu } 4685647Sgblack@eecs.umich.edu 4695647Sgblack@eecs.umich.edu } 4705647Sgblack@eecs.umich.edu break; 4715647Sgblack@eecs.umich.edu case APIC_INTERRUPT_COMMAND_LOW: 4726046Sgblack@eecs.umich.edu { 4736046Sgblack@eecs.umich.edu InterruptCommandRegLow low = regs[APIC_INTERRUPT_COMMAND_LOW]; 4746046Sgblack@eecs.umich.edu // Check if we're already sending an IPI. 4756046Sgblack@eecs.umich.edu if (low.deliveryStatus) { 4766046Sgblack@eecs.umich.edu newVal = low; 4776046Sgblack@eecs.umich.edu break; 4786046Sgblack@eecs.umich.edu } 4796046Sgblack@eecs.umich.edu low = val; 4806046Sgblack@eecs.umich.edu InterruptCommandRegHigh high = regs[APIC_INTERRUPT_COMMAND_HIGH]; 4816712Snate@binkert.org TriggerIntMessage message = 0; 4826046Sgblack@eecs.umich.edu message.destination = high.destination; 4836046Sgblack@eecs.umich.edu message.vector = low.vector; 4846046Sgblack@eecs.umich.edu message.deliveryMode = low.deliveryMode; 4856046Sgblack@eecs.umich.edu message.destMode = low.destMode; 4866046Sgblack@eecs.umich.edu message.level = low.level; 4876046Sgblack@eecs.umich.edu message.trigger = low.trigger; 4886138Sgblack@eecs.umich.edu ApicList apics; 4896138Sgblack@eecs.umich.edu int numContexts = sys->numContexts(); 4906046Sgblack@eecs.umich.edu switch (low.destShorthand) { 4916046Sgblack@eecs.umich.edu case 0: 4926138Sgblack@eecs.umich.edu if (message.deliveryMode == DeliveryMode::LowestPriority) { 4936138Sgblack@eecs.umich.edu panic("Lowest priority delivery mode " 4946138Sgblack@eecs.umich.edu "IPIs aren't implemented.\n"); 4956138Sgblack@eecs.umich.edu } 4966138Sgblack@eecs.umich.edu if (message.destMode == 1) { 4976138Sgblack@eecs.umich.edu int dest = message.destination; 4986138Sgblack@eecs.umich.edu hack_once("Assuming logical destinations are 1 << id.\n"); 4996138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 5006138Sgblack@eecs.umich.edu if (dest & 0x1) 5016138Sgblack@eecs.umich.edu apics.push_back(i); 5026138Sgblack@eecs.umich.edu dest = dest >> 1; 5036138Sgblack@eecs.umich.edu } 5046138Sgblack@eecs.umich.edu } else { 5056138Sgblack@eecs.umich.edu if (message.destination == 0xFF) { 5066138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 5076138Sgblack@eecs.umich.edu if (i == initialApicId) { 5086138Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5096138Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5106138Sgblack@eecs.umich.edu } else { 5116138Sgblack@eecs.umich.edu apics.push_back(i); 5126138Sgblack@eecs.umich.edu } 5136138Sgblack@eecs.umich.edu } 5146138Sgblack@eecs.umich.edu } else { 5156138Sgblack@eecs.umich.edu if (message.destination == initialApicId) { 5166138Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5176138Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5186138Sgblack@eecs.umich.edu } else { 5196138Sgblack@eecs.umich.edu apics.push_back(message.destination); 5206138Sgblack@eecs.umich.edu } 5216138Sgblack@eecs.umich.edu } 5226138Sgblack@eecs.umich.edu } 5236046Sgblack@eecs.umich.edu break; 5246046Sgblack@eecs.umich.edu case 1: 5256069Sgblack@eecs.umich.edu newVal = val; 5266069Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5276069Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5286046Sgblack@eecs.umich.edu break; 5296046Sgblack@eecs.umich.edu case 2: 5306069Sgblack@eecs.umich.edu requestInterrupt(message.vector, 5316069Sgblack@eecs.umich.edu message.deliveryMode, message.trigger); 5326069Sgblack@eecs.umich.edu // Fall through 5336046Sgblack@eecs.umich.edu case 3: 5346069Sgblack@eecs.umich.edu { 5356069Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 5366138Sgblack@eecs.umich.edu if (i != initialApicId) { 5376138Sgblack@eecs.umich.edu apics.push_back(i); 5386069Sgblack@eecs.umich.edu } 5396069Sgblack@eecs.umich.edu } 5406069Sgblack@eecs.umich.edu } 5416046Sgblack@eecs.umich.edu break; 5426046Sgblack@eecs.umich.edu } 54310542Sgabeblack@google.com // Record that an IPI is being sent if one actually is. 54410542Sgabeblack@google.com if (apics.size()) { 54510542Sgabeblack@google.com low.deliveryStatus = 1; 54610542Sgabeblack@google.com pendingIPIs += apics.size(); 54710542Sgabeblack@google.com } 54810542Sgabeblack@google.com regs[APIC_INTERRUPT_COMMAND_LOW] = low; 54910542Sgabeblack@google.com intMasterPort.sendMessage(apics, message, sys->isTimingMode()); 5506138Sgblack@eecs.umich.edu newVal = regs[APIC_INTERRUPT_COMMAND_LOW]; 5516046Sgblack@eecs.umich.edu } 5525647Sgblack@eecs.umich.edu break; 5535647Sgblack@eecs.umich.edu case APIC_LVT_TIMER: 5545647Sgblack@eecs.umich.edu case APIC_LVT_THERMAL_SENSOR: 5555647Sgblack@eecs.umich.edu case APIC_LVT_PERFORMANCE_MONITORING_COUNTERS: 5565647Sgblack@eecs.umich.edu case APIC_LVT_LINT0: 5575647Sgblack@eecs.umich.edu case APIC_LVT_LINT1: 5585647Sgblack@eecs.umich.edu case APIC_LVT_ERROR: 5595647Sgblack@eecs.umich.edu { 5605647Sgblack@eecs.umich.edu uint64_t readOnlyMask = (1 << 12) | (1 << 14); 5615647Sgblack@eecs.umich.edu newVal = (val & ~readOnlyMask) | 5625647Sgblack@eecs.umich.edu (regs[reg] & readOnlyMask); 5635647Sgblack@eecs.umich.edu } 5645647Sgblack@eecs.umich.edu break; 5655647Sgblack@eecs.umich.edu case APIC_INITIAL_COUNT: 5665648Sgblack@eecs.umich.edu { 5675648Sgblack@eecs.umich.edu newVal = bits(val, 31, 0); 5685848Sgblack@eecs.umich.edu // Compute how many timer ticks we're being programmed for. 5695848Sgblack@eecs.umich.edu uint64_t newCount = newVal * 5705848Sgblack@eecs.umich.edu (divideFromConf(regs[APIC_DIVIDE_CONFIGURATION])); 5715648Sgblack@eecs.umich.edu // Schedule on the edge of the next tick plus the new count. 5729544Sandreas.hansson@arm.com Tick offset = curTick() % clockPeriod(); 5735648Sgblack@eecs.umich.edu if (offset) { 5745648Sgblack@eecs.umich.edu reschedule(apicTimerEvent, 5759544Sandreas.hansson@arm.com curTick() + (newCount + 1) * 5769544Sandreas.hansson@arm.com clockPeriod() - offset, true); 5775648Sgblack@eecs.umich.edu } else { 5789623Snilay@cs.wisc.edu if (newCount) 5799623Snilay@cs.wisc.edu reschedule(apicTimerEvent, 5809623Snilay@cs.wisc.edu curTick() + newCount * 5819623Snilay@cs.wisc.edu clockPeriod(), true); 5825648Sgblack@eecs.umich.edu } 5835648Sgblack@eecs.umich.edu } 5845647Sgblack@eecs.umich.edu break; 5855647Sgblack@eecs.umich.edu case APIC_CURRENT_COUNT: 5865647Sgblack@eecs.umich.edu //Local APIC Current Count register is read only. 5875647Sgblack@eecs.umich.edu return; 5885647Sgblack@eecs.umich.edu case APIC_DIVIDE_CONFIGURATION: 5895647Sgblack@eecs.umich.edu newVal = val & 0xB; 5905647Sgblack@eecs.umich.edu break; 5915647Sgblack@eecs.umich.edu default: 5925647Sgblack@eecs.umich.edu break; 5935647Sgblack@eecs.umich.edu } 5945648Sgblack@eecs.umich.edu regs[reg] = newVal; 5955647Sgblack@eecs.umich.edu return; 5965647Sgblack@eecs.umich.edu} 5975647Sgblack@eecs.umich.edu 5986041Sgblack@eecs.umich.edu 5999807Sstever@gmail.comX86ISA::Interrupts::Interrupts(Params * p) 60014293Sgabeblack@google.com : PioDevice(p), IntDevice(this, p->int_latency), 60112124Sspwilson2@wisc.edu apicTimerEvent([this]{ processApicTimerEvent(); }, name()), 6029807Sstever@gmail.com pendingSmi(false), smiVector(0), 6039807Sstever@gmail.com pendingNmi(false), nmiVector(0), 6049807Sstever@gmail.com pendingExtInt(false), extIntVector(0), 6059807Sstever@gmail.com pendingInit(false), initVector(0), 6069807Sstever@gmail.com pendingStartup(false), startupVector(0), 6079807Sstever@gmail.com startedUp(false), pendingUnmaskableInt(false), 6089807Sstever@gmail.com pendingIPIs(0), cpu(NULL), 60914293Sgabeblack@google.com intSlavePort(name() + ".int_slave", this, this), 61014293Sgabeblack@google.com pioDelay(p->pio_latency) 6116041Sgblack@eecs.umich.edu{ 6126041Sgblack@eecs.umich.edu memset(regs, 0, sizeof(regs)); 6136041Sgblack@eecs.umich.edu //Set the local apic DFR to the flat model. 6146041Sgblack@eecs.umich.edu regs[APIC_DESTINATION_FORMAT] = (uint32_t)(-1); 6156041Sgblack@eecs.umich.edu ISRV = 0; 6166041Sgblack@eecs.umich.edu IRRV = 0; 6176041Sgblack@eecs.umich.edu} 6186041Sgblack@eecs.umich.edu 6196041Sgblack@eecs.umich.edu 6205654Sgblack@eecs.umich.edubool 6215704Snate@binkert.orgX86ISA::Interrupts::checkInterrupts(ThreadContext *tc) const 6225654Sgblack@eecs.umich.edu{ 6235654Sgblack@eecs.umich.edu RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS); 6245689Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6255689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending unmaskable interrupt.\n"); 6265654Sgblack@eecs.umich.edu return true; 6275689Sgblack@eecs.umich.edu } 6285655Sgblack@eecs.umich.edu if (rflags.intf) { 6295689Sgblack@eecs.umich.edu if (pendingExtInt) { 6305689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending external interrupt.\n"); 6315655Sgblack@eecs.umich.edu return true; 6325689Sgblack@eecs.umich.edu } 6335655Sgblack@eecs.umich.edu if (IRRV > ISRV && bits(IRRV, 7, 4) > 6345689Sgblack@eecs.umich.edu bits(regs[APIC_TASK_PRIORITY], 7, 4)) { 6355689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Reported pending regular interrupt.\n"); 6365655Sgblack@eecs.umich.edu return true; 6375689Sgblack@eecs.umich.edu } 6385654Sgblack@eecs.umich.edu } 6395654Sgblack@eecs.umich.edu return false; 6405654Sgblack@eecs.umich.edu} 6415654Sgblack@eecs.umich.edu 6429874Sandreas@sandberg.pp.sebool 6439874Sandreas@sandberg.pp.seX86ISA::Interrupts::checkInterruptsRaw() const 6449874Sandreas@sandberg.pp.se{ 6459874Sandreas@sandberg.pp.se return pendingUnmaskableInt || pendingExtInt || 6469874Sandreas@sandberg.pp.se (IRRV > ISRV && bits(IRRV, 7, 4) > 6479874Sandreas@sandberg.pp.se bits(regs[APIC_TASK_PRIORITY], 7, 4)); 6489874Sandreas@sandberg.pp.se} 6499874Sandreas@sandberg.pp.se 6505654Sgblack@eecs.umich.eduFault 6515704Snate@binkert.orgX86ISA::Interrupts::getInterrupt(ThreadContext *tc) 6525654Sgblack@eecs.umich.edu{ 6535704Snate@binkert.org assert(checkInterrupts(tc)); 6545655Sgblack@eecs.umich.edu // These are all probably fairly uncommon, so we'll make them easier to 6555655Sgblack@eecs.umich.edu // check for. 6565655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6575655Sgblack@eecs.umich.edu if (pendingSmi) { 6585689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated SMI fault object.\n"); 65910474Sandreas.hansson@arm.com return std::make_shared<SystemManagementInterrupt>(); 6605655Sgblack@eecs.umich.edu } else if (pendingNmi) { 6615689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated NMI fault object.\n"); 66210474Sandreas.hansson@arm.com return std::make_shared<NonMaskableInterrupt>(nmiVector); 6635655Sgblack@eecs.umich.edu } else if (pendingInit) { 6645689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated INIT fault object.\n"); 66510474Sandreas.hansson@arm.com return std::make_shared<InitInterrupt>(initVector); 6666050Sgblack@eecs.umich.edu } else if (pendingStartup) { 6676050Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generating SIPI fault object.\n"); 66810474Sandreas.hansson@arm.com return std::make_shared<StartupInterrupt>(startupVector); 6695655Sgblack@eecs.umich.edu } else { 6705655Sgblack@eecs.umich.edu panic("pendingUnmaskableInt set, but no unmaskable " 6715655Sgblack@eecs.umich.edu "ints were pending.\n"); 6725655Sgblack@eecs.umich.edu return NoFault; 6735655Sgblack@eecs.umich.edu } 6745655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 6755689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated external interrupt fault object.\n"); 67610474Sandreas.hansson@arm.com return std::make_shared<ExternalInterrupt>(extIntVector); 6775655Sgblack@eecs.umich.edu } else { 6785689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Generated regular interrupt fault object.\n"); 6795655Sgblack@eecs.umich.edu // The only thing left are fixed and lowest priority interrupts. 68010474Sandreas.hansson@arm.com return std::make_shared<ExternalInterrupt>(IRRV); 6815655Sgblack@eecs.umich.edu } 6825654Sgblack@eecs.umich.edu} 6835654Sgblack@eecs.umich.edu 6845654Sgblack@eecs.umich.eduvoid 6855704Snate@binkert.orgX86ISA::Interrupts::updateIntrInfo(ThreadContext *tc) 6865654Sgblack@eecs.umich.edu{ 6875704Snate@binkert.org assert(checkInterrupts(tc)); 6885655Sgblack@eecs.umich.edu if (pendingUnmaskableInt) { 6895655Sgblack@eecs.umich.edu if (pendingSmi) { 6905689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "SMI sent to core.\n"); 6915655Sgblack@eecs.umich.edu pendingSmi = false; 6925655Sgblack@eecs.umich.edu } else if (pendingNmi) { 6935689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "NMI sent to core.\n"); 6945655Sgblack@eecs.umich.edu pendingNmi = false; 6955655Sgblack@eecs.umich.edu } else if (pendingInit) { 6965689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Init sent to core.\n"); 6975655Sgblack@eecs.umich.edu pendingInit = false; 6986066Sgblack@eecs.umich.edu startedUp = false; 6996050Sgblack@eecs.umich.edu } else if (pendingStartup) { 7006050Sgblack@eecs.umich.edu DPRINTF(LocalApic, "SIPI sent to core.\n"); 7016050Sgblack@eecs.umich.edu pendingStartup = false; 7026066Sgblack@eecs.umich.edu startedUp = true; 7035655Sgblack@eecs.umich.edu } 7046050Sgblack@eecs.umich.edu if (!(pendingSmi || pendingNmi || pendingInit || pendingStartup)) 7055655Sgblack@eecs.umich.edu pendingUnmaskableInt = false; 7065655Sgblack@eecs.umich.edu } else if (pendingExtInt) { 7075655Sgblack@eecs.umich.edu pendingExtInt = false; 7085655Sgblack@eecs.umich.edu } else { 7095689Sgblack@eecs.umich.edu DPRINTF(LocalApic, "Interrupt %d sent to core.\n", IRRV); 7105655Sgblack@eecs.umich.edu // Mark the interrupt as "in service". 7115655Sgblack@eecs.umich.edu ISRV = IRRV; 7125655Sgblack@eecs.umich.edu setRegArrayBit(APIC_IN_SERVICE_BASE, ISRV); 7135655Sgblack@eecs.umich.edu // Clear it out of the IRR. 7145655Sgblack@eecs.umich.edu clearRegArrayBit(APIC_INTERRUPT_REQUEST_BASE, IRRV); 7155655Sgblack@eecs.umich.edu updateIRRV(); 7165655Sgblack@eecs.umich.edu } 7175654Sgblack@eecs.umich.edu} 7185654Sgblack@eecs.umich.edu 7197902Shestness@cs.utexas.eduvoid 72010905Sandreas.sandberg@arm.comX86ISA::Interrupts::serialize(CheckpointOut &cp) const 7217902Shestness@cs.utexas.edu{ 7227902Shestness@cs.utexas.edu SERIALIZE_ARRAY(regs, NUM_APIC_REGS); 7237902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingSmi); 7247902Shestness@cs.utexas.edu SERIALIZE_SCALAR(smiVector); 7257902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingNmi); 7267902Shestness@cs.utexas.edu SERIALIZE_SCALAR(nmiVector); 7277902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingExtInt); 7287902Shestness@cs.utexas.edu SERIALIZE_SCALAR(extIntVector); 7297902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingInit); 7307902Shestness@cs.utexas.edu SERIALIZE_SCALAR(initVector); 7317902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingStartup); 7327902Shestness@cs.utexas.edu SERIALIZE_SCALAR(startupVector); 7337902Shestness@cs.utexas.edu SERIALIZE_SCALAR(startedUp); 7347902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingUnmaskableInt); 7357902Shestness@cs.utexas.edu SERIALIZE_SCALAR(pendingIPIs); 7367902Shestness@cs.utexas.edu SERIALIZE_SCALAR(IRRV); 7377902Shestness@cs.utexas.edu SERIALIZE_SCALAR(ISRV); 7387902Shestness@cs.utexas.edu bool apicTimerEventScheduled = apicTimerEvent.scheduled(); 7397902Shestness@cs.utexas.edu SERIALIZE_SCALAR(apicTimerEventScheduled); 7407902Shestness@cs.utexas.edu Tick apicTimerEventTick = apicTimerEvent.when(); 7417902Shestness@cs.utexas.edu SERIALIZE_SCALAR(apicTimerEventTick); 7427902Shestness@cs.utexas.edu} 7437902Shestness@cs.utexas.edu 7447902Shestness@cs.utexas.eduvoid 74510905Sandreas.sandberg@arm.comX86ISA::Interrupts::unserialize(CheckpointIn &cp) 7467902Shestness@cs.utexas.edu{ 7477902Shestness@cs.utexas.edu UNSERIALIZE_ARRAY(regs, NUM_APIC_REGS); 7487902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingSmi); 7497902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(smiVector); 7507902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingNmi); 7517902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(nmiVector); 7527902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingExtInt); 7537902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(extIntVector); 7547902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingInit); 7557902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(initVector); 7567902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingStartup); 7577902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(startupVector); 7587902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(startedUp); 7597902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingUnmaskableInt); 7607902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(pendingIPIs); 7617902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(IRRV); 7627902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(ISRV); 7637902Shestness@cs.utexas.edu bool apicTimerEventScheduled; 7647902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(apicTimerEventScheduled); 7657902Shestness@cs.utexas.edu if (apicTimerEventScheduled) { 7667902Shestness@cs.utexas.edu Tick apicTimerEventTick; 7677902Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(apicTimerEventTick); 7687902Shestness@cs.utexas.edu if (apicTimerEvent.scheduled()) { 7697902Shestness@cs.utexas.edu reschedule(apicTimerEvent, apicTimerEventTick, true); 7707902Shestness@cs.utexas.edu } else { 7717902Shestness@cs.utexas.edu schedule(apicTimerEvent, apicTimerEventTick); 7727902Shestness@cs.utexas.edu } 7737902Shestness@cs.utexas.edu } 7747902Shestness@cs.utexas.edu} 7757902Shestness@cs.utexas.edu 7765647Sgblack@eecs.umich.eduX86ISA::Interrupts * 7775647Sgblack@eecs.umich.eduX86LocalApicParams::create() 7785647Sgblack@eecs.umich.edu{ 7795647Sgblack@eecs.umich.edu return new X86ISA::Interrupts(this); 7805647Sgblack@eecs.umich.edu} 78112124Sspwilson2@wisc.edu 78212124Sspwilson2@wisc.eduvoid 78312124Sspwilson2@wisc.eduX86ISA::Interrupts::processApicTimerEvent() { 78412124Sspwilson2@wisc.edu if (triggerTimerInterrupt()) 78512124Sspwilson2@wisc.edu setReg(APIC_INITIAL_COUNT, readReg(APIC_INITIAL_COUNT)); 78612124Sspwilson2@wisc.edu} 787