ua2005.cc revision 2650
12650Ssaidi@eecs.umich.edu/* 22650Ssaidi@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 32650Ssaidi@eecs.umich.edu * All rights reserved. 42650Ssaidi@eecs.umich.edu * 52650Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 62650Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 72650Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 82650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 92650Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 102650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 112650Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 122650Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 132650Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 142650Ssaidi@eecs.umich.edu * this software without specific prior written permission. 152650Ssaidi@eecs.umich.edu * 162650Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172650Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182650Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192650Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202650Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212650Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222650Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232650Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242650Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252650Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262650Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272650Ssaidi@eecs.umich.edu */ 282650Ssaidi@eecs.umich.edu 292650Ssaidi@eecs.umich.edu#include "arch/sparc/regfile.hh" 302650Ssaidi@eecs.umich.edu 312650Ssaidi@eecs.umich.eduFault 322650Ssaidi@eecs.umich.eduSparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, 332650Ssaidi@eecs.umich.edu ExecContext *xc) 342650Ssaidi@eecs.umich.edu{ 352650Ssaidi@eecs.umich.edu int64_t time; 362650Ssaidi@eecs.umich.edu SparcSystem *sys; 372650Ssaidi@eecs.umich.edu switch (miscReg) { 382650Ssaidi@eecs.umich.edu /** Full system only ASRs */ 392650Ssaidi@eecs.umich.edu case MISCREG_SOFTINT: 402650Ssaidi@eecs.umich.edu if (isNonPriv()) 412650Ssaidi@eecs.umich.edu return new PrivilegedOpcode; 422650Ssaidi@eecs.umich.edu // Check if we are going to interrupt because of something 432650Ssaidi@eecs.umich.edu int oldLevel = InterruptLevel(softint); 442650Ssaidi@eecs.umich.edu int newLevel = InterruptLevel(val); 452650Ssaidi@eecs.umich.edu setReg(miscReg, val); 462650Ssaidi@eecs.umich.edu if (newLevel > oldLevel) 472650Ssaidi@eecs.umich.edu ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 482650Ssaidi@eecs.umich.edu //xc->getCpuPtr()->checkInterrupts = true; 492650Ssaidi@eecs.umich.edu return NoFault; 502650Ssaidi@eecs.umich.edu 512650Ssaidi@eecs.umich.edu case MISCREG_SOFTINT_CLR: 522650Ssaidi@eecs.umich.edu return setRegWithEffect(miscReg, ~val & softint, xc); 532650Ssaidi@eecs.umich.edu case MISCREG_SOFTINT_SET: 542650Ssaidi@eecs.umich.edu return setRegWithEffect(miscReg, val | softint, xc); 552650Ssaidi@eecs.umich.edu 562650Ssaidi@eecs.umich.edu case MISCREG_TICK_CMPR: 572650Ssaidi@eecs.umich.edu if (isNonPriv()) 582650Ssaidi@eecs.umich.edu return new PrivilegedOpcode; 592650Ssaidi@eecs.umich.edu setReg(miscReg, val); 602650Ssaidi@eecs.umich.edu if (tick_cmprFields.int_dis && tickCompare.scheduled()) 612650Ssaidi@eecs.umich.edu tickCompare.deschedule(); 622650Ssaidi@eecs.umich.edu time = tick_cmprFields.tick_cmpr - tickFields.counter; 632650Ssaidi@eecs.umich.edu if (!tick_cmprFields.int_dis && time > 0) 642650Ssaidi@eecs.umich.edu tickCompare.schedule(time * xc->getCpuPtr()->cycles(1)); 652650Ssaidi@eecs.umich.edu return NoFault; 662650Ssaidi@eecs.umich.edu 672650Ssaidi@eecs.umich.edu case MISCREG_STICK: 682650Ssaidi@eecs.umich.edu if (isNonPriv()) 692650Ssaidi@eecs.umich.edu return new PrivilegedOpcode; 702650Ssaidi@eecs.umich.edu if (isPriv()) 712650Ssaidi@eecs.umich.edu return new PrivilegedAction; 722650Ssaidi@eecs.umich.edu sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr()); 732650Ssaidi@eecs.umich.edu assert(sys != NULL); 742650Ssaidi@eecs.umich.edu sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64; 752650Ssaidi@eecs.umich.edu stickFields.npt = val & Bit64 ? 1 : 0; 762650Ssaidi@eecs.umich.edu return NoFault; 772650Ssaidi@eecs.umich.edu 782650Ssaidi@eecs.umich.edu case MISCREG_STICK_CMPR: 792650Ssaidi@eecs.umich.edu if (isNonPriv()) 802650Ssaidi@eecs.umich.edu return new PrivilegedOpcode; 812650Ssaidi@eecs.umich.edu sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr()); 822650Ssaidi@eecs.umich.edu assert(sys != NULL); 832650Ssaidi@eecs.umich.edu setReg(miscReg, val); 842650Ssaidi@eecs.umich.edu if (stick_cmprFields.int_dis && sTickCompare.scheduled()) 852650Ssaidi@eecs.umich.edu sTickCompare.deschedule(); 862650Ssaidi@eecs.umich.edu time = stick_cmprFields.tick_cmpr - sys->sysTick; 872650Ssaidi@eecs.umich.edu if (!stick_cmprFields.int_dis && time > 0) 882650Ssaidi@eecs.umich.edu sTickCompare.schedule(time * Clock::Int::ns); 892650Ssaidi@eecs.umich.edu return NoFault; 902650Ssaidi@eecs.umich.edu 912650Ssaidi@eecs.umich.edu /** Fullsystem only Priv registers. */ 922650Ssaidi@eecs.umich.edu case MISCREG_PIL: 932650Ssaidi@eecs.umich.edu if (FULL_SYSTEM) { 942650Ssaidi@eecs.umich.edu setReg(miscReg, val); 952650Ssaidi@eecs.umich.edu //xc->getCpuPtr()->checkInterrupts; 962650Ssaidi@eecs.umich.edu // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 972650Ssaidi@eecs.umich.edu return NoFault; 982650Ssaidi@eecs.umich.edu } else 992650Ssaidi@eecs.umich.edu panic("PIL not implemented for syscall emulation\n"); 1002650Ssaidi@eecs.umich.edu 1012650Ssaidi@eecs.umich.edu /** Hyper privileged registers */ 1022650Ssaidi@eecs.umich.edu case MISCREG_HPSTATE: 1032650Ssaidi@eecs.umich.edu case MISCREG_HINTP: 1042650Ssaidi@eecs.umich.edu setReg(miscReg, val); 1052650Ssaidi@eecs.umich.edu return NoFault; 1062650Ssaidi@eecs.umich.edu case MISCREG_HTSTATE: 1072650Ssaidi@eecs.umich.edu if (tl == 0) 1082650Ssaidi@eecs.umich.edu return new IllegalInstruction; 1092650Ssaidi@eecs.umich.edu setReg(miscReg, val); 1102650Ssaidi@eecs.umich.edu return NoFault; 1112650Ssaidi@eecs.umich.edu 1122650Ssaidi@eecs.umich.edu case MISCREG_HTBA: 1132650Ssaidi@eecs.umich.edu // clear lower 7 bits on writes. 1142650Ssaidi@eecs.umich.edu setReg(miscReg, val & ULL(~0x7FFF)); 1152650Ssaidi@eecs.umich.edu return NoFault; 1162650Ssaidi@eecs.umich.edu 1172650Ssaidi@eecs.umich.edu case MISCREG_STRAND_STS_REG: 1182650Ssaidi@eecs.umich.edu setReg(miscReg, strandStatusReg); 1192650Ssaidi@eecs.umich.edu return NoFault; 1202650Ssaidi@eecs.umich.edu case MISCREG_HSTICK_CMPR: 1212650Ssaidi@eecs.umich.edu if (isNonPriv()) 1222650Ssaidi@eecs.umich.edu return new PrivilegedOpcode; 1232650Ssaidi@eecs.umich.edu sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr()); 1242650Ssaidi@eecs.umich.edu assert(sys != NULL); 1252650Ssaidi@eecs.umich.edu setReg(miscReg, val); 1262650Ssaidi@eecs.umich.edu if (hstick_cmprFields.int_dis && hSTickCompare.scheduled()) 1272650Ssaidi@eecs.umich.edu hSTickCompare.deschedule(); 1282650Ssaidi@eecs.umich.edu int64_t time = hstick_cmprFields.tick_cmpr - sys->sysTick; 1292650Ssaidi@eecs.umich.edu if (!hstick_cmprFields.int_dis && time > 0) 1302650Ssaidi@eecs.umich.edu hSTickCompare.schedule(time * Clock::Int::ns); 1312650Ssaidi@eecs.umich.edu return NoFault; 1322650Ssaidi@eecs.umich.edu default: 1332650Ssaidi@eecs.umich.edu return new IllegalInstruction; 1342650Ssaidi@eecs.umich.edu } 1352650Ssaidi@eecs.umich.edu} 1362650Ssaidi@eecs.umich.edu 1372650Ssaidi@eecs.umich.eduMiscReg 1382650Ssaidi@eecs.umich.eduMiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ExecContext * xc) 1392650Ssaidi@eecs.umich.edu{ 1402650Ssaidi@eecs.umich.edu switch (miscReg) { 1412650Ssaidi@eecs.umich.edu 1422650Ssaidi@eecs.umich.edu /** Privileged registers. */ 1432650Ssaidi@eecs.umich.edu case MISCREG_SOFTINT: 1442650Ssaidi@eecs.umich.edu if (isNonPriv()) { 1452650Ssaidi@eecs.umich.edu fault = new PrivilegedOpcode; 1462650Ssaidi@eecs.umich.edu return 0; 1472650Ssaidi@eecs.umich.edu } 1482650Ssaidi@eecs.umich.edu return readReg(miscReg); 1492650Ssaidi@eecs.umich.edu case MISCREG_TICK_CMPR: 1502650Ssaidi@eecs.umich.edu if (isNonPriv()) { 1512650Ssaidi@eecs.umich.edu fault = new PrivilegedOpcode; 1522650Ssaidi@eecs.umich.edu return 0; 1532650Ssaidi@eecs.umich.edu } 1542650Ssaidi@eecs.umich.edu return readReg(miscReg); 1552650Ssaidi@eecs.umich.edu case MISCREG_STICK: 1562650Ssaidi@eecs.umich.edu SparcSystem *sys; 1572650Ssaidi@eecs.umich.edu if (stickFields.npt && !isNonPriv()) { 1582650Ssaidi@eecs.umich.edu fault = new PrivilegedAction; 1592650Ssaidi@eecs.umich.edu return 0; 1602650Ssaidi@eecs.umich.edu } 1612650Ssaidi@eecs.umich.edu sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr()); 1622650Ssaidi@eecs.umich.edu assert(sys != NULL); 1632650Ssaidi@eecs.umich.edu return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63; 1642650Ssaidi@eecs.umich.edu case MISCREG_STICK_CMPR: 1652650Ssaidi@eecs.umich.edu if (isNonPriv()) { 1662650Ssaidi@eecs.umich.edu fault = new PrivilegedOpcode; 1672650Ssaidi@eecs.umich.edu return 0; 1682650Ssaidi@eecs.umich.edu } 1692650Ssaidi@eecs.umich.edu return readReg(miscReg); 1702650Ssaidi@eecs.umich.edu 1712650Ssaidi@eecs.umich.edu 1722650Ssaidi@eecs.umich.edu /** Hyper privileged registers */ 1732650Ssaidi@eecs.umich.edu case MISCREG_HPSTATE: 1742650Ssaidi@eecs.umich.edu case MISCREG_HINTP: 1752650Ssaidi@eecs.umich.edu return readReg(miscReg); 1762650Ssaidi@eecs.umich.edu case MISCREG_HTSTATE: 1772650Ssaidi@eecs.umich.edu if (tl == 0) { 1782650Ssaidi@eecs.umich.edu fault = new IllegalInstruction; 1792650Ssaidi@eecs.umich.edu return 0; 1802650Ssaidi@eecs.umich.edu } 1812650Ssaidi@eecs.umich.edu return readReg(miscReg); 1822650Ssaidi@eecs.umich.edu 1832650Ssaidi@eecs.umich.edu case MISCREG_HTBA: 1842650Ssaidi@eecs.umich.edu return readReg(miscReg) & ULL(~0x7FFF); 1852650Ssaidi@eecs.umich.edu case MISCREG_HVER: 1862650Ssaidi@eecs.umich.edu return NWindows | MaxTL << 8 | MaxGL << 16; 1872650Ssaidi@eecs.umich.edu case MISCREG_STRAND_STS_REG: 1882650Ssaidi@eecs.umich.edu return strandStatusReg; 1892650Ssaidi@eecs.umich.edu case MISCREG_HSTICK_CMPR: 1902650Ssaidi@eecs.umich.edu return hstick_cmpr; 1912650Ssaidi@eecs.umich.edu 1922650Ssaidi@eecs.umich.edu default: 1932650Ssaidi@eecs.umich.edu fault = new IllegalInstruction; 1942650Ssaidi@eecs.umich.edu return 0; 1952650Ssaidi@eecs.umich.edu } 1962650Ssaidi@eecs.umich.edu} 1972650Ssaidi@eecs.umich.edu 1982650Ssaidi@eecs.umich.edu 1992650Ssaidi@eecs.umich.edu}; // namespace SparcISA 200