ua2005.cc revision 2650
1/* 2 * Copyright (c) 2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include "arch/sparc/regfile.hh" 30 31Fault 32SparcISA::MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val, 33 ExecContext *xc) 34{ 35 int64_t time; 36 SparcSystem *sys; 37 switch (miscReg) { 38 /** Full system only ASRs */ 39 case MISCREG_SOFTINT: 40 if (isNonPriv()) 41 return new PrivilegedOpcode; 42 // Check if we are going to interrupt because of something 43 int oldLevel = InterruptLevel(softint); 44 int newLevel = InterruptLevel(val); 45 setReg(miscReg, val); 46 if (newLevel > oldLevel) 47 ; // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 48 //xc->getCpuPtr()->checkInterrupts = true; 49 return NoFault; 50 51 case MISCREG_SOFTINT_CLR: 52 return setRegWithEffect(miscReg, ~val & softint, xc); 53 case MISCREG_SOFTINT_SET: 54 return setRegWithEffect(miscReg, val | softint, xc); 55 56 case MISCREG_TICK_CMPR: 57 if (isNonPriv()) 58 return new PrivilegedOpcode; 59 setReg(miscReg, val); 60 if (tick_cmprFields.int_dis && tickCompare.scheduled()) 61 tickCompare.deschedule(); 62 time = tick_cmprFields.tick_cmpr - tickFields.counter; 63 if (!tick_cmprFields.int_dis && time > 0) 64 tickCompare.schedule(time * xc->getCpuPtr()->cycles(1)); 65 return NoFault; 66 67 case MISCREG_STICK: 68 if (isNonPriv()) 69 return new PrivilegedOpcode; 70 if (isPriv()) 71 return new PrivilegedAction; 72 sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr()); 73 assert(sys != NULL); 74 sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64; 75 stickFields.npt = val & Bit64 ? 1 : 0; 76 return NoFault; 77 78 case MISCREG_STICK_CMPR: 79 if (isNonPriv()) 80 return new PrivilegedOpcode; 81 sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr()); 82 assert(sys != NULL); 83 setReg(miscReg, val); 84 if (stick_cmprFields.int_dis && sTickCompare.scheduled()) 85 sTickCompare.deschedule(); 86 time = stick_cmprFields.tick_cmpr - sys->sysTick; 87 if (!stick_cmprFields.int_dis && time > 0) 88 sTickCompare.schedule(time * Clock::Int::ns); 89 return NoFault; 90 91 /** Fullsystem only Priv registers. */ 92 case MISCREG_PIL: 93 if (FULL_SYSTEM) { 94 setReg(miscReg, val); 95 //xc->getCpuPtr()->checkInterrupts; 96 // MUST DO SOMETHING HERE TO TELL CPU TO LOOK FOR INTERRUPTS XXX 97 return NoFault; 98 } else 99 panic("PIL not implemented for syscall emulation\n"); 100 101 /** Hyper privileged registers */ 102 case MISCREG_HPSTATE: 103 case MISCREG_HINTP: 104 setReg(miscReg, val); 105 return NoFault; 106 case MISCREG_HTSTATE: 107 if (tl == 0) 108 return new IllegalInstruction; 109 setReg(miscReg, val); 110 return NoFault; 111 112 case MISCREG_HTBA: 113 // clear lower 7 bits on writes. 114 setReg(miscReg, val & ULL(~0x7FFF)); 115 return NoFault; 116 117 case MISCREG_STRAND_STS_REG: 118 setReg(miscReg, strandStatusReg); 119 return NoFault; 120 case MISCREG_HSTICK_CMPR: 121 if (isNonPriv()) 122 return new PrivilegedOpcode; 123 sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr()); 124 assert(sys != NULL); 125 setReg(miscReg, val); 126 if (hstick_cmprFields.int_dis && hSTickCompare.scheduled()) 127 hSTickCompare.deschedule(); 128 int64_t time = hstick_cmprFields.tick_cmpr - sys->sysTick; 129 if (!hstick_cmprFields.int_dis && time > 0) 130 hSTickCompare.schedule(time * Clock::Int::ns); 131 return NoFault; 132 default: 133 return new IllegalInstruction; 134 } 135} 136 137MiscReg 138MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ExecContext * xc) 139{ 140 switch (miscReg) { 141 142 /** Privileged registers. */ 143 case MISCREG_SOFTINT: 144 if (isNonPriv()) { 145 fault = new PrivilegedOpcode; 146 return 0; 147 } 148 return readReg(miscReg); 149 case MISCREG_TICK_CMPR: 150 if (isNonPriv()) { 151 fault = new PrivilegedOpcode; 152 return 0; 153 } 154 return readReg(miscReg); 155 case MISCREG_STICK: 156 SparcSystem *sys; 157 if (stickFields.npt && !isNonPriv()) { 158 fault = new PrivilegedAction; 159 return 0; 160 } 161 sys = dynamic_cast<SparcSystem*>(xc->getSystemPtr()); 162 assert(sys != NULL); 163 return curTick/Clock::Int::ns - sys->sysTick | stickFields.npt << 63; 164 case MISCREG_STICK_CMPR: 165 if (isNonPriv()) { 166 fault = new PrivilegedOpcode; 167 return 0; 168 } 169 return readReg(miscReg); 170 171 172 /** Hyper privileged registers */ 173 case MISCREG_HPSTATE: 174 case MISCREG_HINTP: 175 return readReg(miscReg); 176 case MISCREG_HTSTATE: 177 if (tl == 0) { 178 fault = new IllegalInstruction; 179 return 0; 180 } 181 return readReg(miscReg); 182 183 case MISCREG_HTBA: 184 return readReg(miscReg) & ULL(~0x7FFF); 185 case MISCREG_HVER: 186 return NWindows | MaxTL << 8 | MaxGL << 16; 187 case MISCREG_STRAND_STS_REG: 188 return strandStatusReg; 189 case MISCREG_HSTICK_CMPR: 190 return hstick_cmpr; 191 192 default: 193 fault = new IllegalInstruction; 194 return 0; 195 } 196} 197 198 199}; // namespace SparcISA 200