ua2005.cc revision 13912
12650Ssaidi@eecs.umich.edu/* 22650Ssaidi@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 32650Ssaidi@eecs.umich.edu * All rights reserved. 42650Ssaidi@eecs.umich.edu * 52650Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 62650Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 72650Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 82650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 92650Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 102650Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 112650Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 122650Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 132650Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 142650Ssaidi@eecs.umich.edu * this software without specific prior written permission. 152650Ssaidi@eecs.umich.edu * 162650Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172650Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182650Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192650Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202650Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212650Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222650Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232650Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242650Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252650Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262650Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272650Ssaidi@eecs.umich.edu */ 282650Ssaidi@eecs.umich.edu 2913912Sgabeblack@google.com#include "arch/sparc/interrupts.hh" 306335Sgblack@eecs.umich.edu#include "arch/sparc/isa.hh" 314194Ssaidi@eecs.umich.edu#include "arch/sparc/kernel_stats.hh" 326335Sgblack@eecs.umich.edu#include "arch/sparc/registers.hh" 333817Ssaidi@eecs.umich.edu#include "base/bitfield.hh" 343817Ssaidi@eecs.umich.edu#include "base/trace.hh" 353817Ssaidi@eecs.umich.edu#include "cpu/base.hh" 363817Ssaidi@eecs.umich.edu#include "cpu/thread_context.hh" 378232Snate@binkert.org#include "debug/Quiesce.hh" 388232Snate@binkert.org#include "debug/Timer.hh" 3911793Sbrandon.potter@amd.com#include "sim/full_system.hh" 404194Ssaidi@eecs.umich.edu#include "sim/system.hh" 412650Ssaidi@eecs.umich.edu 423817Ssaidi@eecs.umich.eduusing namespace SparcISA; 435946Sgblack@eecs.umich.eduusing namespace std; 443817Ssaidi@eecs.umich.edu 454103Ssaidi@eecs.umich.edu 464103Ssaidi@eecs.umich.eduvoid 476335Sgblack@eecs.umich.eduISA::checkSoftInt(ThreadContext *tc) 484103Ssaidi@eecs.umich.edu{ 495531Snate@binkert.org BaseCPU *cpu = tc->getCpuPtr(); 505531Snate@binkert.org 514103Ssaidi@eecs.umich.edu // If PIL < 14, copy over the tm and sm bits 524103Ssaidi@eecs.umich.edu if (pil < 14 && softint & 0x10000) 5311150Smitch.hayenga@arm.com cpu->postInterrupt(0, IT_SOFT_INT, 16); 544103Ssaidi@eecs.umich.edu else 5511150Smitch.hayenga@arm.com cpu->clearInterrupt(0, IT_SOFT_INT, 16); 564103Ssaidi@eecs.umich.edu if (pil < 14 && softint & 0x1) 5711150Smitch.hayenga@arm.com cpu->postInterrupt(0, IT_SOFT_INT, 0); 584103Ssaidi@eecs.umich.edu else 5911150Smitch.hayenga@arm.com cpu->clearInterrupt(0, IT_SOFT_INT, 0); 604103Ssaidi@eecs.umich.edu 614103Ssaidi@eecs.umich.edu // Copy over any of the other bits that are set 624103Ssaidi@eecs.umich.edu for (int bit = 15; bit > 0; --bit) { 634103Ssaidi@eecs.umich.edu if (1 << bit & softint && bit > pil) 6411150Smitch.hayenga@arm.com cpu->postInterrupt(0, IT_SOFT_INT, bit); 654103Ssaidi@eecs.umich.edu else 6611150Smitch.hayenga@arm.com cpu->clearInterrupt(0, IT_SOFT_INT, bit); 674103Ssaidi@eecs.umich.edu } 684103Ssaidi@eecs.umich.edu} 694103Ssaidi@eecs.umich.edu 707741Sgblack@eecs.umich.edu// These functions map register indices to names 715946Sgblack@eecs.umich.edustatic inline string 725946Sgblack@eecs.umich.edugetMiscRegName(RegIndex index) 735946Sgblack@eecs.umich.edu{ 745946Sgblack@eecs.umich.edu static string miscRegName[NumMiscRegs] = 755946Sgblack@eecs.umich.edu {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic", 765946Sgblack@eecs.umich.edu "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr", 775946Sgblack@eecs.umich.edu "stick", "stick_cmpr", 785946Sgblack@eecs.umich.edu "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl", 795946Sgblack@eecs.umich.edu "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin", 805946Sgblack@eecs.umich.edu "wstate",*/ "gl", 815946Sgblack@eecs.umich.edu "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg", 825946Sgblack@eecs.umich.edu "hstick_cmpr", 835946Sgblack@eecs.umich.edu "fsr", "prictx", "secctx", "partId", "lsuCtrlReg", 845946Sgblack@eecs.umich.edu "scratch0", "scratch1", "scratch2", "scratch3", "scratch4", 855946Sgblack@eecs.umich.edu "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail", 865946Sgblack@eecs.umich.edu "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail", 875946Sgblack@eecs.umich.edu "nresErrorHead", "nresErrorTail", "TlbData" }; 885946Sgblack@eecs.umich.edu return miscRegName[index]; 895946Sgblack@eecs.umich.edu} 904103Ssaidi@eecs.umich.edu 913817Ssaidi@eecs.umich.eduvoid 9213583Sgabeblack@google.comISA::setFSReg(int miscReg, RegVal val, ThreadContext *tc) 932650Ssaidi@eecs.umich.edu{ 945531Snate@binkert.org BaseCPU *cpu = tc->getCpuPtr(); 955531Snate@binkert.org 962650Ssaidi@eecs.umich.edu int64_t time; 972650Ssaidi@eecs.umich.edu switch (miscReg) { 982982Sstever@eecs.umich.edu /* Full system only ASRs */ 993919Shsul@eecs.umich.edu case MISCREG_SOFTINT: 1006335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val);; 1014103Ssaidi@eecs.umich.edu checkSoftInt(tc); 1023919Shsul@eecs.umich.edu break; 1033919Shsul@eecs.umich.edu case MISCREG_SOFTINT_CLR: 1046335Sgblack@eecs.umich.edu return setMiscReg(MISCREG_SOFTINT, ~val & softint, tc); 1053919Shsul@eecs.umich.edu case MISCREG_SOFTINT_SET: 1066335Sgblack@eecs.umich.edu return setMiscReg(MISCREG_SOFTINT, val | softint, tc); 1072650Ssaidi@eecs.umich.edu 1083919Shsul@eecs.umich.edu case MISCREG_TICK_CMPR: 1093919Shsul@eecs.umich.edu if (tickCompare == NULL) 1103919Shsul@eecs.umich.edu tickCompare = new TickCompareEvent(this, tc); 1116335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1124103Ssaidi@eecs.umich.edu if ((tick_cmpr & ~mask(63)) && tickCompare->scheduled()) 1135606Snate@binkert.org cpu->deschedule(tickCompare); 1143919Shsul@eecs.umich.edu time = (tick_cmpr & mask(63)) - (tick & mask(63)); 1154103Ssaidi@eecs.umich.edu if (!(tick_cmpr & ~mask(63)) && time > 0) { 1164103Ssaidi@eecs.umich.edu if (tickCompare->scheduled()) 1175606Snate@binkert.org cpu->deschedule(tickCompare); 1189180Sandreas.hansson@arm.com cpu->schedule(tickCompare, cpu->clockEdge(Cycles(time))); 1194103Ssaidi@eecs.umich.edu } 12011102Spalle@lyckegaard.dk DPRINTF(Timer, "writing to TICK compare register value %#X\n", val); 1213919Shsul@eecs.umich.edu break; 1222650Ssaidi@eecs.umich.edu 1233919Shsul@eecs.umich.edu case MISCREG_STICK_CMPR: 1243919Shsul@eecs.umich.edu if (sTickCompare == NULL) 1253919Shsul@eecs.umich.edu sTickCompare = new STickCompareEvent(this, tc); 1266335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1273919Shsul@eecs.umich.edu if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled()) 1285606Snate@binkert.org cpu->deschedule(sTickCompare); 1293919Shsul@eecs.umich.edu time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 1305531Snate@binkert.org cpu->instCount(); 1314103Ssaidi@eecs.umich.edu if (!(stick_cmpr & ~mask(63)) && time > 0) { 1324103Ssaidi@eecs.umich.edu if (sTickCompare->scheduled()) 1335606Snate@binkert.org cpu->deschedule(sTickCompare); 1349180Sandreas.hansson@arm.com cpu->schedule(sTickCompare, cpu->clockEdge(Cycles(time))); 1354103Ssaidi@eecs.umich.edu } 1363919Shsul@eecs.umich.edu DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val); 1373919Shsul@eecs.umich.edu break; 1382650Ssaidi@eecs.umich.edu 1393919Shsul@eecs.umich.edu case MISCREG_PSTATE: 1406335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 14112620Sgabeblack@google.com break; 1423827Shsul@eecs.umich.edu 1433919Shsul@eecs.umich.edu case MISCREG_PIL: 1446335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1454103Ssaidi@eecs.umich.edu checkSoftInt(tc); 1463919Shsul@eecs.umich.edu break; 1472650Ssaidi@eecs.umich.edu 1483919Shsul@eecs.umich.edu case MISCREG_HVER: 1493919Shsul@eecs.umich.edu panic("Shouldn't be writing HVER\n"); 1502650Ssaidi@eecs.umich.edu 1513921Shsul@eecs.umich.edu case MISCREG_HINTP: 1526335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1534103Ssaidi@eecs.umich.edu if (hintp) 15411150Smitch.hayenga@arm.com cpu->postInterrupt(0, IT_HINTP, 0); 1554103Ssaidi@eecs.umich.edu else 15611150Smitch.hayenga@arm.com cpu->clearInterrupt(0, IT_HINTP, 0); 1574103Ssaidi@eecs.umich.edu break; 1583921Shsul@eecs.umich.edu 1593919Shsul@eecs.umich.edu case MISCREG_HTBA: 1603919Shsul@eecs.umich.edu // clear lower 7 bits on writes. 1616335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val & ULL(~0x7FFF)); 1623919Shsul@eecs.umich.edu break; 1632650Ssaidi@eecs.umich.edu 1643919Shsul@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 1653919Shsul@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 1666335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1674103Ssaidi@eecs.umich.edu if (cpu_mondo_head != cpu_mondo_tail) 16811150Smitch.hayenga@arm.com cpu->postInterrupt(0, IT_CPU_MONDO, 0); 1694103Ssaidi@eecs.umich.edu else 17011150Smitch.hayenga@arm.com cpu->clearInterrupt(0, IT_CPU_MONDO, 0); 1714103Ssaidi@eecs.umich.edu break; 1723919Shsul@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 1733919Shsul@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 1746335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1754103Ssaidi@eecs.umich.edu if (dev_mondo_head != dev_mondo_tail) 17611150Smitch.hayenga@arm.com cpu->postInterrupt(0, IT_DEV_MONDO, 0); 1774103Ssaidi@eecs.umich.edu else 17811150Smitch.hayenga@arm.com cpu->clearInterrupt(0, IT_DEV_MONDO, 0); 1794103Ssaidi@eecs.umich.edu break; 1803919Shsul@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 1813919Shsul@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 1826335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1834103Ssaidi@eecs.umich.edu if (res_error_head != res_error_tail) 18411150Smitch.hayenga@arm.com cpu->postInterrupt(0, IT_RES_ERROR, 0); 1854103Ssaidi@eecs.umich.edu else 18611150Smitch.hayenga@arm.com cpu->clearInterrupt(0, IT_RES_ERROR, 0); 1874103Ssaidi@eecs.umich.edu break; 1883919Shsul@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 1893919Shsul@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 1906335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1914103Ssaidi@eecs.umich.edu // This one doesn't have an interrupt to report to the guest OS 1923919Shsul@eecs.umich.edu break; 1933828Shsul@eecs.umich.edu 1943919Shsul@eecs.umich.edu case MISCREG_HSTICK_CMPR: 1953919Shsul@eecs.umich.edu if (hSTickCompare == NULL) 1963919Shsul@eecs.umich.edu hSTickCompare = new HSTickCompareEvent(this, tc); 1976335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 1983919Shsul@eecs.umich.edu if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled()) 1995606Snate@binkert.org cpu->deschedule(hSTickCompare); 2003919Shsul@eecs.umich.edu time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 2015531Snate@binkert.org cpu->instCount(); 2024103Ssaidi@eecs.umich.edu if (!(hstick_cmpr & ~mask(63)) && time > 0) { 2034103Ssaidi@eecs.umich.edu if (hSTickCompare->scheduled()) 2045606Snate@binkert.org cpu->deschedule(hSTickCompare); 2059180Sandreas.hansson@arm.com cpu->schedule(hSTickCompare, cpu->clockEdge(Cycles(time))); 2064103Ssaidi@eecs.umich.edu } 2073919Shsul@eecs.umich.edu DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val); 2083919Shsul@eecs.umich.edu break; 2093817Ssaidi@eecs.umich.edu 2103919Shsul@eecs.umich.edu case MISCREG_HPSTATE: 2118829Sgblack@eecs.umich.edu { 2128829Sgblack@eecs.umich.edu HPSTATE newVal = val; 2138829Sgblack@eecs.umich.edu newVal.id = 1; 2148829Sgblack@eecs.umich.edu // T1000 spec says impl. dependent val must always be 1 2158829Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, newVal); 2168829Sgblack@eecs.umich.edu newVal = hpstate; 2178829Sgblack@eecs.umich.edu if (newVal.tlz && tl == 0 && !newVal.hpriv) 21811150Smitch.hayenga@arm.com cpu->postInterrupt(0, IT_TRAP_LEVEL_ZERO, 0); 2198829Sgblack@eecs.umich.edu else 22011150Smitch.hayenga@arm.com cpu->clearInterrupt(0, IT_TRAP_LEVEL_ZERO, 0); 2218829Sgblack@eecs.umich.edu break; 2228829Sgblack@eecs.umich.edu } 2233919Shsul@eecs.umich.edu case MISCREG_HTSTATE: 2246335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, val); 2254194Ssaidi@eecs.umich.edu break; 2264194Ssaidi@eecs.umich.edu 2273919Shsul@eecs.umich.edu case MISCREG_STRAND_STS_REG: 2284194Ssaidi@eecs.umich.edu if (bits(val,2,2)) 2294194Ssaidi@eecs.umich.edu panic("No support for setting spec_en bit\n"); 2306335Sgblack@eecs.umich.edu setMiscRegNoEffect(miscReg, bits(val,0,0)); 2314194Ssaidi@eecs.umich.edu if (!bits(val,0,0)) { 2324216Ssaidi@eecs.umich.edu DPRINTF(Quiesce, "Cpu executed quiescing instruction\n"); 2334194Ssaidi@eecs.umich.edu // Time to go to sleep 2344194Ssaidi@eecs.umich.edu tc->suspend(); 2358778Sgblack@eecs.umich.edu if (FullSystem && tc->getKernelStats()) 2364194Ssaidi@eecs.umich.edu tc->getKernelStats()->quiesce(); 2375531Snate@binkert.org } 2383919Shsul@eecs.umich.edu break; 2393817Ssaidi@eecs.umich.edu 2403919Shsul@eecs.umich.edu default: 2415531Snate@binkert.org panic("Invalid write to FS misc register %s\n", 2425531Snate@binkert.org getMiscRegName(miscReg)); 2432650Ssaidi@eecs.umich.edu } 2442650Ssaidi@eecs.umich.edu} 2452650Ssaidi@eecs.umich.edu 24613583Sgabeblack@google.comRegVal 2476335Sgblack@eecs.umich.eduISA::readFSReg(int miscReg, ThreadContext * tc) 2482650Ssaidi@eecs.umich.edu{ 2494194Ssaidi@eecs.umich.edu uint64_t temp; 2504194Ssaidi@eecs.umich.edu 2512650Ssaidi@eecs.umich.edu switch (miscReg) { 2523919Shsul@eecs.umich.edu /* Privileged registers. */ 2533825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_HEAD: 2543825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_CPU_MONDO_TAIL: 2553825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_HEAD: 2563825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_DEV_MONDO_TAIL: 2573825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_HEAD: 2583825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_RES_ERROR_TAIL: 2593825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_HEAD: 2603825Ssaidi@eecs.umich.edu case MISCREG_QUEUE_NRES_ERROR_TAIL: 2613825Ssaidi@eecs.umich.edu case MISCREG_SOFTINT: 2623825Ssaidi@eecs.umich.edu case MISCREG_TICK_CMPR: 2633825Ssaidi@eecs.umich.edu case MISCREG_STICK_CMPR: 2643825Ssaidi@eecs.umich.edu case MISCREG_PIL: 2653825Ssaidi@eecs.umich.edu case MISCREG_HPSTATE: 2663825Ssaidi@eecs.umich.edu case MISCREG_HINTP: 2673825Ssaidi@eecs.umich.edu case MISCREG_HTSTATE: 2683825Ssaidi@eecs.umich.edu case MISCREG_HSTICK_CMPR: 2696335Sgblack@eecs.umich.edu return readMiscRegNoEffect(miscReg) ; 2702650Ssaidi@eecs.umich.edu 2713825Ssaidi@eecs.umich.edu case MISCREG_HTBA: 2726335Sgblack@eecs.umich.edu return readMiscRegNoEffect(miscReg) & ULL(~0x7FFF); 2733825Ssaidi@eecs.umich.edu case MISCREG_HVER: 2744207Ssaidi@eecs.umich.edu // XXX set to match Legion 2754207Ssaidi@eecs.umich.edu return ULL(0x3e) << 48 | 2764207Ssaidi@eecs.umich.edu ULL(0x23) << 32 | 2774207Ssaidi@eecs.umich.edu ULL(0x20) << 24 | 2787741Sgblack@eecs.umich.edu // MaxGL << 16 | XXX For some reason legion doesn't set GL 2794207Ssaidi@eecs.umich.edu MaxTL << 8 | 2804207Ssaidi@eecs.umich.edu (NWindows -1) << 0; 2812650Ssaidi@eecs.umich.edu 2824194Ssaidi@eecs.umich.edu case MISCREG_STRAND_STS_REG: 2834194Ssaidi@eecs.umich.edu System *sys; 2844194Ssaidi@eecs.umich.edu int x; 2854194Ssaidi@eecs.umich.edu sys = tc->getSystemPtr(); 2864194Ssaidi@eecs.umich.edu 2876335Sgblack@eecs.umich.edu temp = readMiscRegNoEffect(miscReg) & (STS::active | STS::speculative); 2885531Snate@binkert.org // Check that the CPU array is fully populated 2895531Snate@binkert.org // (by calling getNumCPus()) 2905720Snate@binkert.org assert(sys->numContexts() > tc->contextId()); 2914194Ssaidi@eecs.umich.edu 2925714Shsul@eecs.umich.edu temp |= tc->contextId() << STS::shft_id; 2934194Ssaidi@eecs.umich.edu 2945714Shsul@eecs.umich.edu for (x = tc->contextId() & ~3; x < sys->threadContexts.size(); x++) { 2954194Ssaidi@eecs.umich.edu switch (sys->threadContexts[x]->status()) { 2964194Ssaidi@eecs.umich.edu case ThreadContext::Active: 2974194Ssaidi@eecs.umich.edu temp |= STS::st_run << (STS::shft_fsm0 - 2984194Ssaidi@eecs.umich.edu ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 2994194Ssaidi@eecs.umich.edu break; 3004194Ssaidi@eecs.umich.edu case ThreadContext::Suspended: 3014194Ssaidi@eecs.umich.edu // should this be idle? 3024194Ssaidi@eecs.umich.edu temp |= STS::st_idle << (STS::shft_fsm0 - 3034194Ssaidi@eecs.umich.edu ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 3044194Ssaidi@eecs.umich.edu break; 3054194Ssaidi@eecs.umich.edu case ThreadContext::Halted: 3064194Ssaidi@eecs.umich.edu temp |= STS::st_halt << (STS::shft_fsm0 - 3074194Ssaidi@eecs.umich.edu ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1))); 3084194Ssaidi@eecs.umich.edu break; 3094194Ssaidi@eecs.umich.edu default: 3104194Ssaidi@eecs.umich.edu panic("What state are we in?!\n"); 3114194Ssaidi@eecs.umich.edu } // switch 3124194Ssaidi@eecs.umich.edu } // for 3134194Ssaidi@eecs.umich.edu 3144194Ssaidi@eecs.umich.edu return temp; 3153825Ssaidi@eecs.umich.edu default: 3163825Ssaidi@eecs.umich.edu panic("Invalid read to FS misc register\n"); 3172650Ssaidi@eecs.umich.edu } 3182650Ssaidi@eecs.umich.edu} 3192650Ssaidi@eecs.umich.edu 3202651Ssaidi@eecs.umich.eduvoid 3216335Sgblack@eecs.umich.eduISA::processTickCompare(ThreadContext *tc) 3222651Ssaidi@eecs.umich.edu{ 3232651Ssaidi@eecs.umich.edu panic("tick compare not implemented\n"); 3242651Ssaidi@eecs.umich.edu} 3252651Ssaidi@eecs.umich.edu 3262651Ssaidi@eecs.umich.eduvoid 3276335Sgblack@eecs.umich.eduISA::processSTickCompare(ThreadContext *tc) 3282651Ssaidi@eecs.umich.edu{ 3295606Snate@binkert.org BaseCPU *cpu = tc->getCpuPtr(); 3305606Snate@binkert.org 3313888Ssaidi@eecs.umich.edu // since our microcode instructions take two cycles we need to check if 3323888Ssaidi@eecs.umich.edu // we're actually at the correct cycle or we need to wait a little while 3333888Ssaidi@eecs.umich.edu // more 3349180Sandreas.hansson@arm.com int delay; 3359180Sandreas.hansson@arm.com delay = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) - 3365606Snate@binkert.org cpu->instCount(); 3379180Sandreas.hansson@arm.com assert(delay >= 0 && "stick compare missed interrupt cycle"); 3383888Ssaidi@eecs.umich.edu 3399180Sandreas.hansson@arm.com if (delay == 0 || tc->status() == ThreadContext::Suspended) { 3403888Ssaidi@eecs.umich.edu DPRINTF(Timer, "STick compare cycle reached at %#x\n", 3413888Ssaidi@eecs.umich.edu (stick_cmpr & mask(63))); 3424172Ssaidi@eecs.umich.edu if (!(tc->readMiscRegNoEffect(MISCREG_STICK_CMPR) & (ULL(1) << 63))) { 3436335Sgblack@eecs.umich.edu setMiscReg(MISCREG_SOFTINT, softint | (ULL(1) << 16), tc); 3443921Shsul@eecs.umich.edu } 3457741Sgblack@eecs.umich.edu } else { 3469180Sandreas.hansson@arm.com cpu->schedule(sTickCompare, cpu->clockEdge(Cycles(delay))); 3477741Sgblack@eecs.umich.edu } 3482651Ssaidi@eecs.umich.edu} 3492651Ssaidi@eecs.umich.edu 3502651Ssaidi@eecs.umich.eduvoid 3516335Sgblack@eecs.umich.eduISA::processHSTickCompare(ThreadContext *tc) 3522651Ssaidi@eecs.umich.edu{ 3535606Snate@binkert.org BaseCPU *cpu = tc->getCpuPtr(); 3545606Snate@binkert.org 3553891Ssaidi@eecs.umich.edu // since our microcode instructions take two cycles we need to check if 3563891Ssaidi@eecs.umich.edu // we're actually at the correct cycle or we need to wait a little while 3573891Ssaidi@eecs.umich.edu // more 3589180Sandreas.hansson@arm.com int delay; 3596029Ssteve.reinhardt@amd.com if ( tc->status() == ThreadContext::Halted) 3604216Ssaidi@eecs.umich.edu return; 3614216Ssaidi@eecs.umich.edu 3629180Sandreas.hansson@arm.com delay = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) - 3635606Snate@binkert.org cpu->instCount(); 3649180Sandreas.hansson@arm.com assert(delay >= 0 && "hstick compare missed interrupt cycle"); 3653891Ssaidi@eecs.umich.edu 3669180Sandreas.hansson@arm.com if (delay == 0 || tc->status() == ThreadContext::Suspended) { 3673891Ssaidi@eecs.umich.edu DPRINTF(Timer, "HSTick compare cycle reached at %#x\n", 3683891Ssaidi@eecs.umich.edu (stick_cmpr & mask(63))); 3694172Ssaidi@eecs.umich.edu if (!(tc->readMiscRegNoEffect(MISCREG_HSTICK_CMPR) & (ULL(1) << 63))) { 3706335Sgblack@eecs.umich.edu setMiscReg(MISCREG_HINTP, 1, tc); 3713921Shsul@eecs.umich.edu } 3723891Ssaidi@eecs.umich.edu // Need to do something to cause interrupt to happen here !!! @todo 3737741Sgblack@eecs.umich.edu } else { 3749180Sandreas.hansson@arm.com cpu->schedule(hSTickCompare, cpu->clockEdge(Cycles(delay))); 3757741Sgblack@eecs.umich.edu } 3762651Ssaidi@eecs.umich.edu} 3772650Ssaidi@eecs.umich.edu 378